diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json new file mode 100644 index 000000000..117681cd1 --- /dev/null +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -0,0 +1,2756 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE256" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "vmovups xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "SVE 128-bit load already zero's the upper bits", + "Spurious move afterwards", + "Map 1 0b00 0x10 128-bit" + ] + }, + "vmovups ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Doesn't load directly in to destination", + "Map 1 0b00 0x10 256-bit" + ] + }, + "vmovupd xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "SVE 128-bit load already zero's the upper bits", + "Spurious move afterwards", + "Map 1 0b01 0x10 128-bit" + ] + }, + "vmovupd ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Doesn't load directly in to destination", + "Map 1 0b01 0x10 256-bit" + ] + }, + "vmovss xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "32-bit vector load already zero's the upper bits", + "Spurious move afterwards", + "Map 1 0b10 0x10 128-bit" + ] + }, + "vmovss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b10 0x10 128-bit" + ] + }, + "vmovsd xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "32-bit vector load already zero's the upper bits", + "Spurious move afterwards", + "Map 1 0b11 0x10 128-bit" + ] + }, + "vmovsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b11 0x10 128-bit" + ] + }, + "vmovups [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x11 128-bit" + ] + }, + "vmovups [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x11 256-bit" + ] + }, + "vmovupd [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x11 128-bit" + ] + }, + "vmovupd [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x11 256-bit" + ] + }, + "vmovss [rax], xmm0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x11 128-bit" + ] + }, + "db 0xc5, 0xf2, 0x11, 0xc2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "vmovss xmm2, xmm1, xmm0", + "Need to manually encode since nasm won't encode this", + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b10 0x11 128-bit" + ] + }, + "vmovsd [rax], xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x11 128-bit" + ] + }, + "db 0xc5, 0xf3, 0x11, 0xc2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "vmovsd xmm2, xmm1, xmm0", + "Need to manually encode since nasm won't encode this", + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b11 0x11 128-bit" + ] + }, + "vmovlps xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b00 0x12 128-bit" + ] + }, + "vmovlpd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b01 0x12 128-bit" + ] + }, + "vmovsldup xmm0, [rax]": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x12 128-bit" + ] + }, + "vmovsldup ymm0, [rax]": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x12 256-bit" + ] + }, + "vmovddup xmm0, [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x12 128-bit" + ] + }, + "vmovddup ymm0, [rax]": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x12 256-bit" + ] + }, + "vmovlps [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x13 128-bit" + ] + }, + "vmovlpd [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x13 128-bit" + ] + }, + "vunpcklps xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x14 128-bit" + ] + }, + "vunpcklps ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x14 256-bit" + ] + }, + "vunpcklpd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x14 128-bit" + ] + }, + "vunpcklpd ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x14 256-bit" + ] + }, + "vunpckhps xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x15 128-bit" + ] + }, + "vunpckhps ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x15 256-bit" + ] + }, + "vunpckhpd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x15 128-bit" + ] + }, + "vunpckhpd ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x15 256-bit" + ] + }, + "vmovhps xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x16 128-bit" + ] + }, + "vmovhpd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x16 128-bit" + ] + }, + "vmovshdup xmm0, [rax]": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x16 128-bit" + ] + }, + "vmovshdup ymm0, [rax]": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x16 256-bit" + ] + }, + "vmovhps [rax], xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x17 128-bit" + ] + }, + "vmovhpd [rax], xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x17 128-bit" + ] + }, + "vmovmskps rax, xmm0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x50 128-bit" + ] + }, + "vmovmskps rax, ymm0": { + "ExpectedInstructionCount": 42, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x50 256-bit" + ] + }, + "vmovmskpd rax, xmm0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x50 128-bit" + ] + }, + "vmovmskpd rax, ymm0": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x50 256-bit" + ] + }, + "vsqrtps xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x51 128-bit" + ] + }, + "vsqrtps ymm0, ymm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x51 256-bit" + ] + }, + "vsqrtpd xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x51 128-bit" + ] + }, + "vsqrtpd ymm0, ymm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x51 256-bit" + ] + }, + "vsqrtss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b10 0x51 128-bit" + ] + }, + "vsqrtsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Insert in to first element could be more optimal, which is the common case.", + "Map 1 0b11 0x51 128-bit" + ] + }, + "vrsqrtps xmm0, xmm1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b00 0x52 128-bit" + ] + }, + "vrsqrtps ymm0, ymm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b00 0x52 256-bit" + ] + }, + "vrsqrtss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b10 0x52 128-bit" + ] + }, + "vrcpps xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b00 0x53 128-bit" + ] + }, + "vrcpps ymm0, ymm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b00 0x53 256-bit" + ] + }, + "vrcpss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "FEAT_FPRES could make this more optimal", + "Map 1 0b10 0x53 128-bit" + ] + }, + "vandps xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x54 128-bit" + ] + }, + "vandps ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x54 256-bit" + ] + }, + "vandpd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x54 128-bit" + ] + }, + "vandpd ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x54 256-bit" + ] + }, + "vandnps xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x55 128-bit" + ] + }, + "vandnps ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x55 256-bit" + ] + }, + "vandnpd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x55 128-bit" + ] + }, + "vandnpd ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x55 256-bit" + ] + }, + "vorps xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x56 128-bit" + ] + }, + "vorps ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x56 256-bit" + ] + }, + "vorpd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x56 128-bit" + ] + }, + "vorpd ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x56 256-bit" + ] + }, + "vxorps xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x57 128-bit" + ] + }, + "vxorps ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x57 256-bit" + ] + }, + "vxorpd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x57 128-bit" + ] + }, + "vxorpd ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x57 256-bit" + ] + }, + "vpunpcklbw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x60 128-bit" + ] + }, + "vpunpcklbw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x60 256-bit" + ] + }, + "vpunpcklwd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x61 128-bit" + ] + }, + "vpunpcklwd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x61 256-bit" + ] + }, + "vpunpckldq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x62 128-bit" + ] + }, + "vpunpckldq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x62 256-bit" + ] + }, + "vpacksswb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x63 128-bit" + ] + }, + "vpacksswb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x63 256-bit" + ] + }, + "vpcmpgtb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x64 128-bit" + ] + }, + "vpcmpgtb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x64 256-bit" + ] + }, + "vpcmpgtw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x65 128-bit" + ] + }, + "vpcmpgtw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x65 256-bit" + ] + }, + "vpcmpgtd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x66 128-bit" + ] + }, + "vpcmpgtd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x66 256-bit" + ] + }, + "vpackuswb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x67 128-bit" + ] + }, + "vpackuswb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x67 256-bit" + ] + }, + "vpshufd xmm0, xmm1, 00b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 128-bit" + ] + }, + "vpshufd xmm0, xmm1, 01b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 128-bit" + ] + }, + "vpshufd xmm0, xmm1, 10b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 128-bit" + ] + }, + "vpshufd xmm0, xmm1, 11b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 128-bit" + ] + }, + "vpshufd ymm0, ymm1, 00b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 256-bit" + ] + }, + "vpshufd ymm0, ymm1, 01b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 256-bit" + ] + }, + "vpshufd ymm0, ymm1, 10b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 256-bit" + ] + }, + "vpshufd ymm0, ymm1, 11b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x70 256-bit" + ] + }, + "vpshufhw xmm0, xmm1, 00b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 128-bit" + ] + }, + "vpshufhw xmm0, xmm1, 01b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 128-bit" + ] + }, + "vpshufhw xmm0, xmm1, 10b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 128-bit" + ] + }, + "vpshufhw xmm0, xmm1, 11b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 128-bit" + ] + }, + "vpshufhw ymm0, ymm1, 00b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 256-bit" + ] + }, + "vpshufhw ymm0, ymm1, 01b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 256-bit" + ] + }, + "vpshufhw ymm0, ymm1, 10b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 256-bit" + ] + }, + "vpshufhw ymm0, ymm1, 11b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x70 256-bit" + ] + }, + "vpshuflw xmm0, xmm1, 00b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 128-bit" + ] + }, + "vpshuflw xmm0, xmm1, 01b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 128-bit" + ] + }, + "vpshuflw xmm0, xmm1, 10b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 128-bit" + ] + }, + "vpshuflw xmm0, xmm1, 11b": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 128-bit" + ] + }, + "vpshuflw ymm0, ymm1, 00b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 256-bit" + ] + }, + "vpshuflw ymm0, ymm1, 01b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 256-bit" + ] + }, + "vpshuflw ymm0, ymm1, 10b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 256-bit" + ] + }, + "vpshuflw ymm0, ymm1, 11b": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x70 256-bit" + ] + }, + "vpcmpeqb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x74 128-bit" + ] + }, + "vpcmpeqb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x74 256-bit" + ] + }, + "vpcmpeqw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x75 128-bit" + ] + }, + "vpcmpeqw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x75 256-bit" + ] + }, + "vpcmpeqd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x76 128-bit" + ] + }, + "vpcmpeqd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x76 256-bit" + ] + }, + "vzeroupper": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x77 L=0" + ] + }, + "vzeroall": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "Should use movi for all registers", + "Map 1 0b01 0x77 L=1" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x00": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x01": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x02": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x03": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x04": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x05": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x06": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmpps xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 128-bit" + ] + }, + "vcmpps ymm0, ymm1, ymm2, 0x07": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x00": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x01": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x02": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x03": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x04": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x05": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x06": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmppd xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 128-bit" + ] + }, + "vcmppd ymm0, ymm1, ymm2, 0x07": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC2 256-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpss xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x00": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x01": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x02": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x03": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x04": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x05": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x06": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vcmpsd xmm0, xmm1, xmm2, 0x07": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xC2 128-bit" + ] + }, + "vpinsrw xmm0, xmm1, eax, 000b": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC4 128-bit" + ] + }, + "vpinsrw xmm0, xmm1, eax, 001b": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC4 128-bit" + ] + }, + "vpinsrw xmm0, xmm1, eax, 111b": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC4 128-bit" + ] + }, + "vpextrw eax, xmm0, 000b": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC5 128-bit" + ] + }, + "vpextrw eax, xmm0, 001b": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC5 128-bit" + ] + }, + "vpextrw eax, xmm0, 111b": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC5 128-bit" + ] + }, + "vshufps xmm0, xmm1, xmm2, 00b": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 128-bit" + ] + }, + "vshufps ymm0, ymm1, ymm2, 00b": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 256-bit" + ] + }, + "vshufps xmm0, xmm1, xmm2, 01b": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 128-bit" + ] + }, + "vshufps ymm0, ymm1, ymm2, 01b": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 256-bit" + ] + }, + "vshufps xmm0, xmm1, xmm2, 10b": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 128-bit" + ] + }, + "vshufps ymm0, ymm1, ymm2, 10b": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 256-bit" + ] + }, + "vshufps xmm0, xmm1, xmm2, 11b": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 128-bit" + ] + }, + "vshufps ymm0, ymm1, ymm2, 11b": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0xC6 256-bit" + ] + }, + "vshufpd xmm0, xmm1, xmm2, 0b": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC6 128-bit" + ] + }, + "vshufpd ymm0, ymm1, ymm2, 0b": { + "ExpectedInstructionCount": 31, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC6 256-bit" + ] + }, + "vshufpd xmm0, xmm1, xmm2, 1b": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC6 128-bit" + ] + }, + "vshufpd ymm0, ymm1, ymm2, 1b": { + "ExpectedInstructionCount": 31, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xC6 256-bit" + ] + }, + "vmovaps xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x28 128-bit" + ] + }, + "vmovaps ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x28 256-bit" + ] + }, + "vmovapd xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x28 128-bit" + ] + }, + "vmovapd ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x28 256-bit" + ] + }, + "vmovaps [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x29 128-bit" + ] + }, + "vmovaps [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x29 256-bit" + ] + }, + "vmovapd [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x29 128-bit" + ] + }, + "vmovapd [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x29 256-bit" + ] + }, + "vcvtsi2ss xmm0, xmm1, eax": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2A 128-bit" + ] + }, + "vcvtsi2ss xmm0, xmm1, rax": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2A 128-bit" + ] + }, + "vcvtsi2sd xmm0, xmm1, eax": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2A 128-bit" + ] + }, + "vcvtsi2sd xmm0, xmm1, rax": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2A 128-bit" + ] + }, + "vmovntps [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2B 128-bit" + ] + }, + "vmovntps [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2B 256-bit" + ] + }, + "vmovntpd [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2B 128-bit" + ] + }, + "vmovntpd [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2B 256-bit" + ] + }, + "vcvttss2si eax, xmm0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2c 128-bit" + ] + }, + "vcvttss2si rax, xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2c 128-bit" + ] + }, + "vcvttsd2si eax, xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2c 128-bit" + ] + }, + "vcvttsd2si rax, xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2c 128-bit" + ] + }, + "vcvtss2si eax, xmm0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2d 128-bit" + ] + }, + "vcvtss2si rax, xmm0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x2d 128-bit" + ] + }, + "vcvtsd2si eax, xmm0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2d 128-bit" + ] + }, + "vcvtsd2si rax, xmm0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x2d 128-bit" + ] + }, + "vucomiss xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2e 128-bit" + ] + }, + "vucomisd xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2e 128-bit" + ] + }, + "vcomiss xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2f 128-bit" + ] + }, + "vcomisd xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2f 128-bit" + ] + }, + "vaddps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x58 128-bit" + ] + }, + "vaddps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x58 256-bit" + ] + }, + "vaddpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x58 128-bit" + ] + }, + "vaddpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x58 256-bit" + ] + }, + "vaddss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x58 128-bit" + ] + }, + "vaddsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x58 128-bit" + ] + }, + "vmulps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x59 128-bit" + ] + }, + "vmulps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x59 256-bit" + ] + }, + "vmulpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x59 128-bit" + ] + }, + "vmulpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x59 256-bit" + ] + }, + "vmulss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x59 128-bit" + ] + }, + "vmulsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x59 128-bit" + ] + }, + "vcvtps2pd xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5a 128-bit" + ] + }, + "vcvtpd2ps xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5a 128-bit" + ] + }, + "vcvtss2sd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5a 128-bit" + ] + }, + "vcvtsd2ss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5a 128-bit" + ] + }, + "vcvtdq2ps xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5b 128-bit" + ] + }, + "vcvtdq2ps ymm0, ymm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5b 256-bit" + ] + }, + "vcvtps2dq xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5b 128-bit" + ] + }, + "vcvtps2dq ymm0, ymm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5b 256-bit" + ] + }, + "vcvttps2dq xmm0, xmm1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5b 128-bit" + ] + }, + "vcvttps2dq ymm0, ymm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5b 256-bit" + ] + }, + "vsubps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5c 128-bit" + ] + }, + "vsubps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5c 256-bit" + ] + }, + "vsubpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5c 128-bit" + ] + }, + "vsubpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5c 256-bit" + ] + }, + "vsubss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5c 128-bit" + ] + }, + "vsubsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5c 128-bit" + ] + }, + "vminps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5d 128-bit" + ] + }, + "vminps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5d 256-bit" + ] + }, + "vminpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5d 128-bit" + ] + }, + "vminpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5d 256-bit" + ] + }, + "vminss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5d 128-bit" + ] + }, + "vminsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5d 128-bit" + ] + }, + "vdivps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5e 128-bit" + ] + }, + "vdivps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5e 256-bit" + ] + }, + "vdivpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5e 128-bit" + ] + }, + "vdivpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5e 256-bit" + ] + }, + "vdivss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5e 128-bit" + ] + }, + "vdivsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5e 128-bit" + ] + }, + "vmaxps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5f 128-bit" + ] + }, + "vmaxps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x5f 256-bit" + ] + }, + "vmaxpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5f 128-bit" + ] + }, + "vmaxpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x5f 256-bit" + ] + }, + "vmaxss xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x5f 128-bit" + ] + }, + "vmaxsd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x5f 128-bit" + ] + }, + "vpunpckhbw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x68 128-bit" + ] + }, + "vpunpckhbw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x68 256-bit" + ] + }, + "vpunpckhwd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x69 128-bit" + ] + }, + "vpunpckhwd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x69 256-bit" + ] + }, + "vpunpckhdq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6a 128-bit" + ] + }, + "vpunpckhdq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6a 256-bit" + ] + }, + "vpackssdw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6b 128-bit" + ] + }, + "vpackssdw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6b 256-bit" + ] + }, + "vpunpcklqdq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6c 128-bit" + ] + }, + "vpunpcklqdq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6c 256-bit" + ] + }, + "vpunpckhqdq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6d 128-bit" + ] + }, + "vpunpckhqdq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6d 256-bit" + ] + }, + "vmovd xmm0, dword [rax]": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6e 128-bit" + ] + }, + "vmovq xmm0, qword [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6e 128-bit" + ] + }, + "vmovdqa xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6f 128-bit" + ] + }, + "vmovdqa [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x6f 128-bit" + ] + }, + "vmovdqu xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x6f 128-bit" + ] + }, + "vmovdqu [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x6f 128-bit" + ] + }, + "vhaddpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7c 128-bit" + ] + }, + "vhaddpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7c 256-bit" + ] + }, + "vhaddps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x7c 128-bit" + ] + }, + "vhaddps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x7c 256-bit" + ] + }, + "vhsubpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7d 128-bit" + ] + }, + "vhsubpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7d 256-bit" + ] + }, + "vhsubps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x7d 128-bit" + ] + }, + "vhsubps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0x7d 256-bit" + ] + }, + "vmovd dword [rax], xmm0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7e 128-bit" + ] + }, + "vmovq qword [rax], xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7e 128-bit" + ] + }, + "vmovdqa ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7f 128-bit" + ] + }, + "vmovdqa [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x7f 128-bit" + ] + }, + "vmovdqu ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x7f 128-bit" + ] + }, + "vmovdqu [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0x7f 128-bit" + ] + }, + "vaddsubpd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd0 128-bit" + ] + }, + "vaddsubpd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd0 256-bit" + ] + }, + "vaddsubps xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xd0 128-bit" + ] + }, + "vaddsubps ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xd0 256-bit" + ] + }, + "vpsrlw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd1 128-bit" + ] + }, + "vpsrlw ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd1 256-bit" + ] + }, + "vpsrld xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd2 128-bit" + ] + }, + "vpsrld ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd2 256-bit" + ] + }, + "vpsrlq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd3 128-bit" + ] + }, + "vpsrlq ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd3 256-bit" + ] + }, + "vpaddq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd4 128-bit" + ] + }, + "vpaddq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd4 256-bit" + ] + }, + "vpmullw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd5 128-bit" + ] + }, + "vpmullw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd4 256-bit" + ] + }, + "vmovq [rax], xmm0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd6 256-bit" + ] + }, + "vpmovmskb rax, xmm0": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd7 256-bit" + ] + }, + "vpmovmskb rax, ymm0": { + "ExpectedInstructionCount": 20, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd7 256-bit" + ] + }, + "vpsubusb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd8 128-bit" + ] + }, + "vpsubusb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd8 256-bit" + ] + }, + "vpsubusw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd9 128-bit" + ] + }, + "vpsubusw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd9 256-bit" + ] + }, + "vpminub xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xda 128-bit" + ] + }, + "vpminub ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xda 256-bit" + ] + }, + "vpand xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdb 128-bit" + ] + }, + "vpand ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdb 256-bit" + ] + }, + "vpaddusb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdc 128-bit" + ] + }, + "vpaddusb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdc 256-bit" + ] + }, + "vpaddusw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdd 128-bit" + ] + }, + "vpaddusw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdd 256-bit" + ] + }, + "vpmaxub xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdd 128-bit" + ] + }, + "vpmaxub ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xde 256-bit" + ] + }, + "vpandn xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdf 128-bit" + ] + }, + "vpandn ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xdf 256-bit" + ] + }, + "vpavgb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe0 128-bit" + ] + }, + "vpavgb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe0 256-bit" + ] + }, + "vpsraw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe1 128-bit" + ] + }, + "vpsraw ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe1 256-bit" + ] + }, + "vpsrad xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe2 128-bit" + ] + }, + "vpsrad ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe2 256-bit" + ] + }, + "vpavgw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe3 128-bit" + ] + }, + "vpavgw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe3 256-bit" + ] + }, + "vpmulhuw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe4 128-bit" + ] + }, + "vpmulhuw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe4 256-bit" + ] + }, + "vpmulhw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe5 128-bit" + ] + }, + "vpmulhw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe5 256-bit" + ] + }, + "vcvttpd2dq xmm0, xmm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe6 128-bit" + ] + }, + "vcvttpd2dq xmm0, ymm1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe6 256-bit" + ] + }, + "vcvtdq2pd xmm0, xmm1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xe6 128-bit" + ] + }, + "vcvtdq2pd ymm0, xmm1": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b10 0xe6 256-bit" + ] + }, + "vcvtpd2dq xmm0, xmm1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xe6 128-bit" + ] + }, + "vcvtpd2dq xmm0, ymm1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xe6 256-bit" + ] + }, + "vmovntdq [rax], xmm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe7 128-bit" + ] + }, + "vmovntdq [rax], ymm0": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe7 256-bit" + ] + }, + "vpsubsb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe8 128-bit" + ] + }, + "vpsubsb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe8 256-bit" + ] + }, + "vpsubsw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe9 128-bit" + ] + }, + "vpsubsw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xe9 256-bit" + ] + }, + "vpminsw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xea 128-bit" + ] + }, + "vpminsw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xea 256-bit" + ] + }, + "vpor xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xeb 128-bit" + ] + }, + "vpor ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xeb 256-bit" + ] + }, + "vpaddsb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xec 128-bit" + ] + }, + "vpaddsb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xec 256-bit" + ] + }, + "vpaddsw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xed 128-bit" + ] + }, + "vpaddsw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xed 256-bit" + ] + }, + "vpmaxsw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xee 128-bit" + ] + }, + "vpmaxsw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xee 256-bit" + ] + }, + "vpxor xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xef 128-bit" + ] + }, + "vpxor ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xef 256-bit" + ] + }, + "vlddqu xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xf0 128-bit" + ] + }, + "vlddqu ymm0, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b11 0xf0 256-bit" + ] + }, + "vpsllw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf1 128-bit" + ] + }, + "vpsllw ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf1 256-bit" + ] + }, + "vpslld xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf2 128-bit" + ] + }, + "vpslld ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf2 256-bit" + ] + }, + "vpsllq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf3 128-bit" + ] + }, + "vpsllq ymm0, ymm1, xmm2": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf3 256-bit" + ] + }, + "vpmuludq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf4 128-bit" + ] + }, + "vpmuludq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf4 256-bit" + ] + }, + "vpmaddwd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf5 128-bit" + ] + }, + "vpmaddwd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf5 256-bit" + ] + }, + "vpsadbw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf6 128-bit" + ] + }, + "vpsadbw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 44, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf6 256-bit" + ] + }, + "vmaskmovdqu xmm0, xmm1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf7 128-bit" + ] + }, + "vpsubb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf8 128-bit" + ] + }, + "vpsubb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf8 256-bit" + ] + }, + "vpsubw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf9 128-bit" + ] + }, + "vpsubw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xf9 256-bit" + ] + }, + "vpsubd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfa 128-bit" + ] + }, + "vpsubd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfa 256-bit" + ] + }, + "vpsubq xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfb 128-bit" + ] + }, + "vpsubq ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfb 256-bit" + ] + }, + "vpaddb xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfc 128-bit" + ] + }, + "vpaddb ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfc 256-bit" + ] + }, + "vpaddw xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfd 128-bit" + ] + }, + "vpaddw ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfd 256-bit" + ] + }, + "vpaddd xmm0, xmm1, xmm2": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfe 128-bit" + ] + }, + "vpaddd ymm0, ymm1, ymm2": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xfe 256-bit" + ] + } + } +}