From 0a562fbb10fc95809afaf49c30a92fe4f09ee29c Mon Sep 17 00:00:00 2001
From: lioncash <mathew1800@gmail.com>
Date: Thu, 25 Aug 2022 10:17:11 -0400
Subject: [PATCH] InterpreterOps: Extend SSAData to handle 256-bit vectors

---
 .../Interface/Core/Interpreter/InterpreterDefines.h   | 11 ++++++++---
 .../Interface/Core/Interpreter/InterpreterOps.cpp     | 10 +++++++---
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h
index 8175d4c32..d07567a1f 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h
@@ -159,21 +159,26 @@
   break;                                            \
   }
 
+struct InterpVector256 {
+  __uint128_t Lower;
+  __uint128_t Upper;
+};
+
 template<typename Res>
 Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.ID().Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.ID().Value];
   return reinterpret_cast<Res>(DstPtr);
 }
 
 template<typename Res>
 Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Op.Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.Value];
   return reinterpret_cast<Res>(DstPtr);
 }
 
 
 template<typename Res>
 Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
-  auto DstPtr = &reinterpret_cast<__uint128_t*>(SSAData)[Src.ID().Value];
+  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Src.ID().Value];
   return reinterpret_cast<Res>(DstPtr);
 }
diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
index 85d7a4a04..2d36ddd72 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
@@ -1,5 +1,6 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
+#include "InterpreterDefines.h"
 #include "InterpreterOps.h"
 #include "F80Ops.h"
 
@@ -336,23 +337,26 @@ void InterpreterOps::Op_NoOp(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR:
 void InterpreterOps::InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::IR::IRListView const *CurrentIR) {
   volatile void *StackEntry = alloca(0);
 
-  uintptr_t ListSize = CurrentIR->GetSSACount();
+  const uintptr_t ListSize = CurrentIR->GetSSACount();
 
   static_assert(sizeof(FEXCore::IR::IROp_Header) == 4);
   static_assert(sizeof(FEXCore::IR::OrderedNode) == 16);
 
   auto BlockEnd = CurrentIR->GetBlocks().end();
 
+  constexpr size_t ListEntrySizeInBytes = sizeof(InterpVector256);
+  const size_t SSADataSize = ListSize * ListEntrySizeInBytes;
+
   InterpreterOps::IROpData OpData{};
   OpData.State = Frame->Thread;
-  OpData.SSAData = alloca(ListSize * 16);
+  OpData.SSAData = alloca(SSADataSize);
   OpData.CurrentEntry = Frame->State.rip;
   OpData.CurrentIR = CurrentIR;
   OpData.StackEntry = StackEntry;
   OpData.BlockIterator = CurrentIR->GetBlocks().begin();
 
   // Clear them all to zero. Required for Zero-extend semantics
-  memset(OpData.SSAData, 0, ListSize * 16);
+  memset(OpData.SSAData, 0, SSADataSize);
 
   while (1) {
     using namespace FEXCore::IR;