From 0ba501636ef92a67ab50698dc6333d1e4f5fcb3a Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 27 Oct 2024 23:33:49 -0700 Subject: [PATCH] IR: Change VSRSHR to use IR::OpSize --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 6 +++--- FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 8 ++++---- .../Interface/Core/OpcodeDispatcher/AVX_128.cpp | 2 +- .../Interface/Core/OpcodeDispatcher/H0F38Tables.h | 12 ++++++------ .../Interface/Core/OpcodeDispatcher/Vector.cpp | 8 ++++---- FEXCore/Source/Interface/IR/IR.json | 2 +- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 02d21a611..687d963b4 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5227,9 +5227,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x06), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VPHSUBOp, 4>}, {OPD(2, 0b01, 0x07), 1, &OpDispatchBuilder::VPHSUBSWOp}, - {OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::VPSIGN<1>}, - {OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::VPSIGN<2>}, - {OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::VPSIGN<4>}, + {OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::VPSIGN}, + {OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::VPSIGN}, + {OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::VPSIGN}, {OPD(2, 0b01, 0x0B), 1, &OpDispatchBuilder::VPMULHRSWOp}, {OPD(2, 0b01, 0x0C), 1, &OpDispatchBuilder::VPERMILRegOp}, {OPD(2, 0b01, 0x0D), 1, &OpDispatchBuilder::VPERMILRegOp}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index e38e92f29..145db4fa1 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -484,9 +484,9 @@ public: void InsertPSOp(OpcodeArgs); void PExtrOp(OpcodeArgs, IR::OpSize ElementSize); - template + template void PSIGN(OpcodeArgs); - template + template void VPSIGN(OpcodeArgs); // BMI1 Ops @@ -978,7 +978,7 @@ public: void AVX128_VPACKSS(OpcodeArgs); template void AVX128_VPACKUS(OpcodeArgs); - Ref AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2); + Ref AVX128_PSIGNImpl(IR::OpSize ElementSize, Ref Src1, Ref Src2); template void AVX128_VPSIGN(OpcodeArgs); template @@ -1413,7 +1413,7 @@ private: Ref GeneratePSHUFBMask(IR::OpSize SrcSize); Ref PSHUFBOpImpl(uint8_t SrcSize, Ref Src1, Ref Src2, Ref MaskVector); - Ref PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2); + Ref PSIGNImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src1, Ref Src2); Ref PSLLIImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src, uint64_t Shift); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 3b2cbf8fa..7c872529c 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -1091,7 +1091,7 @@ void OpDispatchBuilder::AVX128_VPACKUS(OpcodeArgs) { }); } -Ref OpDispatchBuilder::AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2) { +Ref OpDispatchBuilder::AVX128_PSIGNImpl(IR::OpSize ElementSize, Ref Src1, Ref Src2) { Ref Control = _VSQSHL(OpSize::i128Bit, ElementSize, Src2, (ElementSize * 8) - 1); Control = _VSRSHR(OpSize::i128Bit, ElementSize, Control, (ElementSize * 8) - 1); return _VMul(OpSize::i128Bit, ElementSize, Src1, Control); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h index 01aa24bc3..ac2b6f1de 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h @@ -25,12 +25,12 @@ constexpr std::tuple OpDis {OPD(PF_38_66, 0x06), 1, &OpDispatchBuilder::PHSUB<4>}, {OPD(PF_38_NONE, 0x07), 1, &OpDispatchBuilder::PHSUBS}, {OPD(PF_38_66, 0x07), 1, &OpDispatchBuilder::PHSUBS}, - {OPD(PF_38_NONE, 0x08), 1, &OpDispatchBuilder::PSIGN<1>}, - {OPD(PF_38_66, 0x08), 1, &OpDispatchBuilder::PSIGN<1>}, - {OPD(PF_38_NONE, 0x09), 1, &OpDispatchBuilder::PSIGN<2>}, - {OPD(PF_38_66, 0x09), 1, &OpDispatchBuilder::PSIGN<2>}, - {OPD(PF_38_NONE, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>}, - {OPD(PF_38_66, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>}, + {OPD(PF_38_NONE, 0x08), 1, &OpDispatchBuilder::PSIGN}, + {OPD(PF_38_66, 0x08), 1, &OpDispatchBuilder::PSIGN}, + {OPD(PF_38_NONE, 0x09), 1, &OpDispatchBuilder::PSIGN}, + {OPD(PF_38_66, 0x09), 1, &OpDispatchBuilder::PSIGN}, + {OPD(PF_38_NONE, 0x0A), 1, &OpDispatchBuilder::PSIGN}, + {OPD(PF_38_66, 0x0A), 1, &OpDispatchBuilder::PSIGN}, {OPD(PF_38_NONE, 0x0B), 1, &OpDispatchBuilder::PMULHRSW}, {OPD(PF_38_66, 0x0B), 1, &OpDispatchBuilder::PMULHRSW}, {OPD(PF_38_66, 0x10), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, OpSize::i8Bit>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index acc8a33e0..2d5b71d4a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -1646,15 +1646,15 @@ void OpDispatchBuilder::VEXTRACT128Op(OpcodeArgs) { StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, StoreSize, OpSize::iInvalid); } -Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2) { - const auto Size = GetSrcSize(Op); +Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src1, Ref Src2) { + const auto Size = OpSizeFromSrc(Op); Ref Control = _VSQSHL(Size, ElementSize, Src2, (ElementSize * 8) - 1); Control = _VSRSHR(Size, ElementSize, Control, (ElementSize * 8) - 1); return _VMul(Size, ElementSize, Src1, Control); } -template +template void OpDispatchBuilder::PSIGN(OpcodeArgs) { Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags); @@ -1667,7 +1667,7 @@ template void OpDispatchBuilder::PSIGN(OpcodeArgs); template void OpDispatchBuilder::PSIGN(OpcodeArgs); template void OpDispatchBuilder::PSIGN(OpcodeArgs); -template +template void OpDispatchBuilder::VPSIGN(OpcodeArgs) { Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags); diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 925b9f3bd..77cbdae4e 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -2094,7 +2094,7 @@ "DestSize": "RegisterSize", "NumElements": "RegisterSize / (ElementSize >> 1)" }, - "FPR = VSRSHR u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": { + "FPR = VSRSHR OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector, u8:$BitShift": { "Desc": ["Signed rounding shift right by immediate", "Exactly matching Arm64 srshr semantics" ],