From 6069fcb9d4d70b6b2e0a3ee5805f0fd1072b6665 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 12 Mar 2020 18:30:25 -0700
Subject: [PATCH 1/2] Implements Movshdup instruction

---
 .../FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 10 ++++++++++
 .../FEXCore/Source/Interface/Core/OpcodeDispatcher.h   |  1 +
 2 files changed, 11 insertions(+)

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index a6c6cc806..3fba19301 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -2382,6 +2382,15 @@ void OpDispatchBuilder::MOVLPOp(OpcodeArgs) {
   }
 }
 
+void OpDispatchBuilder::MOVSHDUPOp(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 8);
+  OrderedNode *Result = _VInsElement(16, 4, 3, 3, Src, Src);
+  Result = _VInsElement(16, 4, 2, 3, Result, Src);
+  Result = _VInsElement(16, 4, 1, 1, Result, Src);
+  Result = _VInsElement(16, 4, 0, 1, Result, Src);
+  StoreResult(FPRClass, Op, Result, -1);
+}
+
 void OpDispatchBuilder::MOVSSOp(OpcodeArgs) {
   if (Op->Dest.TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_GPR &&
       Op->Src[0].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_GPR) {
@@ -4723,6 +4732,7 @@ void InstallOpcodeHandlers() {
 
   const std::vector<std::tuple<uint8_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr>> RepModOpTable = {
     {0x10, 2, &OpDispatchBuilder::MOVSSOp},
+    {0x16, 1, &OpDispatchBuilder::MOVSHDUPOp},
     {0x19, 7, &OpDispatchBuilder::NOPOp},
     {0x2A, 1, &OpDispatchBuilder::CVT<4, true>},
     {0x2C, 1, &OpDispatchBuilder::FCVT<4, true>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
index 3e73fd6b6..9d6c8d8eb 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -185,6 +185,7 @@ public:
   void MOVUPSOp(OpcodeArgs);
   void MOVLHPSOp(OpcodeArgs);
   void MOVLPOp(OpcodeArgs);
+  void MOVSHDUPOp(OpcodeArgs);
   void MOVHPDOp(OpcodeArgs);
   void MOVSDOp(OpcodeArgs);
   template<FEXCore::IR::IROps IROp, size_t ElementSize>

From 5bf9dd13b3c65e3f3ebc2c579fb5f90b6e84dbf1 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 12 Mar 2020 18:30:35 -0700
Subject: [PATCH 2/2] Adds movshdup unit test

---
 unittests/ASM/REP/F3_16.asm | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 unittests/ASM/REP/F3_16.asm

diff --git a/unittests/ASM/REP/F3_16.asm b/unittests/ASM/REP/F3_16.asm
new file mode 100644
index 000000000..0d76a4da9
--- /dev/null
+++ b/unittests/ASM/REP/F3_16.asm
@@ -0,0 +1,32 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "XMM0":  ["0x4142434441424344", "0x5152535451525354"],
+    "XMM1":  ["0x4142434441424344", "0x5152535451525354"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+mov rdx, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [rdx + 8 * 0], rax
+mov rax, 0x5152535455565758
+mov [rdx + 8 * 1], rax
+
+mov rax, 0x6162633265666768
+mov [rdx + 8 * 2], rax
+mov rax, 0x7172737475767778
+mov [rdx + 8 * 3], rax
+
+movapd xmm2, [rdx + 8 * 0]
+movapd xmm0, [rdx + 8 * 2]
+movapd xmm1, [rdx + 8 * 2]
+
+movshdup xmm0, xmm2
+movshdup xmm1, [rdx + 8 * 0]
+
+hlt