From 17dc0bfcd894d2ec45cc3cc14e6f31a1b2e9561b Mon Sep 17 00:00:00 2001
From: Stefanos Kornilios Mitsis Poiitidis <stef@skmp.dev>
Date: Sun, 6 Dec 2020 12:59:48 +0200
Subject: [PATCH] SRA: Only do read-alias if accessing low part of register

---
 .../FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp    | 8 ++++++++
 .../FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp | 4 ++++
 .../Source/Interface/IR/Passes/RegisterAllocationPass.cpp | 8 ++++----
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
index bb7da0ae9..078b29415 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -524,7 +524,9 @@ DEF_OP(LDiv) {
       CallRuntime(LDIV);
 #else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LDIV));
+      SpillStaticRegs(true);
       blr(x3);
+      FillStaticRegs(true);
 #endif
 
       // Result is now in x0
@@ -585,7 +587,9 @@ DEF_OP(LUDiv) {
       CallRuntime(LUDIV);
 #else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUDIV));
+      SpillStaticRegs(true);
       blr(x3);
+      FillStaticRegs(true);
 #endif
 
       // Result is now in x0
@@ -656,7 +660,9 @@ DEF_OP(LRem) {
       CallRuntime(LREM);
 #else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LREM));
+      SpillStaticRegs(true);
       blr(x3);
+      FillStaticRegs(true);
 #endif
 
       // Result is now in x0
@@ -723,7 +729,9 @@ DEF_OP(LURem) {
       CallRuntime(LUREM);
 #else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUREM));
+      SpillStaticRegs(true);
       blr(x3);
+      FillStaticRegs(true);
 #endif
 
       // Result is now in x0
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp
index 84d9530f2..1bc6d0180 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp
@@ -308,7 +308,9 @@ DEF_OP(RemoveCodeEntry) {
   LoadConstant(x1, Op->RIP);
  
   LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  SpillStaticRegs(true);
   blr(x2);
+  FillStaticRegs(true);
 
   // Fix the stack and any values that were stepped on
   i = 0;
@@ -349,7 +351,9 @@ DEF_OP(CPUID) {
   PtrCast Ptr;
   Ptr.ClassPtr = &FEXCore::CPUIDEmu::RunFunction;
   LoadConstant(x3, Ptr.Data);
+  SpillStaticRegs(true);
   blr(x3);
+  FillStaticRegs(true);
 
   i = 0;
   for (auto RA : RA64) {
diff --git a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
index e2e8308e6..5dcaefdd2 100644
--- a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+++ b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -510,11 +510,11 @@ namespace FEXCore::IR {
       }
     };
 
-    auto IsAliasable = [](uint8_t Size, RegisterClassType StaticClass) {
+    auto IsAliasable = [](uint8_t Size, RegisterClassType StaticClass, uint32_t Offset) {
       if (StaticClass == GPRFixedClass) {
-        return Size == 8 || Size == 4; // lower values depend on z-ext semantics
+        return (Size == 8 || Size == 4) && ((Offset & 7) == 0); // lower values depend on z-ext semantics
       } else if (StaticClass == FPRFixedClass) {
-        return Size == 16 || Size == 8 || Size == 4; // maybe 2 and 1 are safe too
+        return (Size == 16 || Size == 8 || Size == 4) && ((Offset & 15) == 0); // maybe 2 and 1 are safe too
       } else {
         assert(false);
       }
@@ -654,7 +654,7 @@ namespace FEXCore::IR {
             // if not sra-allocated and full size, sra-allocate
             if (!LiveRanges[Node].Global && LiveRanges[Node].PrefferedRegister  == -1) {
               // only full size reads can be aliased
-              if (IsAliasable(IROp->Size, Op->StaticClass)) {
+              if (IsAliasable(IROp->Size, Op->StaticClass, Op->Offset)) {
 
                 // We can only track a single active span.
                 // Marking here as written is overly agressive, but