From 6fcbce0c528d955f0003bf5e3b32da857658bff8 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 2 Feb 2023 20:11:00 -0500 Subject: [PATCH 1/5] ARMEmitter: Handle SVE FADDV --- .../Core/ArchHelpers/CodeEmitter/SVEOps.inl | 19 ++++++++++++++++++- .../FEXCore/unittests/Emitter/SVE_Tests.cpp | 2 +- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 12ba2a204..ff133e367 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -573,7 +573,10 @@ public: } // SVE floating-point recursive reduction - // XXX: + void faddv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; + SVEFPRecursiveReduction(Op, 0b000, size, vd, pg, zn); + } // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) @@ -3929,6 +3932,20 @@ private: dc32(Instr); } + void SVEFPRecursiveReduction(uint32_t op, uint32_t opc, SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + LOGMAN_THROW_AA_FMT(size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, + "FP reduction operation can only use 16-bit, 32-bit, or 64-bit element sizes"); + LOGMAN_THROW_AA_FMT(pg <= PReg::p7, "FP reduction operation can only use p0-p7 as a governing predicate"); + + uint32_t Instr = op; + Instr |= FEXCore::ToUnderlying(size) << 22; + Instr |= opc << 16; + Instr |= pg.Idx() << 10; + Instr |= zn.Idx() << 5; + Instr |= vd.Idx(); + dc32(Instr); + } + // SVE floating-point round to integral value void frintX(uint32_t opc, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { // opc = round mode diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 3115e212f..91aac179d 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -433,7 +433,7 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point arithmetic //TEST_SINGLE(frsqrts(SubRegSize::i128Bit, ZReg::z30, ZReg::z29, ZReg::z28), "frsqrts z30.q, z29.q, z28.q"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive reduction") { - // TODO: Implement in emitter. + TEST_SINGLE(faddv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "faddv v30.h, p7, z28.h"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") { From 25f97065dfc702fc10bf07264d86ac1ac703a2d8 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 2 Feb 2023 20:31:52 -0500 Subject: [PATCH 2/5] ARMEmitter: Handle SVE FMAXNMV --- .../Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index ff133e367..593438404 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -577,6 +577,10 @@ public: constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; SVEFPRecursiveReduction(Op, 0b000, size, vd, pg, zn); } + void fmaxnmv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; + SVEFPRecursiveReduction(Op, 0b100, size, vd, pg, zn); + } // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 91aac179d..dc3fb16db 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -433,7 +433,13 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point arithmetic //TEST_SINGLE(frsqrts(SubRegSize::i128Bit, ZReg::z30, ZReg::z29, ZReg::z28), "frsqrts z30.q, z29.q, z28.q"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive reduction") { - TEST_SINGLE(faddv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "faddv v30.h, p7, z28.h"); + TEST_SINGLE(faddv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "faddv h30, p7, z28.h"); + TEST_SINGLE(faddv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "faddv s30, p7, z28.s"); + TEST_SINGLE(faddv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "faddv d30, p7, z28.d"); + + TEST_SINGLE(fmaxnmv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv h30, p7, z28.h"); + TEST_SINGLE(fmaxnmv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv s30, p7, z28.s"); + TEST_SINGLE(fmaxnmv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv d30, p7, z28.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") { From ac9f9d291b4ae4e26cd1458a0db09954acac68d3 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 2 Feb 2023 20:34:16 -0500 Subject: [PATCH 3/5] ARMEmitter: Handle SVE FMINNMV --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 593438404..4c9877947 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -581,6 +581,10 @@ public: constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; SVEFPRecursiveReduction(Op, 0b100, size, vd, pg, zn); } + void fminnmv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; + SVEFPRecursiveReduction(Op, 0b101, size, vd, pg, zn); + } // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index dc3fb16db..be68a0c47 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -440,6 +440,10 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive r TEST_SINGLE(fmaxnmv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv h30, p7, z28.h"); TEST_SINGLE(fmaxnmv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv s30, p7, z28.s"); TEST_SINGLE(fmaxnmv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxnmv d30, p7, z28.d"); + + TEST_SINGLE(fminnmv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv h30, p7, z28.h"); + TEST_SINGLE(fminnmv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv s30, p7, z28.s"); + TEST_SINGLE(fminnmv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv d30, p7, z28.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") { From f77de7f2830f212b618511ae96bad8eed0643c5b Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 2 Feb 2023 20:36:33 -0500 Subject: [PATCH 4/5] ARMEmitter: Handle SVE FMAXV --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 4c9877947..ee455d63b 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -585,6 +585,10 @@ public: constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; SVEFPRecursiveReduction(Op, 0b101, size, vd, pg, zn); } + void fmaxv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; + SVEFPRecursiveReduction(Op, 0b110, size, vd, pg, zn); + } // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index be68a0c47..6935e77dd 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -444,6 +444,10 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive r TEST_SINGLE(fminnmv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv h30, p7, z28.h"); TEST_SINGLE(fminnmv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv s30, p7, z28.s"); TEST_SINGLE(fminnmv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fminnmv d30, p7, z28.d"); + + TEST_SINGLE(fmaxv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv h30, p7, z28.h"); + TEST_SINGLE(fmaxv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv s30, p7, z28.s"); + TEST_SINGLE(fmaxv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv d30, p7, z28.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") { From 4001dc12199db4465ceac0dbd1561929df81aba4 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 2 Feb 2023 20:41:41 -0500 Subject: [PATCH 5/5] ARMEmitter: Handle SVE FMINV --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index ee455d63b..a3fbec28f 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -589,6 +589,10 @@ public: constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; SVEFPRecursiveReduction(Op, 0b110, size, vd, pg, zn); } + void fminv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) { + constexpr uint32_t Op = 0b0110'0101'0000'0000'0010'0000'0000'0000; + SVEFPRecursiveReduction(Op, 0b111, size, vd, pg, zn); + } // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 6935e77dd..57f0ebaf6 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -448,6 +448,10 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive r TEST_SINGLE(fmaxv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv h30, p7, z28.h"); TEST_SINGLE(fmaxv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv s30, p7, z28.s"); TEST_SINGLE(fmaxv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fmaxv d30, p7, z28.d"); + + TEST_SINGLE(fminv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z28), "fminv h30, p7, z28.h"); + TEST_SINGLE(fminv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z28), "fminv s30, p7, z28.s"); + TEST_SINGLE(fminv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z28), "fminv d30, p7, z28.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") {