From 1ea53c65ab67f99015efbea1e2d29a680fb364d5 Mon Sep 17 00:00:00 2001
From: Lioncache <mai.iam2048@gmail.com>
Date: Mon, 20 Feb 2023 16:25:07 -0500
Subject: [PATCH] x86_64/VectorOps: Handle 8-bit VShlI IR op

Useful for handling VPERMD.
---
 .../Interface/Core/JIT/x86_64/VectorOps.cpp     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
index 1dbd6da43..20fd394da 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
@@ -3332,6 +3332,23 @@ DEF_OP(VShlI) {
   const auto Vector = GetSrc(Op->Vector.ID());
 
   switch (ElementSize) {
+    case 1: {
+      const auto Mask = 0xFFU >> BitShift;
+
+      mov(rax, Mask);
+      vmovq(xmm15, rax);
+
+      if (Is256Bit) {
+        vpsllw(ToYMM(Dst), ToYMM(Vector), BitShift);
+        vpbroadcastb(ymm15, xmm15);
+        vpand(ToYMM(Dst), ToYMM(Dst), ymm15);
+      } else {
+        vpsllw(Dst, Vector, BitShift);
+        vpbroadcastb(xmm15, xmm15);
+        vpand(Dst, Dst, ymm15);
+      }
+      break;
+    }
     case 2: {
       if (Is256Bit) {
         vpsllw(ToYMM(Dst), ToYMM(Vector), BitShift);