From 28fa88ff39e08f27c0991ce42cf8d68c26ba2f6a Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 29 Apr 2024 08:46:36 -0400 Subject: [PATCH] OpcodeDispatcher: fix 8/16-bit adc/sbc flags Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index faea27af3..33e0a4e04 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -344,6 +344,9 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode* Res = _Adc(OpSize, Src1, Src2); Res = _Bfe(OpSize, SrcSize * 8, 0, Res); + // Need to zero-extend for correct comparisons below + Src2 = _Bfe(OpSize, SrcSize * 8, 0, Src2); + auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero); auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero); auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT); @@ -379,6 +382,9 @@ OrderedNode* OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode* Res = _Sub(OpSize, Src1, _Add(OpSize, Src2, CF)); Res = _Bfe(OpSize, SrcSize * 8, 0, Res); + // Need to zero-extend for correct comparisons below + Src1 = _Bfe(OpSize, SrcSize * 8, 0, Src1); + auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero); auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero); auto SelectCF = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT);