From 2e32e1367df1c64eb11757fcedfcfc8f8bf3810e Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 27 Sep 2023 10:36:44 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/H0F38.json | 4 +- .../InstructionCountCI/Primary_32Bit.json | 76 +++++++------------ unittests/InstructionCountCI/VEX_map2.json | 8 +- 3 files changed, 29 insertions(+), 59 deletions(-) diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 0b2c19c3a..ab50cb0d4 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -416,7 +416,7 @@ ] }, "ptest xmm0, xmm1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0x17" @@ -438,8 +438,6 @@ "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "mov w21, #0x90000000", - "bic x20, x20, x21", "strb w23, [x28, #706]", "strb w22, [x28, #708]", "str w20, [x28, #728]" diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 038c7703d..f6d3b79f5 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -215,7 +215,7 @@ ] }, "aaa": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x37", "ExpectedArm64ASM": [ @@ -229,28 +229,26 @@ "cmp x21, #0x9 (9)", "cset x21, hi", "orr x20, x20, x21", - "cbnz x20, #+0x24", + "cbnz x20, #+0x20", "mov w20, #0xff0f", "and x20, x22, x20", "bfxil w4, w20, #0, #16", "mov w20, #0x0", - "mov w21, #0x0", "strb w20, [x28, #708]", - "str w21, [x28, #728]", - "b #+0x28", + "str w20, [x28, #728]", + "b #+0x24", "add x20, x22, #0x106 (262)", "mov w21, #0xff0f", "and x20, x20, x21", "bfxil w4, w20, #0, #16", - "ldr w20, [x28, #728]", - "orr w20, w20, #0x20000000", + "mov w20, #0x20000000", "mov w21, #0x10", "strb w21, [x28, #708]", "str w20, [x28, #728]" ] }, "aas": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x3f", "ExpectedArm64ASM": [ @@ -264,22 +262,20 @@ "cmp x21, #0x9 (9)", "cset x21, hi", "orr x20, x20, x21", - "cbnz x20, #+0x24", + "cbnz x20, #+0x20", "mov w20, #0xff0f", "and x20, x22, x20", "bfxil w4, w20, #0, #16", "mov w20, #0x0", - "mov w21, #0x0", "strb w20, [x28, #708]", - "str w21, [x28, #728]", - "b #+0x2c", + "str w20, [x28, #728]", + "b #+0x28", "sub x20, x22, #0x6 (6)", "sub x20, x20, #0x100 (256)", "mov w21, #0xff0f", "and x20, x20, x21", "bfxil w4, w20, #0, #16", - "ldr w20, [x28, #728]", - "orr w20, w20, #0x20000000", + "mov w20, #0x20000000", "mov w21, #0x10", "strb w21, [x28, #708]", "str w20, [x28, #728]" @@ -440,7 +436,7 @@ ] }, "aam": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0xd4", "ExpectedArm64ASM": [ @@ -453,20 +449,15 @@ "add x20, x21, x20", "bfxil w4, w20, #0, #16", "uxtb w20, w4", - "and x21, x20, #0x80", - "cmp x21, #0x0 (0)", - "cset x21, hs", - "lsl x21, x21, #31", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "orr w21, w21, w22, lsl #30", + "lsl w21, w20, #24", + "tst w21, w21", + "mrs x21, nzcv", "strb w20, [x28, #706]", "str w21, [x28, #728]" ] }, "aad": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "0xd5", "ExpectedArm64ASM": [ @@ -479,20 +470,15 @@ "and x20, x20, #0xff", "bfxil w4, w20, #0, #16", "uxtb w20, w4", - "and x21, x20, #0x80", - "cmp x21, #0x0 (0)", - "cset x21, hs", - "lsl x21, x21, #31", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "orr w21, w21, w22, lsl #30", + "lsl w21, w20, #24", + "tst w21, w21", + "mrs x21, nzcv", "strb w20, [x28, #706]", "str w21, [x28, #728]" ] }, "db 0xd4, 0x40": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "aam with a different immediate byte base", @@ -508,20 +494,15 @@ "add x20, x21, x20", "bfxil w4, w20, #0, #16", "uxtb w20, w4", - "and x21, x20, #0x80", - "cmp x21, #0x0 (0)", - "cset x21, hs", - "lsl x21, x21, #31", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "orr w21, w21, w22, lsl #30", + "lsl w21, w20, #24", + "tst w21, w21", + "mrs x21, nzcv", "strb w20, [x28, #706]", "str w21, [x28, #728]" ] }, "db 0xd5, 0x40": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": [ "aad with a different immediate byte base", @@ -536,14 +517,9 @@ "and x20, x20, #0xff", "bfxil w4, w20, #0, #16", "uxtb w20, w4", - "and x21, x20, #0x80", - "cmp x21, #0x0 (0)", - "cset x21, hs", - "lsl x21, x21, #31", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "orr w21, w21, w22, lsl #30", + "lsl w21, w20, #24", + "tst w21, w21", + "mrs x21, nzcv", "strb w20, [x28, #706]", "str w21, [x28, #728]" ] diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index d2e11b4e1..26a4217ef 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -791,7 +791,7 @@ ] }, "vptest xmm0, xmm1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Optimal": "No", "Comment": [ "Map 2 0b01 0x16 128-bit" @@ -815,15 +815,13 @@ "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "mov w21, #0x90000000", - "bic x20, x20, x21", "strb w23, [x28, #706]", "strb w22, [x28, #708]", "str w20, [x28, #728]" ] }, "vptest ymm0, ymm1": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 29, "Optimal": "No", "Comment": [ "Map 2 0b01 0x16 256-bit" @@ -855,8 +853,6 @@ "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "mov w21, #0x90000000", - "bic x20, x20, x21", "strb w23, [x28, #706]", "strb w22, [x28, #708]", "str w20, [x28, #728]"