From 2fbcf2e4a9bd24659a55f8a02e0b5743bcddac58 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Fri, 25 Aug 2023 03:44:10 -0700 Subject: [PATCH] OpcodeDispatcher: Optimize movddup from register This is now optimal --- FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index c636f294c..04f9e3f54 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -1812,7 +1812,11 @@ void OpDispatchBuilder::VPSRLVOp(OpcodeArgs) { } void OpDispatchBuilder::MOVDDUPOp(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + // If loading a vector, use the full size, so we don't + // unnecessarily zero extend the vector. Otherwise, if + // memory, then we want to load the element size exactly. + const auto SrcSize = Op->Src[0].IsGPR() ? 16U : GetSrcSize(Op); + OrderedNode *Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags, -1); OrderedNode *Res = _VDupElement(16, GetSrcSize(Op), Src, 0); StoreResult(FPRClass, Op, Res, -1);