diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 627c4851b..145002d9a 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5926,6 +5926,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
 
     {OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op},
     {OPD(1, 0b01, 0xF8), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 1>},
+    {OPD(1, 0b01, 0xF9), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 2>},
     {OPD(1, 0b01, 0xFC), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VADD, 1>},
     {OPD(1, 0b01, 0xFD), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VADD, 2>},
     {OPD(1, 0b01, 0xFE), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VADD, 4>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index f11b99774..d452d4483 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -422,6 +422,8 @@ template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VADD, 8>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 1>(OpcodeArgs);
+template
+void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VSUB, 2>(OpcodeArgs);
 
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VCMPEQ, 1>(OpcodeArgs);
diff --git a/unittests/ASM/VEX/vpsubw.asm b/unittests/ASM/VEX/vpsubw.asm
new file mode 100644
index 000000000..b055a5403
--- /dev/null
+++ b/unittests/ASM/VEX/vpsubw.asm
@@ -0,0 +1,43 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x6162636465666768", "0x7172737475767778", "0xFFFF636465666768", "0x7172737475767778"],
+    "XMM1": ["0x4142434445464748", "0x5152535455565758", "0xFFFF434445464748", "0x5152535455565758"],
+    "XMM2": ["0x2020202020202020", "0x2020202020202020", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x2020202020202020", "0x2020202020202020", "0x0000202020202020", "0x2020202020202020"],
+    "XMM4": ["0x2020202020202020", "0x2020202020202020", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5": ["0x2020202020202020", "0x2020202020202020", "0x0000202020202020", "0x2020202020202020"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rdx + 32]
+
+; Memory operand
+vpsubw xmm2, xmm0, [rdx + 32]
+vpsubw ymm3, ymm0, [rdx + 32]
+
+; Register only
+vpsubw xmm4, xmm0, xmm1
+vpsubw ymm5, ymm0, ymm1
+
+hlt
+
+align 32
+.data:
+dq 0x6162636465666768
+dq 0x7172737475767778
+dq 0xFFFF636465666768
+dq 0x7172737475767778
+
+dq 0x4142434445464748
+dq 0x5152535455565758
+dq 0xFFFF434445464748
+dq 0x5152535455565758