From d491ce7125727c215016f9170f2dbae761801b68 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Fri, 3 Feb 2023 22:53:21 -0500 Subject: [PATCH 1/4] ARMEmitter: Handle SVE MLA (vectors) --- .../Core/ArchHelpers/CodeEmitter/SVEOps.inl | 20 ++++++++++++++++++- .../FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 ++++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 128bba1eb..9516e805c 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -596,7 +596,11 @@ public: // SVE integer Multiply-Add - Predicated // SVE integer multiply-accumulate writing addend (predicated) - // XXX: + void mla(SubRegSize size, ZRegister zda, PRegisterMerge pg, ZRegister zn, ZRegister zm) { + constexpr uint32_t Op = 0b0000'0100'0000'0000'0100'0000'0000'0000; + SVEIntegerMultiplyAddSubPredicated(Op, 0b0, size, zda, pg, zn, zm); + } + // SVE integer multiply-add writing multiplicand (predicated) // XXX: @@ -4055,6 +4059,20 @@ private: dc32(Instr); } + void SVEIntegerMultiplyAddSubPredicated(uint32_t op, uint32_t opc, SubRegSize size, ZRegister zd, PRegister pg, ZRegister zn, ZRegister zm) { + LOGMAN_THROW_AA_FMT(size != SubRegSize::i128Bit, "Can't use 128-bit element size"); + LOGMAN_THROW_AA_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate"); + + uint32_t Instr = op; + Instr |= FEXCore::ToUnderlying(size) << 22; + Instr |= opc << 13; + Instr |= zm.Idx() << 16; + Instr |= pg.Idx() << 10; + Instr |= zn.Idx() << 5; + Instr |= zd.Idx(); + dc32(Instr); + } + // SVE floating-point round to integral value void frintX(uint32_t opc, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { // opc = round mode diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 49ca57f56..c98576458 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -455,7 +455,10 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point recursive r } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulate writing addend (predicated)") { - // TODO: Implement in emitter. + TEST_SINGLE(mla(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.b, p7/m, z28.b, z29.b"); + TEST_SINGLE(mla(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.h, p7/m, z28.h, z29.h"); + TEST_SINGLE(mla(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.s, p7/m, z28.s, z29.s"); + TEST_SINGLE(mla(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.d, p7/m, z28.d, z29.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-add writing multiplicand (predicated)") { From 65ad9169847f1a1c47b626f0180960c1499db6fb Mon Sep 17 00:00:00 2001 From: Lioncache Date: Fri, 3 Feb 2023 23:04:55 -0500 Subject: [PATCH 2/4] ARMEmitter: Handle SVE MLS (vectors) --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 9516e805c..69146a447 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -600,6 +600,10 @@ public: constexpr uint32_t Op = 0b0000'0100'0000'0000'0100'0000'0000'0000; SVEIntegerMultiplyAddSubPredicated(Op, 0b0, size, zda, pg, zn, zm); } + void mls(SubRegSize size, ZRegister zda, PRegisterMerge pg, ZRegister zn, ZRegister zm) { + constexpr uint32_t Op = 0b0000'0100'0000'0000'0100'0000'0000'0000; + SVEIntegerMultiplyAddSubPredicated(Op, 0b1, size, zda, pg, zn, zm); + } // SVE integer multiply-add writing multiplicand (predicated) // XXX: diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index c98576458..c8ece9026 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -459,6 +459,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulat TEST_SINGLE(mla(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.h, p7/m, z28.h, z29.h"); TEST_SINGLE(mla(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.s, p7/m, z28.s, z29.s"); TEST_SINGLE(mla(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mla z30.d, p7/m, z28.d, z29.d"); + + TEST_SINGLE(mls(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mls z30.b, p7/m, z28.b, z29.b"); + TEST_SINGLE(mls(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mls z30.h, p7/m, z28.h, z29.h"); + TEST_SINGLE(mls(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mls z30.s, p7/m, z28.s, z29.s"); + TEST_SINGLE(mls(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mls z30.d, p7/m, z28.d, z29.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-add writing multiplicand (predicated)") { From 3783ad8dd12160b7b9cfee7083d10577dc8a876a Mon Sep 17 00:00:00 2001 From: Lioncache Date: Fri, 3 Feb 2023 23:08:00 -0500 Subject: [PATCH 3/4] ARMEmitter: Handle SVE MAD --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 5 ++++- External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 69146a447..ec736c01e 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -606,7 +606,10 @@ public: } // SVE integer multiply-add writing multiplicand (predicated) - // XXX: + void mad(SubRegSize size, ZRegister zdn, PRegisterMerge pg, ZRegister zm, ZRegister za) { + constexpr uint32_t Op = 0b0000'0100'0000'0000'1100'0000'0000'0000; + SVEIntegerMultiplyAddSubPredicated(Op, 0b0, size, zdn, pg, za, zm); + } // SVE Integer Binary Arithmetic - Predicated // SVE integer add/subtract vectors (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index c8ece9026..51a304522 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -467,7 +467,10 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-accumulat } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-add writing multiplicand (predicated)") { - // TODO: Implement in emitter. + TEST_SINGLE(mad(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.b, p7/m, z28.b, z29.b"); + TEST_SINGLE(mad(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.h, p7/m, z28.h, z29.h"); + TEST_SINGLE(mad(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.s, p7/m, z28.s, z29.s"); + TEST_SINGLE(mad(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.d, p7/m, z28.d, z29.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer add/subtract vectors (predicated)") { From 7442ef3a83c62c95f69b61763da2fafc5e629425 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Fri, 3 Feb 2023 23:13:41 -0500 Subject: [PATCH 4/4] ARMEmitter: Handle SVE MSB --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 4 ++++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index ec736c01e..b7c30016b 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -610,6 +610,10 @@ public: constexpr uint32_t Op = 0b0000'0100'0000'0000'1100'0000'0000'0000; SVEIntegerMultiplyAddSubPredicated(Op, 0b0, size, zdn, pg, za, zm); } + void msb(SubRegSize size, ZRegister zdn, PRegisterMerge pg, ZRegister zm, ZRegister za) { + constexpr uint32_t Op = 0b0000'0100'0000'0000'1100'0000'0000'0000; + SVEIntegerMultiplyAddSubPredicated(Op, 0b1, size, zdn, pg, za, zm); + } // SVE Integer Binary Arithmetic - Predicated // SVE integer add/subtract vectors (predicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 51a304522..fc3662736 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -471,6 +471,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply-add writi TEST_SINGLE(mad(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.h, p7/m, z28.h, z29.h"); TEST_SINGLE(mad(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.s, p7/m, z28.s, z29.s"); TEST_SINGLE(mad(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "mad z30.d, p7/m, z28.d, z29.d"); + + TEST_SINGLE(msb(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "msb z30.b, p7/m, z28.b, z29.b"); + TEST_SINGLE(msb(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "msb z30.h, p7/m, z28.h, z29.h"); + TEST_SINGLE(msb(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "msb z30.s, p7/m, z28.s, z29.s"); + TEST_SINGLE(msb(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z28, ZReg::z29), "msb z30.d, p7/m, z28.d, z29.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer add/subtract vectors (predicated)") {