From 383b8b7bb5a2ed2729bd2a8ef6a0bada7233efcf Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sun, 12 Jul 2020 03:41:02 +0100 Subject: [PATCH] Fixes VADDV assert and implementation detail AArch64's ADDV instruction doesn't support 8byte elements, it instead needs to use ADDP(scalar) for the operation. Fixes an assert and minor behaviour difference there --- .../FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp index e03407af0..a1d3ec800 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp @@ -269,8 +269,10 @@ DEF_OP(VAddV) { case 1: case 2: case 4: + addv(GetDst(Node).VCast(Op->Header.ElementSize * 8, 1), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements)); + break; case 8: - addv(GetDst(Node).VCast(OpSize * 8, Elements), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements)); + addp(GetDst(Node).VCast(OpSize * 8, 1), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements)); break; default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break; }