From 392438d70a2e487f55530f6ff06df04920bbccbb Mon Sep 17 00:00:00 2001 From: Lioncache Date: Tue, 21 Mar 2023 16:06:32 -0400 Subject: [PATCH] ARMEmitter: Handle SVE inc/dec register by predicate count group --- .../Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 7 ++++++- External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 10 +++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index ef253349e..9c492fcd4 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -1732,7 +1732,12 @@ public: } // SVE inc/dec register by predicate count - // XXX: + void incp(SubRegSize size, XRegister rdn, PRegister pm) { + SVEIncDecPredicateCountScalar(1, 1, 0b00, 0b00, size, rdn, pm); + } + void decp(SubRegSize size, XRegister rdn, PRegister pm) { + SVEIncDecPredicateCountScalar(1, 1, 0b00, 0b01, size, rdn, pm); + } // SVE Write FFR // SVE FFR write from predicate diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 851f9624e..9b7e23d69 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -2093,7 +2093,15 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE inc/dec vector by predicat } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE inc/dec register by predicate count") { - // TODO: Implement in emitter. + TEST_SINGLE(incp(SubRegSize::i8Bit, XReg::x30, PReg::p15), "incp x30, p15.b"); + TEST_SINGLE(incp(SubRegSize::i16Bit, XReg::x30, PReg::p15), "incp x30, p15.h"); + TEST_SINGLE(incp(SubRegSize::i32Bit, XReg::x30, PReg::p15), "incp x30, p15.s"); + TEST_SINGLE(incp(SubRegSize::i64Bit, XReg::x30, PReg::p15), "incp x30, p15.d"); + + TEST_SINGLE(decp(SubRegSize::i8Bit, XReg::x30, PReg::p15), "decp x30, p15.b"); + TEST_SINGLE(decp(SubRegSize::i16Bit, XReg::x30, PReg::p15), "decp x30, p15.h"); + TEST_SINGLE(decp(SubRegSize::i32Bit, XReg::x30, PReg::p15), "decp x30, p15.s"); + TEST_SINGLE(decp(SubRegSize::i64Bit, XReg::x30, PReg::p15), "decp x30, p15.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE FFR write from predicate") {