diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index 226ade5f0..323c8d1f2 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -102,14 +102,14 @@ void OpDispatchBuilder::MOVHPDOp(OpcodeArgs) {
       Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, OpSize::i128Bit, Op->Flags);
       auto Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 1, 0, Dest, Src);
-      StoreResultFPR(Op, Result);
+      StoreResult_WithAVXInsert(VectorOpType::SSE, RegClass::FPR, Op, Result);
     } else {
       // If the destination is a GPR then the source is memory
       // xmm1[127:64] = src
       Ref Src = MakeSegmentAddress(Op, Op->Src[0]);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, OpSize::i128Bit, Op->Flags);
       auto Result = _VLoadVectorElement(OpSize::i128Bit, OpSize::i64Bit, Dest, 1, Src);
-      StoreResultFPR(Op, Result);
+      StoreResult_WithAVXInsert(VectorOpType::SSE, RegClass::FPR, Op, Result);
     }
   } else {
     // In this case memory is the destination and the high bits of the XMM are source
@@ -141,13 +141,13 @@ void OpDispatchBuilder::MOVLPOp(OpcodeArgs) {
       Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i128Bit});
       Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags, {.Align = OpSize::i128Bit});
       auto Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 0, 1, Dest, Src);
-      StoreResultFPR_WithOpSize(Op, Op->Dest, Result, OpSize::i128Bit, OpSize::i128Bit);
+      StoreResult_WithAVXInsert(VectorOpType::SSE, RegClass::FPR, Op, Result, OpSize::i128Bit);
     } else {
       const auto DstSize = OpSizeFromDst(Op);
       Ref Src = MakeSegmentAddress(Op, Op->Src[0]);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, DstSize, Op->Flags);
       auto Result = _VLoadVectorElement(OpSize::i128Bit, OpSize::i64Bit, Dest, 0, Src);
-      StoreResultFPR(Op, Result);
+      StoreResult_WithAVXInsert(VectorOpType::SSE, RegClass::FPR, Op, Result);
     }
   } else {
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i64Bit});
diff --git a/unittests/ASM/SSELanePreservation/movhlps.asm b/unittests/ASM/SSELanePreservation/movhlps.asm
new file mode 100644
index 000000000..bb7f1f7ab
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movhlps.asm
@@ -0,0 +1,28 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xbd7eb46a1278f793", "0x7d7ccd8836d09fc2", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0x4549bd7eb46a1278", "0x4549bd7eb46a1278", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"],
+    "XMM3": ["0x000043cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+vmovapd ymm3, [rel .data + (3 * 32)]
+
+movhlps xmm0, xmm1
+vmovhlps xmm1, xmm2, xmm3
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
diff --git a/unittests/ASM/SSELanePreservation/movhpd.asm b/unittests/ASM/SSELanePreservation/movhpd.asm
new file mode 100644
index 000000000..4ef8b3880
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movhpd.asm
@@ -0,0 +1,26 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xfdecd28fab3fa4a5", "0xfdecd28fab3fa4a5", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0xc4be43cc1ad6970b", "0xfdecd28fab3fa4a5", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+
+movhpd xmm0, [rel .data]
+vmovhpd xmm1, xmm2, [rel .data]
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
diff --git a/unittests/ASM/SSELanePreservation/movhps.asm b/unittests/ASM/SSELanePreservation/movhps.asm
new file mode 100644
index 000000000..dde939314
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movhps.asm
@@ -0,0 +1,26 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xfdecd28fab3fa4a5", "0xfdecd28fab3fa4a5", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0xc4be43cc1ad6970b", "0xfdecd28fab3fa4a5", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+
+movhps xmm0, [rel .data]
+vmovhps xmm1, xmm2, [rel .data]
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
diff --git a/unittests/ASM/SSELanePreservation/movlhps.asm b/unittests/ASM/SSELanePreservation/movlhps.asm
new file mode 100644
index 000000000..906da3ebe
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movlhps.asm
@@ -0,0 +1,28 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xfdecd28fab3fa4a5", "0x43cc1ad6970b4549", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0xc4be43cc1ad6970b", "0x000043cc1ad6970b", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"],
+    "XMM3": ["0x000043cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+vmovapd ymm3, [rel .data + (3 * 32)]
+
+movlhps xmm0, xmm1
+vmovlhps xmm1, xmm2, xmm3
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
diff --git a/unittests/ASM/SSELanePreservation/movlpd.asm b/unittests/ASM/SSELanePreservation/movlpd.asm
new file mode 100644
index 000000000..a85683629
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movlpd.asm
@@ -0,0 +1,26 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xfdecd28fab3fa4a5", "0x7d7ccd8836d09fc2", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0xfdecd28fab3fa4a5", "0x4549bd7eb46a1278", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+
+movlpd xmm0, [rel .data]
+vmovlpd xmm1, xmm2, [rel .data]
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
diff --git a/unittests/ASM/SSELanePreservation/movlps.asm b/unittests/ASM/SSELanePreservation/movlps.asm
new file mode 100644
index 000000000..b19bd8f74
--- /dev/null
+++ b/unittests/ASM/SSELanePreservation/movlps.asm
@@ -0,0 +1,26 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0xfdecd28fab3fa4a5", "0x7d7ccd8836d09fc2", "0xccdbcfc31f3ff0f3", "0x108390defebac4be"],
+    "XMM1": ["0xfdecd28fab3fa4a5", "0x4549bd7eb46a1278", "0", "0"],
+    "XMM2": ["0xc4be43cc1ad6970b", "0x4549bd7eb46a1278", "0xf793ef673dac6e4c", "0xbb7b5b3d85d34271"]
+  }
+}
+%endif
+
+vmovapd ymm0, [rel .data]
+vmovapd ymm1, [rel .data + (1 * 32)]
+vmovapd ymm2, [rel .data + (2 * 32)]
+
+movlps xmm0, [rel .data]
+vmovlps xmm1, xmm2, [rel .data]
+
+hlt
+
+align 32
+.data:
+dq 0xfdecd28fab3fa4a5, 0x7d7ccd8836d09fc2, 0xccdbcfc31f3ff0f3, 0x108390defebac4be
+dq 0x43cc1ad6970b4549, 0xbd7eb46a1278f793, 0xef673dac6e4cbb7b, 0x5b3d85d342718be9
+dq 0xc4be43cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271
+dq 0x000043cc1ad6970b, 0x4549bd7eb46a1278, 0xf793ef673dac6e4c, 0xbb7b5b3d85d34271