From 39bac4efea399ce276b767cb867b77879d29cf36 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Fri, 13 Mar 2020 17:51:07 -0700
Subject: [PATCH] Fixes 32bit memory load op

xbyak was silently treating this dword load as a 64bit load because the
destination was a 64bit register
---
 External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
index b734a4ffc..148ecfb30 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -1660,7 +1660,7 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
               }
               break;
               case 4: {
-                mov(Dst, dword [MemReg]);
+                mov(Dst.cvt32(), dword [MemReg]);
               }
               break;
               case 8: {