From 45480ef32cb332c779baab39c231a00812cd69cc Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 29 Nov 2022 18:31:33 +0000 Subject: [PATCH] OpcodeDispatcher: Handle VORPS --- .../Interface/Core/OpcodeDispatcher.cpp | 2 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 12 ++--- unittests/ASM/VEX/vorps.asm | 45 +++++++++++++++++++ 4 files changed, 55 insertions(+), 6 deletions(-) create mode 100644 unittests/ASM/VEX/vorps.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 876c4833a..1f53e5c58 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5827,6 +5827,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp}, {OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(1, 0b00, 0x56), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b00, 0x57), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x57), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 198ba15e0..72dc80a74 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -409,6 +409,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } +template +void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index b18a836b0..49c8c477d 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -62,17 +62,17 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0x53), 1, X86InstInfo{"VRCPPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b10, 0x53), 1, X86InstInfo{"VRCPSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x54), 1, X86InstInfo{"VANDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b01, 0x54), 1, X86InstInfo{"VANDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x54), 1, X86InstInfo{"VANDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b01, 0x54), 1, X86InstInfo{"VANDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b00, 0x55), 1, X86InstInfo{"VANDNPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b01, 0x55), 1, X86InstInfo{"VANDNPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x56), 1, X86InstInfo{"VORPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b01, 0x56), 1, X86InstInfo{"VORPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x56), 1, X86InstInfo{"VORPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(1, 0b01, 0x56), 1, X86InstInfo{"VORPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VXORPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VXORPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x60), 1, X86InstInfo{"VPUNPCKLBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b01, 0x61), 1, X86InstInfo{"VPUNPCKLWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vorps.asm b/unittests/ASM/VEX/vorps.asm new file mode 100644 index 000000000..5be63027a --- /dev/null +++ b/unittests/ASM/VEX/vorps.asm @@ -0,0 +1,45 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434445464748", "0x5152535455565758", "0x6162636465666768", "0x7172737475767778"], + "XMM1": ["0xCCCCCCCC75767778", "0x61626364DDDDDDDD", "0xEEEEEEEE55565758", "0x41424344FFFFFFFF"], + "XMM2": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"], + "XMM3": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"], + "XMM5": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data1] +lea rbx, [rel .data2] + +vmovapd ymm0, [rdx] +vmovapd ymm1, [rbx] + +; Register only +vorps ymm2, ymm0, ymm1 +vorps xmm3, xmm0, xmm1 + +; With memory operand +vorps ymm4, ymm0, [rbx] +vorps xmm5, xmm0, [rbx] + +hlt + +align 32 +.data1: +dq 0x4142434445464748 +dq 0x5152535455565758 +dq 0x6162636465666768 +dq 0x7172737475767778 + +.data2: +dq 0xCCCCCCCC75767778 +dq 0x61626364DDDDDDDD +dq 0xEEEEEEEE55565758 +dq 0x41424344FFFFFFFF