From 4e783202bc0bd273e39ad4a1a6f2c058bda511f2 Mon Sep 17 00:00:00 2001 From: Scott Mansell Date: Fri, 24 Jul 2020 16:30:29 +1200 Subject: [PATCH] DCSE: Rename Node2 to StoreNode --- .../IR/Passes/DeadContextStoreElimination.cpp | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp b/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp index 8c4effdd5..7d248ba9f 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp @@ -24,7 +24,7 @@ namespace { uint32_t AccessOffset; uint8_t AccessSize; FEXCore::IR::OrderedNode *Node; - FEXCore::IR::OrderedNode *Node2; + FEXCore::IR::OrderedNode *StoreNode; }; using ContextInfo = std::vector; @@ -199,6 +199,7 @@ namespace { ContextClassification->at(Offset).Accessed = Access; ContextClassification->at(Offset).AccessRegClass = FEXCore::IR::InvalidClass; ContextClassification->at(Offset).AccessOffset = 0; + ContextClassification->at(Offset).StoreNode = nullptr; }; size_t Offset = 0; SetAccess(Offset++, DefaultAccess[0]); @@ -252,8 +253,8 @@ private: std::unordered_map OffsetToBlockMap; ContextMemberInfo *FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size); - ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr); - ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr); + ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr); + ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr); void CalculateControlFlowInfo(FEXCore::IR::IREmitter *IREmit); // Block local Passes @@ -276,7 +277,7 @@ ContextMemberInfo *RCLSE::FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t O return Info; } -ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) { +ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) { LogMan::Throw::A((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size"); LogMan::Throw::A(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member"); @@ -293,13 +294,13 @@ ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, FEXCore::IR::Reg Info->AccessOffset = Offset; Info->AccessSize = Size; Info->Node = Node; - Info->Node2 = Node2; + Info->StoreNode = StoreNode; return Info; } -ContextMemberInfo *RCLSE::RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) { +ContextMemberInfo *RCLSE::RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode) { ContextMemberInfo *Info = FindMemberInfo(ClassifiedInfo, Offset, Size); - return RecordAccess(Info, RegClass, Offset, Size, AccessType, Node, Node2); + return RecordAccess(Info, RegClass, Offset, Size, AccessType, Node, StoreNode); } void RCLSE::CalculateControlFlowInfo(FEXCore::IR::IREmitter *IREmit) { @@ -465,7 +466,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) { uint32_t LastOffset = Info->AccessOffset; uint8_t LastSize = Info->AccessSize; LastAccessType LastAccess = Info->Accessed; - OrderedNode *LastNode2 = Info->Node2; + OrderedNode *LastStoreNode = Info->StoreNode; RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_WRITE, Op->Header.Args[0].GetNode(ListBegin), CodeNode); if (LastAccess == ACCESS_WRITE && @@ -475,7 +476,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) { Info->Accessed == ACCESS_WRITE) { // Remove the last store because this one overwrites it entirely // Happens when we store in to a location then store again - IREmit->Remove(LastNode2); + IREmit->Remove(LastStoreNode); } } else if (IROp->Op == OP_LOADCONTEXT) {