From 8762bc1fa31a3cca83814e32ffe34cf31d6425ca Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 21 Feb 2024 12:48:15 -0400 Subject: [PATCH 1/2] OpcodeDispatcher: simplify CalculateAF signature - Res is unused - SrcSize doesn't matter since we ignore the high bits, might as well always use 32-bit, it doesn't matter Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 2 +- .../Interface/Core/OpcodeDispatcher/Flags.cpp | 16 ++++++---------- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 7e0df0530..6093be52a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1739,7 +1739,7 @@ private: OrderedNode *LoadAF(); void FixupAF(); void CalculatePF(OrderedNode *Res); - void CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2); + void CalculateAF(OrderedNode *Src1, OrderedNode *Src2); void CalculateOF(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool Sub); void CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index 4c45e8b13..7d3c4f039 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -282,7 +282,7 @@ void OpDispatchBuilder::CalculatePF(OrderedNode *Res) { SetRFLAG(Res); } -void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) { +void OpDispatchBuilder::CalculateAF(OrderedNode *Src1, OrderedNode *Src2) { // We only care about bit 4 in the subsequent XOR. If we'll XOR with 0, // there's no sense XOR'ing at all. This affects INC. uint64_t Const; @@ -294,7 +294,7 @@ void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode // We store the XOR of the arguments. At read time, we XOR with the // appropriate bit of the result (available as the PF flag) and extract the // appropriate bit. - OrderedNode *XorRes = _Xor(OpSize, Src1, Src2); + OrderedNode *XorRes = _Xor(OpSize::i32Bit, Src1, Src2); SetRFLAG(XorRes); } @@ -491,7 +491,7 @@ void OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, Or auto One = _Constant(1); auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit; - CalculateAF(OpSize, Res, Src1, Src2); + CalculateAF(Src1, Src2); CalculatePF(Res); if (SrcSize >= 4) { @@ -520,7 +520,7 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or auto One = _Constant(1); auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit; - CalculateAF(OpSize, Res, Src1, Src2); + CalculateAF(Src1, Src2); CalculatePF(Res); if (SrcSize >= 4) { @@ -551,9 +551,7 @@ void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, Or } void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) { - auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit; - - CalculateAF(OpSize, Res, Src1, Src2); + CalculateAF(Src1, Src2); CalculatePF(Res); // Stash CF before stomping over it @@ -571,9 +569,7 @@ void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, Or } void OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) { - auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit; - - CalculateAF(OpSize, Res, Src1, Src2); + CalculateAF(Src1, Src2); CalculatePF(Res); // Stash CF before stomping over it From 30ff225e80d8a42af28543c0679233aba0ff75d3 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 21 Feb 2024 12:49:14 -0400 Subject: [PATCH 2/2] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/Atomics.json | 4 +- .../InstructionCountCI/FlagM/Atomics.json | 4 +- .../InstructionCountCI/FlagM/FlagOpts.json | 4 +- .../InstructionCountCI/FlagM/Primary.json | 42 +++++++++---------- .../FlagM/PrimaryGroup.json | 10 ++--- .../InstructionCountCI/FlagM/Secondary.json | 8 ++-- unittests/InstructionCountCI/Primary.json | 42 +++++++++---------- .../InstructionCountCI/PrimaryGroup.json | 10 ++--- unittests/InstructionCountCI/Secondary.json | 6 +-- 9 files changed, 65 insertions(+), 65 deletions(-) diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 20a8ccf68..11e71668b 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -322,7 +322,7 @@ "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", "add x26, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "cmn x20, x5" ] }, @@ -404,7 +404,7 @@ "mov x20, x7", "ldaddal x20, x7, [x4]", "add x26, x7, x20", - "eor x27, x7, x20", + "eor w27, w7, w20", "cmn x7, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 7d5f4f594..71a0a7aa4 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -309,7 +309,7 @@ "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", "add x26, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "cmn x20, x5" ] }, @@ -357,7 +357,7 @@ "mov x20, x7", "ldaddal x20, x7, [x4]", "add x26, x7, x20", - "eor x27, x7, x20", + "eor w27, w7, w20", "cmn x7, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index b2d962d02..d5e3892cf 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -44,7 +44,7 @@ "add x20, x6, x20", "mov x21, x5", "sub x5, x21, x20", - "eor x27, x21, x6", + "eor w27, w21, w6", "mov x26, x5", "cfinv", "sbcs xzr, x21, x6", @@ -66,7 +66,7 @@ "add x20, x6, x20", "mov x21, x5", "add x5, x21, x20", - "eor x27, x21, x6", + "eor w27, w21, w6", "mov x26, x5", "adcs xzr, x21, x6", "cfinv" diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 39665ecc1..143599f9a 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -54,7 +54,7 @@ "ExpectedArm64ASM": [ "mov x20, x7", "add x7, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "mov x26, x7", "cmn x20, x5" ] @@ -114,7 +114,7 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add x5, x20, x7", - "eor x27, x20, x7", + "eor w27, w20, w7", "mov x26, x5", "cmn x20, x7" ] @@ -212,7 +212,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmn x21, x20" ] @@ -463,7 +463,7 @@ "add x20, x5, x20", "mov x21, x7", "add x7, x21, x20", - "eor x27, x21, x5", + "eor w27, w21, w5", "mov x26, x7", "adcs xzr, x21, x5" ] @@ -558,7 +558,7 @@ "add x20, x7, x20", "mov x21, x5", "add x5, x21, x20", - "eor x27, x21, x7", + "eor w27, w21, w7", "mov x26, x5", "adcs xzr, x21, x7" ] @@ -714,7 +714,7 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "adcs xzr, x22, x20" ] @@ -799,7 +799,7 @@ "add x20, x5, x20", "mov x21, x7", "sub x7, x21, x20", - "eor x27, x21, x5", + "eor w27, w21, w5", "mov x26, x7", "cfinv", "sbcs xzr, x21, x5", @@ -898,7 +898,7 @@ "add x20, x7, x20", "mov x21, x5", "sub x5, x21, x20", - "eor x27, x21, x7", + "eor w27, w21, w7", "mov x26, x5", "cfinv", "sbcs xzr, x21, x7", @@ -1062,7 +1062,7 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "cfinv", "sbcs xzr, x22, x20", @@ -1265,7 +1265,7 @@ "ExpectedArm64ASM": [ "mov x20, x7", "sub x7, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "mov x26, x7", "cmp x20, x5", "cfinv" @@ -1329,7 +1329,7 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub x5, x20, x7", - "eor x27, x20, x7", + "eor w27, w20, w7", "mov x26, x5", "cmp x20, x7", "cfinv" @@ -1435,7 +1435,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmp x21, x20", "cfinv" @@ -1636,7 +1636,7 @@ "Comment": "0x39", "ExpectedArm64ASM": [ "sub x26, x7, x5", - "eor x27, x7, x5", + "eor w27, w7, w5", "cmp x7, x5", "cfinv" ] @@ -1690,7 +1690,7 @@ ], "ExpectedArm64ASM": [ "sub x26, x5, x7", - "eor x27, x5, x7", + "eor w27, w5, w7", "cmp x5, x7", "cfinv" ] @@ -1780,7 +1780,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "sub x26, x4, x20", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "cfinv" ] @@ -2127,7 +2127,7 @@ "sub x22, x23, x22, lsl #4", "add x11, x11, x22", "add x10, x10, x22", - "eor x27, x21, x20", + "eor w27, w21, w20", "cmp x21, x20", "cfinv" ] @@ -2208,7 +2208,7 @@ "ldr x21, [x11]", "ldr x22, [x10]", "sub x26, x22, x21", - "eor x27, x22, x21", + "eor w27, w22, w21", "cmp x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", @@ -2294,7 +2294,7 @@ "ldr x21, [x11]", "ldr x22, [x10]", "sub x26, x22, x21", - "eor x27, x22, x21", + "eor w27, w22, w21", "cmp x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", @@ -2424,7 +2424,7 @@ "mov w22, #0x8", "sub x21, x22, x21, lsl #4", "add x11, x11, x21", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "cfinv" ] @@ -2501,7 +2501,7 @@ "cbz x5, #+0x28", "ldr x21, [x11]", "sub x26, x4, x21", - "eor x27, x4, x21", + "eor w27, w4, w21", "cmp x4, x21", "cfinv", "sub x5, x5, #0x1 (1)", @@ -2582,7 +2582,7 @@ "cbz x5, #+0x28", "ldr x21, [x11]", "sub x26, x4, x21", - "eor x27, x4, x21", + "eor w27, w4, w21", "cmp x4, x21", "cfinv", "sub x5, x5, #0x1 (1)", diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index a5b987f98..5afa1a7cf 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -835,7 +835,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmn x21, x20" ] @@ -883,7 +883,7 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "adcs xzr, x22, x20" ] @@ -913,7 +913,7 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "cfinv", "sbcs xzr, x22, x20", @@ -958,7 +958,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmp x21, x20", "cfinv" @@ -1001,7 +1001,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "sub x26, x4, x20", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "cfinv" ] diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 3ed8ed003..acf53989a 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1071,7 +1071,7 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub x26, x4, x20", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "cfinv", "mov x4, x20", @@ -1087,7 +1087,7 @@ "casal x1, x7, [x20]", "mov x4, x1", "sub x26, x20, x4", - "eor x27, x20, x4", + "eor w27, w20, w4", "cmp x20, x4", "cfinv" ] @@ -1610,7 +1610,7 @@ "mov x21, x7", "add x4, x20, x21", "mov x7, x20", - "eor x27, x20, x21", + "eor w27, w20, w21", "mov x26, x4", "cmn x20, x21" ] @@ -1622,7 +1622,7 @@ "mov x20, x7", "ldaddal x20, x7, [x4]", "add x26, x7, x20", - "eor x27, x7, x20", + "eor w27, w7, w20", "cmn x7, x20" ] }, diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 99e2ac88b..d9ee2d145 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -53,7 +53,7 @@ "ExpectedArm64ASM": [ "mov x20, x7", "add x7, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "mov x26, x7", "cmn x20, x5" ] @@ -113,7 +113,7 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add x5, x20, x7", - "eor x27, x20, x7", + "eor w27, w20, w7", "mov x26, x5", "cmn x20, x7" ] @@ -211,7 +211,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmn x21, x20" ] @@ -464,7 +464,7 @@ "add x20, x5, x20", "mov x21, x7", "add x7, x21, x20", - "eor x27, x21, x5", + "eor w27, w21, w5", "mov x26, x7", "adcs xzr, x21, x5" ] @@ -561,7 +561,7 @@ "add x20, x7, x20", "mov x21, x5", "add x5, x21, x20", - "eor x27, x21, x7", + "eor w27, w21, w7", "mov x26, x5", "adcs xzr, x21, x7" ] @@ -721,7 +721,7 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "adcs xzr, x22, x20" ] @@ -812,7 +812,7 @@ "add x20, x5, x20", "mov x21, x7", "sub x7, x21, x20", - "eor x27, x21, x5", + "eor w27, w21, w5", "mov x26, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -921,7 +921,7 @@ "add x20, x7, x20", "mov x21, x5", "sub x5, x21, x20", - "eor x27, x21, x7", + "eor w27, w21, w7", "mov x26, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1105,7 +1105,7 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -1318,7 +1318,7 @@ "ExpectedArm64ASM": [ "mov x20, x7", "sub x7, x20, x5", - "eor x27, x20, x5", + "eor w27, w20, w5", "mov x26, x7", "cmp x20, x5", "mrs x20, nzcv", @@ -1390,7 +1390,7 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub x5, x20, x7", - "eor x27, x20, x7", + "eor w27, w20, w7", "mov x26, x5", "cmp x20, x7", "mrs x20, nzcv", @@ -1512,7 +1512,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmp x21, x20", "mrs x20, nzcv", @@ -1721,7 +1721,7 @@ "Comment": "0x39", "ExpectedArm64ASM": [ "sub x26, x7, x5", - "eor x27, x7, x5", + "eor w27, w7, w5", "cmp x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1783,7 +1783,7 @@ ], "ExpectedArm64ASM": [ "sub x26, x5, x7", - "eor x27, x5, x7", + "eor w27, w5, w7", "cmp x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1889,7 +1889,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "sub x26, x4, x20", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -3231,7 +3231,7 @@ "sub x22, x23, x22, lsl #4", "add x11, x11, x22", "add x10, x10, x22", - "eor x27, x21, x20", + "eor w27, w21, w20", "cmp x21, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -3320,7 +3320,7 @@ "ldr x21, [x11]", "ldr x22, [x10]", "sub x26, x22, x21", - "eor x27, x22, x21", + "eor w27, w22, w21", "cmp x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3414,7 +3414,7 @@ "ldr x21, [x11]", "ldr x22, [x10]", "sub x26, x22, x21", - "eor x27, x22, x21", + "eor w27, w22, w21", "cmp x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3798,7 +3798,7 @@ "mov w22, #0x8", "sub x21, x22, x21, lsl #4", "add x11, x11, x21", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -3883,7 +3883,7 @@ "cbz x5, #+0x30", "ldr x21, [x11]", "sub x26, x4, x21", - "eor x27, x4, x21", + "eor w27, w4, w21", "cmp x4, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3972,7 +3972,7 @@ "cbz x5, #+0x30", "ldr x21, [x11]", "sub x26, x4, x21", - "eor x27, x4, x21", + "eor w27, w4, w21", "cmp x4, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index c46050617..d0cb9c68b 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -898,7 +898,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmn x21, x20" ] @@ -946,7 +946,7 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "adcs xzr, x22, x20" ] @@ -980,7 +980,7 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x27, x22, x20", + "eor w27, w22, w20", "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -1031,7 +1031,7 @@ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x27, x21, x20", + "eor w27, w21, w20", "mov x26, x4", "cmp x21, x20", "mrs x20, nzcv", @@ -1078,7 +1078,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "sub x26, x4, x20", - "eor x27, x4, x20", + "eor w27, w4, w20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index e58dd8659..9e090a6ff 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -2011,7 +2011,7 @@ "casal x1, x7, [x20]", "mov x4, x1", "sub x26, x20, x4", - "eor x27, x20, x4", + "eor w27, w20, w4", "cmp x20, x4", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2623,7 +2623,7 @@ "mov x21, x7", "add x4, x20, x21", "mov x7, x20", - "eor x27, x20, x21", + "eor w27, w20, w21", "mov x26, x4", "cmn x20, x21" ] @@ -2635,7 +2635,7 @@ "mov x20, x7", "ldaddal x20, x7, [x4]", "add x26, x7, x20", - "eor x27, x7, x20", + "eor w27, w7, w20", "cmn x7, x20" ] },