From 57ebfceb4887ed694fc42027f1e7968bb2991c3a Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sat, 29 Jan 2022 23:37:05 -0800
Subject: [PATCH] HostFeatures: Check for CRC32 op support

Available with CRC32 bit on Arm64 or SSE4.2 on x86-64
---
 External/FEXCore/Source/Interface/Core/HostFeatures.cpp | 2 ++
 External/FEXCore/Source/Interface/Core/HostFeatures.h   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/External/FEXCore/Source/Interface/Core/HostFeatures.cpp b/External/FEXCore/Source/Interface/Core/HostFeatures.cpp
index 5db0303f9..e53000ea2 100644
--- a/External/FEXCore/Source/Interface/Core/HostFeatures.cpp
+++ b/External/FEXCore/Source/Interface/Core/HostFeatures.cpp
@@ -53,6 +53,7 @@ HostFeatures::HostFeatures() {
 #ifdef _M_ARM_64
   auto Features = vixl::CPUFeatures::InferFromOS();
   SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
+  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
   SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
   // Only supported when FEAT_AFP is supported
   SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
@@ -78,6 +79,7 @@ HostFeatures::HostFeatures() {
 #ifdef _M_X86_64
   Xbyak::util::Cpu Features{};
   SupportsAES = Features.has(Xbyak::util::Cpu::tAESNI);
+  SupportsCRC = Features.has(Xbyak::util::Cpu::tSSE42);
   SupportsFlushInputsToZero = true;
   SupportsFloatExceptions = true;
 #else
diff --git a/External/FEXCore/Source/Interface/Core/HostFeatures.h b/External/FEXCore/Source/Interface/Core/HostFeatures.h
index c87ae6149..4d830f68b 100644
--- a/External/FEXCore/Source/Interface/Core/HostFeatures.h
+++ b/External/FEXCore/Source/Interface/Core/HostFeatures.h
@@ -15,6 +15,7 @@ class HostFeatures final {
     uint32_t DCacheLineSize{};
     uint32_t ICacheLineSize{};
     bool SupportsAES{};
+    bool SupportsCRC{};
     bool SupportsCLZERO{};
     bool SupportsAtomics{};
     bool SupportsRCPC{};