From c819afebead5b82ac971e1f6b8a105d8b70bff4c Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Mon, 14 Sep 2020 17:22:24 -0700
Subject: [PATCH 1/2] Unit test to ensure ASHR Sexts to the correct sizes

---
 unittests/ASM/PrimaryGroup/2_D1_07_2.asm | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 unittests/ASM/PrimaryGroup/2_D1_07_2.asm

diff --git a/unittests/ASM/PrimaryGroup/2_D1_07_2.asm b/unittests/ASM/PrimaryGroup/2_D1_07_2.asm
new file mode 100644
index 000000000..411cbcffa
--- /dev/null
+++ b/unittests/ASM/PrimaryGroup/2_D1_07_2.asm
@@ -0,0 +1,31 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x414141414141FFFF",
+    "RBX": "0x00000000FFFFFFFF",
+    "RDX": "0xFFFFFFFFFFFFFFFF",
+    "RSI": "0x42424242424242FF"
+  }
+}
+%endif
+
+mov rdx, 0xe0000000
+
+mov rax, 0x4141414141418000
+mov rbx, 0x80000000
+mov rdx, 0x8000000000000000
+mov rsi, 0x4242424242424280
+
+mov cl, 7
+sar sil, cl
+
+mov cl, 15
+sar ax, cl
+
+mov cl, 31
+sar ebx, cl
+
+mov cl, 63
+sar rdx, cl
+
+hlt

From c875beb74b81d9623cfbd730e44daf6163f40df4 Mon Sep 17 00:00:00 2001
From: Stefanos Kornilios Mitsis Poiitidis <stef@skmp.dev>
Date: Tue, 15 Sep 2020 17:02:09 +0300
Subject: [PATCH 2/2] OP_ASHR: Fix zext semantics after sext

---
 .../Source/Interface/Core/Interpreter/InterpreterCore.cpp | 8 ++++----
 .../FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp    | 4 ++++
 External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp | 4 ++--
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp
index 183edadb7..10bb27362 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp
@@ -764,16 +764,16 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
             uint8_t Mask = OpSize * 8 - 1;
             switch (OpSize) {
               case 1:
-                GD = static_cast<int8_t>(Src1) >> (Src2 & Mask);
+                GD = (uint8_t)(static_cast<int8_t>(Src1) >> (Src2 & Mask));
                 break;
               case 2:
-                GD = static_cast<int16_t>(Src1) >> (Src2 & Mask);
+                GD = (uint16_t)(static_cast<int16_t>(Src1) >> (Src2 & Mask));
                 break;
               case 4:
-                GD = static_cast<int32_t>(Src1) >> (Src2 & Mask);
+                GD = (uint32_t)(static_cast<int32_t>(Src1) >> (Src2 & Mask));
                 break;
               case 8:
-                GD = static_cast<int64_t>(Src1) >> (Src2 & Mask);
+                GD = (uint64_t)(static_cast<int64_t>(Src1) >> (Src2 & Mask));
                 break;
               default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
             };
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
index f6d9c9c04..40e4413cd 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -413,9 +413,13 @@ DEF_OP(Ashr) {
   uint8_t OpSize = IROp->Size;
   if (OpSize == 8)
     asrv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
+  else if (OpSize == 4) {
+    asrv(GetReg<RA_32>(Node), GetReg<RA_32>(Op->Header.Args[0].ID()), GetReg<RA_32>(Op->Header.Args[1].ID()));
+  }
   else {
     sbfx(TMP1.X(), GetReg<RA_64>(Op->Header.Args[0].ID()), 0, OpSize * 8);
     asrv(GetReg<RA_64>(Node), TMP1.X(), GetReg<RA_64>(Op->Header.Args[1].ID()));
+    ubfx(GetReg<RA_64>(Node),GetReg<RA_64>(Node), 0, OpSize * 8);
   }
 }
 
diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
index 648554570..0853d84f5 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -1513,12 +1513,12 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
           case 1:
             movsx(rax, GetSrc<RA_8>(Op->Header.Args[0].ID()));
             sar(al, cl);
-            movsx(GetDst<RA_64>(Node), al);
+            movzx(GetDst<RA_64>(Node), al);
           break;
           case 2:
             movsx(rax, GetSrc<RA_16>(Op->Header.Args[0].ID()));
             sar(ax, cl);
-            movsx(GetDst<RA_64>(Node), ax);
+            movzx(GetDst<RA_64>(Node), ax);
           break;
           case 4:
             mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[0].ID()));