From c409ea78bc38e944ce431b7ffff770511b1e729c Mon Sep 17 00:00:00 2001 From: Lioncache Date: Wed, 23 Aug 2023 13:52:12 -0400 Subject: [PATCH 1/4] OpcodeDispatcher: Remove unnecessary moves from VMOV{A,U}PS/VMOV{A,U}PD Zero-extension will occur automatically upon storing if necessary. We can also join the SSE and AVX implementations together. --- .../Interface/Core/OpcodeDispatcher.cpp | 44 +++++++++--------- .../Source/Interface/Core/OpcodeDispatcher.h | 7 +-- .../Core/OpcodeDispatcher/Vector.cpp | 28 +---------- unittests/InstructionCountCI/VEX_map1.json | 46 +++++++++++++++++++ 4 files changed, 72 insertions(+), 53 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 8a653a72d..31b779185 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5815,12 +5815,12 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { #define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode)) static constexpr std::tuple AVXTable[] = { - {OPD(1, 0b00, 0x10), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, - {OPD(1, 0b01, 0x10), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b00, 0x10), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, + {OPD(1, 0b01, 0x10), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {OPD(1, 0b10, 0x10), 1, &OpDispatchBuilder::VMOVSSOp}, {OPD(1, 0b11, 0x10), 1, &OpDispatchBuilder::VMOVSDOp}, - {OPD(1, 0b00, 0x11), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, - {OPD(1, 0b01, 0x11), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b00, 0x11), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, + {OPD(1, 0b01, 0x11), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {OPD(1, 0b10, 0x11), 1, &OpDispatchBuilder::VMOVSSOp}, {OPD(1, 0b11, 0x11), 1, &OpDispatchBuilder::VMOVSDOp}, @@ -5843,10 +5843,10 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x17), 1, &OpDispatchBuilder::VMOVHPOp}, {OPD(1, 0b01, 0x17), 1, &OpDispatchBuilder::VMOVHPOp}, - {OPD(1, 0b00, 0x28), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, - {OPD(1, 0b01, 0x28), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, - {OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, - {OPD(1, 0b01, 0x29), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, + {OPD(1, 0b00, 0x28), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, + {OPD(1, 0b01, 0x28), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, + {OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, + {OPD(1, 0b01, 0x29), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, {OPD(1, 0b10, 0x2A), 1, &OpDispatchBuilder::AVXCVTGPR_To_FPR<4>}, {OPD(1, 0b11, 0x2A), 1, &OpDispatchBuilder::AVXCVTGPR_To_FPR<8>}, @@ -5946,8 +5946,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b01, 0x6D), 1, &OpDispatchBuilder::VPUNPCKHOp<8>}, {OPD(1, 0b01, 0x6E), 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, - {OPD(1, 0b01, 0x6F), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, - {OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b01, 0x6F), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, + {OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {OPD(1, 0b01, 0x70), 1, &OpDispatchBuilder::VPSHUFWOp<4, true>}, {OPD(1, 0b10, 0x70), 1, &OpDispatchBuilder::VPSHUFWOp<2, false>}, @@ -5967,8 +5967,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b01, 0x7E), 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, {OPD(1, 0b10, 0x7E), 1, &OpDispatchBuilder::MOVQOp}, - {OPD(1, 0b01, 0x7F), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, - {OPD(1, 0b10, 0x7F), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b01, 0x7F), 1, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, + {OPD(1, 0b10, 0x7F), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {OPD(1, 0b00, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<4, false>}, {OPD(1, 0b01, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<8, false>}, @@ -6023,7 +6023,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b01, 0xEE), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0xEF), 1, &OpDispatchBuilder::AVXVectorALUOp}, - {OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {OPD(1, 0b01, 0xF1), 1, &OpDispatchBuilder::VPSLLOp<2>}, {OPD(1, 0b01, 0xF2), 1, &OpDispatchBuilder::VPSLLOp<4>}, {OPD(1, 0b01, 0xF3), 1, &OpDispatchBuilder::VPSLLOp<8>}, @@ -6344,9 +6344,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0x3F, 1, &OpDispatchBuilder::ThunkOp}, {0x40, 16, &OpDispatchBuilder::CMOVOp}, {0x6E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, - {0x6F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x6F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0x7E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, - {0x7F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x7F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0x80, 16, &OpDispatchBuilder::CondJUMPOp}, {0x90, 16, &OpDispatchBuilder::SETccOp}, {0xA0, 1, &OpDispatchBuilder::PUSHSegmentOp}, @@ -6375,12 +6375,12 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0xC8, 8, &OpDispatchBuilder::BSWAPOp}, // SSE - {0x10, 2, &OpDispatchBuilder::MOVUPSOp}, + {0x10, 2, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0x12, 2, &OpDispatchBuilder::MOVLPOp}, {0x14, 1, &OpDispatchBuilder::PUNPCKLOp<4>}, {0x15, 1, &OpDispatchBuilder::PUNPCKHOp<4>}, {0x16, 2, &OpDispatchBuilder::MOVHPDOp}, - {0x28, 2, &OpDispatchBuilder::MOVAPSOp}, + {0x28, 2, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, {0x2A, 1, &OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float<4, false>}, {0x2B, 1, &OpDispatchBuilder::MOVVectorNTOp}, {0x2C, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int<4, false, false>}, @@ -6623,10 +6623,10 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0x5D, 1, &OpDispatchBuilder::VectorScalarALUOp}, {0x5E, 1, &OpDispatchBuilder::VectorScalarALUOp}, {0x5F, 1, &OpDispatchBuilder::VectorScalarALUOp}, - {0x6F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x6F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, true, false>}, {0x7E, 1, &OpDispatchBuilder::MOVQOp}, - {0x7F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x7F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0xB8, 1, &OpDispatchBuilder::PopcountOp}, {0xBC, 1, &OpDispatchBuilder::TZCNT}, {0xBD, 1, &OpDispatchBuilder::LZCNT}, @@ -6669,7 +6669,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0x15, 1, &OpDispatchBuilder::PUNPCKHOp<8>}, {0x16, 2, &OpDispatchBuilder::MOVHPDOp}, {0x19, 7, &OpDispatchBuilder::NOPOp}, - {0x28, 2, &OpDispatchBuilder::MOVAPSOp}, + {0x28, 2, &OpDispatchBuilder::MOVAPS_MOVAPDOp}, {0x2A, 1, &OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float<4, true>}, {0x2B, 1, &OpDispatchBuilder::MOVVectorNTOp}, {0x2C, 1, &OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int<8, false>}, @@ -6706,7 +6706,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0x6C, 1, &OpDispatchBuilder::PUNPCKLOp<8>}, {0x6D, 1, &OpDispatchBuilder::PUNPCKHOp<8>}, {0x6E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, - {0x6F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x6F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0x70, 1, &OpDispatchBuilder::PSHUFDOp<4, false, true>}, {0x74, 1, &OpDispatchBuilder::VectorALUOp}, @@ -6716,7 +6716,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {0x7C, 1, &OpDispatchBuilder::VectorALUOp}, {0x7D, 1, &OpDispatchBuilder::HSUBP<8>}, {0x7E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR}, - {0x7F, 1, &OpDispatchBuilder::MOVUPSOp}, + {0x7F, 1, &OpDispatchBuilder::MOVUPS_MOVUPDOp}, {0xC2, 1, &OpDispatchBuilder::VFCMPOp<8, false>}, {0xC4, 1, &OpDispatchBuilder::PINSROp<2>}, {0xC5, 1, &OpDispatchBuilder::PExtrOp<2>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 4cd54ac6a..4b7cf8a86 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -316,8 +316,8 @@ public: void SGDTOp(OpcodeArgs); // SSE - void MOVAPSOp(OpcodeArgs); - void MOVUPSOp(OpcodeArgs); + void MOVAPS_MOVAPDOp(OpcodeArgs); + void MOVUPS_MOVUPDOp(OpcodeArgs); void MOVLPOp(OpcodeArgs); void MOVHPDOp(OpcodeArgs); void MOVSDOp(OpcodeArgs); @@ -474,9 +474,6 @@ public: template void VMASKMOVOp(OpcodeArgs); - void VMOVAPS_VMOVAPD_Op(OpcodeArgs); - void VMOVUPS_VMOVUPD_Op(OpcodeArgs); - void VMOVHPOp(OpcodeArgs); void VMOVLPOp(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index a5e3c465c..cf6562bdc 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -45,36 +45,12 @@ void OpDispatchBuilder::VMOVVectorNTOp(OpcodeArgs) { StoreResult(FPRClass, Op, Src, 1, MemoryAccessType::ACCESS_STREAM); } -void OpDispatchBuilder::MOVAPSOp(OpcodeArgs) { +void OpDispatchBuilder::MOVAPS_MOVAPDOp(OpcodeArgs) { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); StoreResult(FPRClass, Op, Src, -1); } -void OpDispatchBuilder::VMOVAPS_VMOVAPD_Op(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); - const auto Is128BitDest = GetDstSize(Op) == Core::CPUState::XMM_SSE_REG_SIZE; - - if (Op->Dest.IsGPR() && Is128BitDest) { - // Clear the upper lane - Src = _VMov(16, Src); - } - - StoreResult(FPRClass, Op, Src, -1); -} - -void OpDispatchBuilder::VMOVUPS_VMOVUPD_Op(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 1); - const auto Is128BitDest = GetDstSize(Op) == Core::CPUState::XMM_SSE_REG_SIZE; - - if (Op->Dest.IsGPR() && Is128BitDest) { - // Clear the upper lane - Src = _VMov(16, Src); - } - - StoreResult(FPRClass, Op, Src, 1); -} - -void OpDispatchBuilder::MOVUPSOp(OpcodeArgs) { +void OpDispatchBuilder::MOVUPS_MOVUPDOp(OpcodeArgs) { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 1); StoreResult(FPRClass, Op, Src, 1); } diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 899752d5a..d89d71928 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -3506,6 +3506,29 @@ "mov z16.d, p7/m, z4.d" ] }, + "vmovaps xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x29 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" + ] + }, + "vmovaps ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x29 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" + ] + }, "vmovapd xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", @@ -3528,6 +3551,29 @@ "mov z16.d, p7/m, z4.d" ] }, + "vmovapd xmm0, xmm1": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x29 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" + ] + }, + "vmovapd ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x29 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" + ] + }, "vmovaps [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", From 7d05797e82ad58d2accd76e61714ea9f4a11e5cb Mon Sep 17 00:00:00 2001 From: Lioncache Date: Wed, 23 Aug 2023 14:14:33 -0400 Subject: [PATCH 2/4] OpcodeDispatcher: Remove redundant moves from VMOVHPOp Zero-extension will automatically occur if necessary upon storing. --- FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp | 3 --- unittests/InstructionCountCI/VEX_map1.json | 6 ++---- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index cf6562bdc..497108c2c 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -88,9 +88,6 @@ void OpDispatchBuilder::VMOVHPOp(OpcodeArgs) { OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags, 8); OrderedNode *Result = _VInsElement(16, 8, 1, 0, Src1, Src2); - // Clear the upper lane. - Result = _VMov(16, Result); - StoreResult(FPRClass, Op, Result, -1); } else { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 16); diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index d89d71928..0ebe74138 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -443,7 +443,7 @@ ] }, "vmovhps xmm0, xmm1, [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": [ "Map 1 0b00 0x16 128-bit" @@ -454,12 +454,11 @@ "ldr d5, [x4]", "mov v4.d[1], v5.d[0]", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, "vmovhpd xmm0, xmm1, [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": [ "Map 1 0b01 0x16 128-bit" @@ -470,7 +469,6 @@ "ldr d5, [x4]", "mov v4.d[1], v5.d[0]", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, From bcba3700c842fdf7eac33d135b105e3de0b59e15 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Wed, 23 Aug 2023 14:17:25 -0400 Subject: [PATCH 3/4] OpcodeDispatcher: Remove redundant moves from VMOVVectorNTOp Zero-extension will automatically occur if necessary upon storing. We can also join the SSE and AVX implementations. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 8 ++++---- FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 2 -- .../Interface/Core/OpcodeDispatcher/Vector.cpp | 12 ------------ 3 files changed, 4 insertions(+), 18 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 31b779185..7b492e51e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5851,8 +5851,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b10, 0x2A), 1, &OpDispatchBuilder::AVXCVTGPR_To_FPR<4>}, {OPD(1, 0b11, 0x2A), 1, &OpDispatchBuilder::AVXCVTGPR_To_FPR<8>}, - {OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp}, - {OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::MOVVectorNTOp}, + {OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::MOVVectorNTOp}, {OPD(1, 0b10, 0x2C), 1, &OpDispatchBuilder::CVTFPR_To_GPR<4, false>}, {OPD(1, 0b11, 0x2C), 1, &OpDispatchBuilder::CVTFPR_To_GPR<8, false>}, @@ -6012,7 +6012,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b10, 0xE6), 1, &OpDispatchBuilder::AVXVector_CVT_Int_To_Float<4, true>}, {OPD(1, 0b11, 0xE6), 1, &OpDispatchBuilder::AVXVector_CVT_Float_To_Int<8, true, true>}, - {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::MOVVectorNTOp}, {OPD(1, 0b01, 0xE8), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0xE9), 1, &OpDispatchBuilder::AVXVectorALUOp}, @@ -6077,7 +6077,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x28), 1, &OpDispatchBuilder::VPMULLOp<4, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, - {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::MOVVectorNTOp}, {OPD(2, 0b01, 0x2B), 1, &OpDispatchBuilder::VPACKUSOp<4>}, {OPD(2, 0b01, 0x2C), 1, &OpDispatchBuilder::VMASKMOVOp<4, false>}, {OPD(2, 0b01, 0x2D), 1, &OpDispatchBuilder::VMASKMOVOp<8, false>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 4b7cf8a86..2bc7bc6b9 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -484,8 +484,6 @@ public: void VMOVSDOp(OpcodeArgs); void VMOVSSOp(OpcodeArgs); - void VMOVVectorNTOp(OpcodeArgs); - void VMPSADBWOp(OpcodeArgs); template diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 497108c2c..7bf1e87d3 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -33,18 +33,6 @@ void OpDispatchBuilder::MOVVectorNTOp(OpcodeArgs) { StoreResult(FPRClass, Op, Src, 1, MemoryAccessType::ACCESS_STREAM); } -void OpDispatchBuilder::VMOVVectorNTOp(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 1, true, false, MemoryAccessType::ACCESS_STREAM); - const auto Is128BitDest = GetDstSize(Op) == Core::CPUState::XMM_SSE_REG_SIZE; - - if (Op->Dest.IsGPR() && Is128BitDest) { - // Clear the upper lane - Src = _VMov(16, Src); - } - - StoreResult(FPRClass, Op, Src, 1, MemoryAccessType::ACCESS_STREAM); -} - void OpDispatchBuilder::MOVAPS_MOVAPDOp(OpcodeArgs) { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); StoreResult(FPRClass, Op, Src, -1); From 8e7e91d61f90e0b9a47c8964d4abe9244c670ccf Mon Sep 17 00:00:00 2001 From: Lioncache Date: Wed, 23 Aug 2023 14:23:01 -0400 Subject: [PATCH 4/4] OpcodeDispatcher: Remove redundant moves in VMOVLPOp Zero-extension will automatically occur upon storing if necessary. --- FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp | 3 --- unittests/InstructionCountCI/VEX_map1.json | 6 ++---- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7bf1e87d3..684542084 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -113,9 +113,6 @@ void OpDispatchBuilder::VMOVLPOp(OpcodeArgs) { OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags, 8); OrderedNode *Result = _VInsElement(16, 8, 0, 0, Src1, Src2); - // Clear the upper lane. - Result = _VMov(16, Result); - StoreResult(FPRClass, Op, Result, -1); } else { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 8); diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 0ebe74138..f530e3e06 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -215,7 +215,7 @@ ] }, "vmovlps xmm0, xmm1, [rax]": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Insert in to first element could be more optimal, which is the common case.", @@ -226,12 +226,11 @@ "ldr q5, [x4]", "mov v4.d[0], v5.d[0]", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, "vmovlpd xmm0, xmm1, [rax]": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Insert in to first element could be more optimal, which is the common case.", @@ -242,7 +241,6 @@ "ldr q5, [x4]", "mov v4.d[0], v5.d[0]", "mov v4.16b, v4.16b", - "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] },