From 91f48c63ff0ebdc662a4ef7fcb14fa641b71780e Mon Sep 17 00:00:00 2001
From: CallumDev <callum.mcging@gmail.com>
Date: Mon, 21 Feb 2022 00:06:37 +1030
Subject: [PATCH] Implement F64 ops in Interpreter

---
 .../Interface/Core/Interpreter/F80Ops.cpp     | 75 +++++++++++++++++++
 .../Core/Interpreter/InterpreterOps.cpp       | 11 +++
 .../Core/Interpreter/InterpreterOps.h         | 11 +++
 3 files changed, 97 insertions(+)

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp
index a0143bdad..26fedb250 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp
@@ -356,6 +356,81 @@ DEF_OP(F80BCDSTORE) {
   memcpy(GDP, BCD, 10);
 }
 
+DEF_OP(F64SIN) {
+  auto Op = IROp->C<IR::IROp_F64SIN>();
+  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Tmp = sin(Src);
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64COS) {
+  auto Op = IROp->C<IR::IROp_F64COS>();
+  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Tmp = cos(Src);
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64TAN) {
+  auto Op = IROp->C<IR::IROp_F64TAN>();
+  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Tmp = tan(Src);
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64F2XM1) {
+  auto Op = IROp->C<IR::IROp_F64F2XM1>();
+  double Src = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Tmp = exp2(Src) - 1.0;
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64ATAN) {
+  auto Op = IROp->C<IR::IROp_F64ATAN>();
+  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
+  double Tmp = atan2(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64FPREM) {
+  auto Op = IROp->C<IR::IROp_F64FPREM>();
+  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
+  double Tmp = remainder(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64FPREM1) {
+  auto Op = IROp->C<IR::IROp_F64FPREM1>();
+  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
+  double Tmp = remainder(Src1, Src2);
+
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64FYL2X) {
+  auto Op = IROp->C<IR::IROp_F64FYL2X>();
+  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
+  double Tmp = Src2 * log2(Src1);
+
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+DEF_OP(F64SCALE) {
+  auto Op = IROp->C<IR::IROp_F64SCALE>();
+  double Src1 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[0]);
+  double Src2 = *GetSrc<double*>(Data->SSAData, Op->Header.Args[1]);
+  double trunc = round(Src2);
+  double Tmp = Src1 * exp2(trunc);
+
+  memcpy(GDP, &Tmp, sizeof(double));
+}
+
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU
diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
index 2ae4f80f4..9693cd95f 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
@@ -311,6 +311,17 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(F80BCDLOAD,             F80BCDLOAD);
   REGISTER_OP(F80BCDSTORE,            F80BCDSTORE);
 
+  // F64 ops
+  REGISTER_OP(F64SIN,                 F64SIN);
+  REGISTER_OP(F64COS,                 F64COS);
+  REGISTER_OP(F64TAN,                 F64TAN);
+  REGISTER_OP(F64F2XM1,               F64F2XM1);
+  REGISTER_OP(F64ATAN,                F64ATAN);
+  REGISTER_OP(F64FPREM,               F64FPREM);
+  REGISTER_OP(F64FPREM1,              F64FPREM1);
+  REGISTER_OP(F64FYL2X,               F64FYL2X);
+  REGISTER_OP(F64SCALE,               F64SCALE);
+
   return Handlers;
 }();
 
diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
index 0b3d9ae4a..bbce6b065 100644
--- a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
+++ b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
@@ -330,6 +330,17 @@ namespace FEXCore::CPU {
   DEF_OP(F80CMP);
   DEF_OP(F80BCDLOAD);
   DEF_OP(F80BCDSTORE);
+
+  //< F64 ops
+  DEF_OP(F64SIN);
+  DEF_OP(F64COS);
+  DEF_OP(F64TAN);
+  DEF_OP(F64F2XM1);
+  DEF_OP(F64ATAN);
+  DEF_OP(F64FPREM);
+  DEF_OP(F64FPREM1);
+  DEF_OP(F64FYL2X);
+  DEF_OP(F64SCALE);
 #undef DEF_OP
   template<typename unsigned_type, typename signed_type, typename float_type>
   [[nodiscard]] static bool IsConditionTrue(uint8_t Cond, uint64_t Src1, uint64_t Src2) {