diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index edefb37c0..5b8e2821c 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -999,7 +999,7 @@ private: void VectorUnaryDuplicateOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize); OrderedNode* VectorRoundImpl(OpcodeArgs, size_t ElementSize, - OrderedNode *Src, uint64_t Mode); + OrderedNode *Src, uint64_t Mode, bool IsScalar); OrderedNode* Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, size_t DstElementSize, size_t SrcElementSize, const X86Tables::DecodedOperand& Src1Op, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7d8052ef0..8a8abd3ee 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -3724,7 +3724,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, - OrderedNode *Src, uint64_t Mode) { + OrderedNode *Src, uint64_t Mode, + bool IsScalar) { const auto Size = GetDstSize(Op); const uint64_t RoundControlSource = (Mode >> 2) & 1; uint64_t RoundControl = Mode & 0b11; @@ -3741,7 +3742,9 @@ OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, FEXCore::IR::Round_Host, }; - return _Vector_FToI(Size, ElementSize, Src, SourceModes[(RoundControlSource << 2) | RoundControl]); + const auto SourceMode = SourceModes[(RoundControlSource << 2) | RoundControl]; + const auto OpSize = IsScalar ? ElementSize : Size; + return _Vector_FToI(OpSize, ElementSize, Src, SourceMode); } template @@ -3755,7 +3758,7 @@ void OpDispatchBuilder::VectorRound(OpcodeArgs) { LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); const uint64_t Mode = Op->Src[1].Data.Literal.Value; - Src = VectorRoundImpl(Op, ElementSize, Src, Mode); + Src = VectorRoundImpl(Op, ElementSize, Src, Mode, Scalar); if constexpr (Scalar) { // Insert the lower bits @@ -3797,7 +3800,7 @@ void OpDispatchBuilder::AVXVectorRound(OpcodeArgs) { const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE; OrderedNode *Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[SrcIdx], SrcSize, Op->Flags, -1); - OrderedNode *Result = VectorRoundImpl(Op, ElementSize, Src, GetMode()); + OrderedNode *Result = VectorRoundImpl(Op, ElementSize, Src, GetMode(), Scalar); if constexpr (Scalar) { // Insert the lower bits diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index a7c921485..b474fa8a4 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -57,7 +57,7 @@ "0x66 0x0f 0x3a 0x08" ], "ExpectedArm64ASM": [ - "frinti v16.4s, v17.4s" + "frintn v16.4s, v17.4s" ] }, "roundps xmm0, xmm1, 00000001b": { @@ -112,7 +112,7 @@ "0x66 0x0f 0x3a 0x09" ], "ExpectedArm64ASM": [ - "frinti v16.2d, v17.2d" + "frintn v16.2d, v17.2d" ] }, "roundpd xmm0, xmm1, 00000001b": { @@ -164,12 +164,10 @@ "Optimal": "No", "Comment": [ "Nearest rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frinti v4.4s, v17.4s", + "frintn s4, s17", "mov v16.s[0], v4.s[0]" ] }, @@ -178,12 +176,10 @@ "Optimal": "No", "Comment": [ "-inf rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintm v4.4s, v17.4s", + "frintm s4, s17", "mov v16.s[0], v4.s[0]" ] }, @@ -192,12 +188,10 @@ "Optimal": "No", "Comment": [ "+inf rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintp v4.4s, v17.4s", + "frintp s4, s17", "mov v16.s[0], v4.s[0]" ] }, @@ -206,12 +200,10 @@ "Optimal": "No", "Comment": [ "truncate rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frintz v4.4s, v17.4s", + "frintz s4, s17", "mov v16.s[0], v4.s[0]" ] }, @@ -220,12 +212,10 @@ "Optimal": "No", "Comment": [ "host rounding mode rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" ], "ExpectedArm64ASM": [ - "frinti v4.4s, v17.4s", + "frinti s4, s17", "mov v16.s[0], v4.s[0]" ] }, @@ -234,12 +224,10 @@ "Optimal": "No", "Comment": [ "Nearest rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frinti v4.2d, v17.2d", + "frintn d4, d17", "mov v16.d[0], v4.d[0]" ] }, @@ -248,12 +236,10 @@ "Optimal": "No", "Comment": [ "-inf rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintm v4.2d, v17.2d", + "frintm d4, d17", "mov v16.d[0], v4.d[0]" ] }, @@ -262,12 +248,10 @@ "Optimal": "No", "Comment": [ "+inf rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintp v4.2d, v17.2d", + "frintp d4, d17", "mov v16.d[0], v4.d[0]" ] }, @@ -276,12 +260,10 @@ "Optimal": "No", "Comment": [ "truncate rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frintz v4.2d, v17.2d", + "frintz d4, d17", "mov v16.d[0], v4.d[0]" ] }, @@ -290,12 +272,10 @@ "Optimal": "No", "Comment": [ "host rounding mode rounding", - "FPConvert instruction using vector conversion instead of scalar.", - "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" ], "ExpectedArm64ASM": [ - "frinti v4.2d, v17.2d", + "frinti d4, d17", "mov v16.d[0], v4.d[0]" ] }, diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 00d68fc76..54a0ecf60 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -1633,7 +1633,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.4s, v4.4s", + "frintn v4.4s, v4.4s", "mov v4.16b, v4.16b", "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" @@ -1773,7 +1773,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.2d, v4.2d", + "frintn v4.2d, v4.2d", "mov v4.16b, v4.16b", "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" @@ -1913,7 +1913,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.4s, v4.4s", + "frintn s4, s4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.s[0], v4.s[0]", @@ -1932,7 +1932,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintm v4.4s, v4.4s", + "frintm s4, s4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.s[0], v4.s[0]", @@ -1951,7 +1951,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintp v4.4s, v4.4s", + "frintp s4, s4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.s[0], v4.s[0]", @@ -1970,7 +1970,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintz v4.4s, v4.4s", + "frintz s4, s4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.s[0], v4.s[0]", @@ -1989,7 +1989,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.4s, v4.4s", + "frinti s4, s4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.s[0], v4.s[0]", @@ -2008,7 +2008,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.2d, v4.2d", + "frintn d4, d4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.d[0], v4.d[0]", @@ -2027,7 +2027,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintm v4.2d, v4.2d", + "frintm d4, d4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.d[0], v4.d[0]", @@ -2046,7 +2046,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintp v4.2d, v4.2d", + "frintp d4, d4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.d[0], v4.d[0]", @@ -2065,7 +2065,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frintz v4.2d, v4.2d", + "frintz d4, d4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.d[0], v4.d[0]", @@ -2084,7 +2084,7 @@ ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z17.d", - "frinti v4.2d, v4.2d", + "frinti d4, d4", "mov z5.d, p7/m, z16.d", "mov v0.16b, v5.16b", "mov v0.d[0], v4.d[0]",