diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index cf63400ce..7dd02b7db 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -11725,7 +11725,7 @@
       ]
     },
     "fld and fnstsw": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 163,
       "x86Insts": [
         "fld dword [rax]",
         "fld dword [rax + 4]",
@@ -11733,7 +11733,171 @@
         "fld dword [rax + 12]",
         "fnstsw [rbx]"
       ],
-      "ExpectedArm64ASM": []
+      "ExpectedArm64ASM": [
+        "ldr s2, [x4]",
+        "mrs x0, nzcv",
+        "str w0, [x28, #1000]",
+        "stp x4, x5, [x28, #280]",
+        "stp x6, x7, [x28, #296]",
+        "str x8, [x28, #312]",
+        "stp x16, x17, [x28, #376]",
+        "sub sp, sp, #0x70 (112)",
+        "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
+        "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
+        "str x30, [x0], #16",
+        "fmov s0, s2",
+        "ldrh w0, [x28, #1296]",
+        "ldr x1, [x28, #1424]",
+        "blr x1",
+        "ldr w4, [x28, #1000]",
+        "msr nzcv, x4",
+        "ldp x4, x5, [x28, #280]",
+        "ldp x6, x7, [x28, #296]",
+        "ldr x8, [x28, #312]",
+        "ldp x16, x17, [x28, #376]",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
+        "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
+        "ldr x30, [sp], #16",
+        "eor v2.16b, v2.16b, v2.16b",
+        "mov v2.d[0], x0",
+        "mov v2.h[4], w1",
+        "ldr s3, [x4, #4]",
+        "mrs x0, nzcv",
+        "str w0, [x28, #1000]",
+        "stp x4, x5, [x28, #280]",
+        "stp x6, x7, [x28, #296]",
+        "str x8, [x28, #312]",
+        "stp x16, x17, [x28, #376]",
+        "sub sp, sp, #0x70 (112)",
+        "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
+        "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
+        "str x30, [x0], #16",
+        "fmov s0, s3",
+        "ldrh w0, [x28, #1296]",
+        "ldr x1, [x28, #1424]",
+        "blr x1",
+        "ldr w4, [x28, #1000]",
+        "msr nzcv, x4",
+        "ldp x4, x5, [x28, #280]",
+        "ldp x6, x7, [x28, #296]",
+        "ldr x8, [x28, #312]",
+        "ldp x16, x17, [x28, #376]",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
+        "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
+        "ldr x30, [sp], #16",
+        "eor v3.16b, v3.16b, v3.16b",
+        "mov v3.d[0], x0",
+        "mov v3.h[4], w1",
+        "mov w20, #0x8",
+        "ldr s4, [x4, #8]",
+        "mrs x0, nzcv",
+        "str w0, [x28, #1000]",
+        "stp x4, x5, [x28, #280]",
+        "stp x6, x7, [x28, #296]",
+        "str x8, [x28, #312]",
+        "stp x16, x17, [x28, #376]",
+        "sub sp, sp, #0x70 (112)",
+        "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
+        "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
+        "str x30, [x0], #16",
+        "fmov s0, s4",
+        "ldrh w0, [x28, #1296]",
+        "ldr x1, [x28, #1424]",
+        "blr x1",
+        "ldr w4, [x28, #1000]",
+        "msr nzcv, x4",
+        "ldp x4, x5, [x28, #280]",
+        "ldp x6, x7, [x28, #296]",
+        "ldr x8, [x28, #312]",
+        "ldp x16, x17, [x28, #376]",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
+        "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
+        "ldr x30, [sp], #16",
+        "eor v4.16b, v4.16b, v4.16b",
+        "mov v4.d[0], x0",
+        "mov v4.h[4], w1",
+        "ldr s5, [x4, #12]",
+        "mrs x0, nzcv",
+        "str w0, [x28, #1000]",
+        "stp x4, x5, [x28, #280]",
+        "stp x6, x7, [x28, #296]",
+        "str x8, [x28, #312]",
+        "stp x16, x17, [x28, #376]",
+        "sub sp, sp, #0x70 (112)",
+        "mov x0, sp",
+        "st1 {v2.2d, v3.2d}, [x0], #32",
+        "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
+        "str x30, [x0], #16",
+        "fmov s0, s5",
+        "ldrh w0, [x28, #1296]",
+        "ldr x1, [x28, #1424]",
+        "blr x1",
+        "ldr w4, [x28, #1000]",
+        "msr nzcv, x4",
+        "ldp x4, x5, [x28, #280]",
+        "ldp x6, x7, [x28, #296]",
+        "ldr x8, [x28, #312]",
+        "ldp x16, x17, [x28, #376]",
+        "ld1 {v2.2d, v3.2d}, [sp], #32",
+        "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
+        "ldr x30, [sp], #16",
+        "eor v5.16b, v5.16b, v5.16b",
+        "mov v5.d[0], x0",
+        "mov v5.h[4], w1",
+        "ldrb w21, [x28, #1019]",
+        "sub w21, w21, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "strb w21, [x28, #1019]",
+        "add x0, x28, x21, lsl #4",
+        "str q5, [x0, #1040]",
+        "add w22, w21, #0x1 (1)",
+        "and w22, w22, #0x7",
+        "add x0, x28, x22, lsl #4",
+        "str q4, [x0, #1040]",
+        "add w23, w21, #0x2 (2)",
+        "and w23, w23, #0x7",
+        "add x0, x28, x23, lsl #4",
+        "str q3, [x0, #1040]",
+        "add w24, w21, #0x3 (3)",
+        "and w24, w24, #0x7",
+        "add x0, x28, x24, lsl #4",
+        "str q2, [x0, #1040]",
+        "sub w25, w20, w21",
+        "ldrb w30, [x28, #1298]",
+        "mov w18, #0xf0f",
+        "lsr w25, w18, w25",
+        "orr w25, w30, w25",
+        "strb w25, [x28, #1298]",
+        "ldrb w25, [x28, #1016]",
+        "ldrb w30, [x28, #1017]",
+        "ldrb w18, [x28, #1018]",
+        "ldrb w20, [x28, #1022]",
+        "lsl x25, x25, #8",
+        "orr x25, x25, x30, lsl #9",
+        "orr x25, x25, x18, lsl #10",
+        "orr x20, x25, x20, lsl #14",
+        "ldrb w25, [x28, #1019]",
+        "bfi x20, x25, #11, #3",
+        "strh w20, [x7]",
+        "add x0, x28, x21, lsl #4",
+        "str q5, [x0, #1040]",
+        "add x0, x28, x22, lsl #4",
+        "str q4, [x0, #1040]",
+        "add x0, x28, x23, lsl #4",
+        "str q3, [x0, #1040]",
+        "add x0, x28, x24, lsl #4",
+        "str q2, [x0, #1040]",
+        "mov w20, #0x8",
+        "sub w20, w20, w21",
+        "ldrb w21, [x28, #1298]",
+        "mov w22, #0xf0f",
+        "lsr w20, w22, w20",
+        "orr w20, w21, w20",
+        "strb w20, [x28, #1298]"
+      ]
     },
     "ffree st0": {
       "ExpectedInstructionCount": 6,