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https://github.com/FEX-Emu/FEX.git
synced 2026-10-26 11:00:48 +01:00
Various fixes that unit tests have found
- Need to distinguish between unsigned and signed saturating ops - Fixes vector splat - Fixes VUMULL/VSMULL num element calculation - Fixes undefined behaviour in a couple of vector shift ops - Implements VSSHR - Fixes VExtr calculating offset correctly - Fixes VInsGPR calculating offset correctly - Fixes PSRA (not immediate) x86 ops - Fixes scalar vector unary ops to correctly insert lower bits - Fixes conversion instructions correctly inserting lower bits - Fixes PINSRW using the wrong element size
This commit is contained in:
Ryan Houdek authored and Stefanos Kornilios Mitsis Poiitidis committed
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9b21caa647
commit
9c363fb317
5 files changed
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@@ -2365,22 +2365,7 @@ template<FEXCore::IR::IROps IROp, size_t ElementSize>
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void OpDispatchBuilder::VectorScalarALUOp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Src{};
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if (Op->Src[0].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_GPR) {
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Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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}
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else {
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// Load a elementsize from memory and move it to a vector register
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Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], ElementSize, Op->Flags, -1);
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switch (ElementSize) {
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case 4:
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Src = _SplatVector4(Src);
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break;
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case 8:
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Src = _SplatVector2(Src);
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break;
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}
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}
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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// If OpSize == ElementSize then it only does the lower scalar op
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auto ALUOp = _VAdd(ElementSize, ElementSize, Dest, Src);
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@@ -2406,10 +2391,14 @@ void OpDispatchBuilder::VectorUnaryOp(OpcodeArgs) {
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// Overwrite our IR's op type
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ALUOp.first->Header.Op = IROp;
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// Insert the lower bits
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auto Result = _VInsElement(Size, ElementSize, 0, 0, Dest, ALUOp);
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StoreResult(FPRClass, Op, Result, -1);
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if (Scalar) {
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// Insert the lower bits
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auto Result = _VInsElement(GetSrcSize(Op), ElementSize, 0, 0, Dest, ALUOp);
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StoreResult(FPRClass, Op, Result, -1);
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}
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else {
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StoreResult(FPRClass, Op, ALUOp, -1);
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}
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}
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void OpDispatchBuilder::MOVQOp(OpcodeArgs) {
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@@ -2549,10 +2538,10 @@ void OpDispatchBuilder::ANDNOp(OpcodeArgs) {
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template<size_t ElementSize>
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void OpDispatchBuilder::PINSROp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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auto Size = GetDstSize(Op);
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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uint64_t Index = Op->Src[1].TypeLiteral.Literal;
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@@ -3806,6 +3795,25 @@ void OpDispatchBuilder::PSLL(OpcodeArgs) {
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StoreResult(FPRClass, Op, Result, -1);
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}
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template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
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void OpDispatchBuilder::PSRAOp(OpcodeArgs) {
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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auto Size = GetDstSize(Op);
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OrderedNode *Result{};
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if (Scalar) {
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Result = _VSShrS(Size, ElementSize, Dest, Src);
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}
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else {
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Result = _VSShr(Size, ElementSize, Dest, Src);
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}
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StoreResult(FPRClass, Op, Result, -1);
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}
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void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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uint64_t Shift = Op->Src[1].TypeLiteral.Literal;
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@@ -3874,7 +3882,7 @@ void OpDispatchBuilder::CVT(OpcodeArgs) {
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else
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Src = _UCVTF(Src, DstElementSize);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, 16, Op->Flags, -1);
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Src = _VInsElement(16, DstElementSize, 0, 0, Dest, Src);
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@@ -3972,7 +3980,7 @@ template<size_t ElementSize, bool Scalar>
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void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
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uint8_t CompType = Op->Src[1].TypeLiteral.Literal;
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OrderedNode *Result{};
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@@ -4002,7 +4010,7 @@ void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
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if (Scalar) {
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// Insert the lower bits
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Result = _VInsElement(Size, ElementSize, 0, 0, Dest, Result);
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Result = _VInsElement(GetDstSize(Op), ElementSize, 0, 0, Dest, Result);
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}
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StoreResult(FPRClass, Op, Result, -1);
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@@ -4658,7 +4666,7 @@ void InstallOpcodeHandlers() {
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{0x5F, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMAX, 8>},
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{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, true>},
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{0xC2, 1, &OpDispatchBuilder::VFCMPOp<8, true>},
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{0xF0, 1, &OpDispatchBuilder::UnimplementedOp},
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{0xF0, 1, &OpDispatchBuilder::MOVVectorOp},
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};
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const std::vector<std::tuple<uint8_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr>> OpSizeModOpTable = {
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@@ -4707,7 +4715,7 @@ void InstallOpcodeHandlers() {
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{0x7E, 1, &OpDispatchBuilder::MOVDOp},
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{0x7F, 1, &OpDispatchBuilder::MOVUPSOp},
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{0xC2, 1, &OpDispatchBuilder::VFCMPOp<8, false>},
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{0xC4, 1, &OpDispatchBuilder::PINSROp<4>},
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{0xC4, 1, &OpDispatchBuilder::PINSROp<2>},
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{0xC6, 1, &OpDispatchBuilder::SHUFOp<8>},
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{0xD4, 1, &OpDispatchBuilder::PADDQOp<8>},
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@@ -4719,13 +4727,13 @@ void InstallOpcodeHandlers() {
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{0xDB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
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{0xDE, 1, &OpDispatchBuilder::PMAXUOp<1>},
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{0xDF, 1, &OpDispatchBuilder::ANDNOp},
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{0xE1, 1, &OpDispatchBuilder::PSRAIOp<2>},
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{0xE2, 1, &OpDispatchBuilder::PSRAIOp<4>},
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{0xE1, 1, &OpDispatchBuilder::PSRAOp<2, true, 0>},
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{0xE2, 1, &OpDispatchBuilder::PSRAOp<4, true, 0>},
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{0xE7, 1, &OpDispatchBuilder::MOVVectorOp},
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{0xEA, 1, &OpDispatchBuilder::PMINSWOp},
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{0xEB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
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{0xEC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VQADD, 1>},
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{0xED, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VQADD, 2>},
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{0xEC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSQADD, 1>},
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{0xED, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSQADD, 2>},
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{0xEE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSMAX, 2>},
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{0xEF, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
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