From 50b5971ee5b1a189d7a7ffeed09b280d8c525b93 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 19 Feb 2025 12:38:36 -0800 Subject: [PATCH 1/2] OpcodeDispatcher: Implements a few more pshufd masks Saw these while scanning around. Funnily it makes it look like libnss is worse off because there are multiple instructions using the same table lookup to swizzle. So one instruction turns in to two. We don't have a way to choose one path or the other, so it's usually better to go the route that the instruction in a vacuum is improved, so on average it is also improved. --- .../Interface/Core/OpcodeDispatcher/Vector.cpp | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 148621efa..bff1ab9e5 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -967,13 +967,17 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle) // Special case element duplicate and broadcast to low or high 64-bits. return _VDupElement(OpSize::i128Bit, OpSize::i32Bit, Src, Shuffle & 0b11); } - case 0b00'00'10'10: { // Weird reverse low elements and broadcast to each half of the register Ref Tmp = _VUnZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src); Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Tmp); return _VZip(OpSize::i128Bit, OpSize::i32Bit, Tmp, Tmp); } + case 0b00'00'11'10: { + // First element duplicated and shifted in to the top. + auto Dup = _VDupElement(OpSize::i128Bit, OpSize::i32Bit, Src, 0); + return _VExtr(OpSize::i128Bit, OpSize::i32Bit, Dup, Src, 2); + } case 0b00'01'00'01: { ///< Weird reversed low elements and broadcast Ref Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src); @@ -984,6 +988,11 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle) Ref Tmp = _VZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src); return _VExtr(OpSize::i128Bit, OpSize::i8Bit, Tmp, Tmp, 4); } + case 0b00'01'10'11: { + // Inverse elements + Ref Tmp = _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src); + return _VExtr(OpSize::i128Bit, OpSize::i32Bit, Tmp, Tmp, 2); + } case 0b00'10'00'10: { ///< Weird reversed even elements and broadcast Ref Tmp = _VUnZip(OpSize::i128Bit, OpSize::i32Bit, Src, Src); @@ -1102,6 +1111,10 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle) Ref Tmp = _VZip2(OpSize::i128Bit, OpSize::i32Bit, Src, Src); return _VExtr(OpSize::i128Bit, OpSize::i8Bit, Tmp, Tmp, 8); } + case 0b10'11'00'01: { + // Reverse each 64-bit lane. + return _VRev64(OpSize::i128Bit, OpSize::i32Bit, Src); + } case 0b10'11'10'11: { ///< Weird top two elements reverse and broadcast Ref Tmp = _VZip2(OpSize::i128Bit, OpSize::i64Bit, Src, Src); From ef28a6c19ab923a49b097a2a52caf5a3340698fb Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 19 Feb 2025 12:41:00 -0800 Subject: [PATCH 2/2] InstcountCI: Update --- .../InstructionCountCI/FEXOpt/libnss.json | 494 +++++++++--------- .../InstructionCountCI/Secondary_OpSize.json | 35 ++ 2 files changed, 288 insertions(+), 241 deletions(-) diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index a0f171359..9e0883bec 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -17,7 +17,7 @@ "Instructions": { "libnss3 sha": { "x86InstructionCount": 168, - "ExpectedInstructionCount": 1994, + "ExpectedInstructionCount": 2006, "Comment": [ "This block of code comes from libnss3 which causes panic spilling in FEX's RA.", "This code is hit in steamwebhelper calling in to this function.", @@ -198,12 +198,9 @@ "ldr q19, [x11, #272]", "ldr q24, [x11]", "ldr q23, [x11, #16]", - "ldr x0, [x28, #2064]", - "ldr q2, [x0, #2832]", - "tbl v16.16b, {v18.16b}, v2.16b", - "ldr x0, [x28, #2064]", - "ldr q3, [x0, #432]", - "tbl v18.16b, {v19.16b}, v3.16b", + "rev64 v16.4s, v18.4s", + "rev64 v2.4s, v19.4s", + "ext v18.16b, v2.16b, v2.16b, #8", "ldr q22, [x11, #32]", "ldr q21, [x11, #48]", "mov v19.16b, v16.16b", @@ -214,18 +211,18 @@ "ldr q16, [x29, x20, sxtx]", "mov v20.16b, v18.16b", "mov v17.16b, v19.16b", - "movi v4.16b, #0x8f", - "and v4.16b, v16.16b, v4.16b", - "tbl v21.16b, {v21.16b}, v4.16b", - "movi v4.16b, #0x8f", - "and v4.16b, v16.16b, v4.16b", - "tbl v22.16b, {v22.16b}, v4.16b", - "movi v4.16b, #0x8f", - "and v4.16b, v16.16b, v4.16b", - "tbl v23.16b, {v23.16b}, v4.16b", - "movi v4.16b, #0x8f", - "and v4.16b, v16.16b, v4.16b", - "tbl v24.16b, {v24.16b}, v4.16b", + "movi v2.16b, #0x8f", + "and v2.16b, v16.16b, v2.16b", + "tbl v21.16b, {v21.16b}, v2.16b", + "movi v2.16b, #0x8f", + "and v2.16b, v16.16b, v2.16b", + "tbl v22.16b, {v22.16b}, v2.16b", + "movi v2.16b, #0x8f", + "and v2.16b, v16.16b, v2.16b", + "tbl v23.16b, {v23.16b}, v2.16b", + "movi v2.16b, #0x8f", + "and v2.16b, v16.16b, v2.16b", + "tbl v24.16b, {v24.16b}, v2.16b", "ldr q16, [x29, x20, sxtx]", "add v16.4s, v16.4s, v24.4s", "unimplemented (Unimplemented)", @@ -279,15 +276,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v4.16b, v20.16b", - "mov v4.s[3], w22", - "mov v4.s[2], w30", - "mov v4.s[1], w21", - "mov v20.16b, v4.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "ldr x0, [x28, #2064]", - "ldr q4, [x0, #224]", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -338,19 +334,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v24.16b, v24.16b, #12", - "dup v6.4s, v24.s[3]", - "zip2 v6.2d, v6.2d, v21.2d", + "ext v2.16b, v24.16b, v24.16b, #12", + "dup v3.4s, v24.s[3]", + "zip2 v3.2d, v3.2d, v21.2d", "movi v24.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v23.4s", @@ -405,13 +401,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -462,19 +459,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v23.16b, v23.16b, #12", - "dup v6.4s, v23.s[3]", - "zip2 v6.2d, v6.2d, v24.2d", + "ext v2.16b, v23.16b, v23.16b, #12", + "dup v3.4s, v23.s[3]", + "zip2 v3.2d, v3.2d, v24.2d", "movi v23.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v22.4s", @@ -529,13 +526,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -586,19 +584,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v22.16b, v22.16b, #12", - "dup v6.4s, v22.s[3]", - "zip2 v6.2d, v6.2d, v23.2d", + "ext v2.16b, v22.16b, v22.16b, #12", + "dup v3.4s, v22.s[3]", + "zip2 v3.2d, v3.2d, v23.2d", "movi v22.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v21.4s", @@ -653,13 +651,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -710,19 +709,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", "ext v16.16b, v23.16b, v16.16b, #4", "add v21.4s, v21.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v21.16b, v21.16b, #12", - "dup v6.4s, v21.s[3]", - "zip2 v6.2d, v6.2d, v22.2d", + "ext v2.16b, v21.16b, v21.16b, #12", + "dup v3.4s, v21.s[3]", + "zip2 v3.2d, v3.2d, v22.2d", "movi v21.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v24.4s", @@ -777,13 +776,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -834,19 +834,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v24.16b, v24.16b, #12", - "dup v6.4s, v24.s[3]", - "zip2 v6.2d, v6.2d, v21.2d", + "ext v2.16b, v24.16b, v24.16b, #12", + "dup v3.4s, v24.s[3]", + "zip2 v3.2d, v3.2d, v21.2d", "movi v24.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v23.4s", @@ -901,13 +901,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -958,19 +959,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v23.16b, v23.16b, #12", - "dup v6.4s, v23.s[3]", - "zip2 v6.2d, v6.2d, v24.2d", + "ext v2.16b, v23.16b, v23.16b, #12", + "dup v3.4s, v23.s[3]", + "zip2 v3.2d, v3.2d, v24.2d", "movi v23.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v22.4s", @@ -1025,13 +1026,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1082,19 +1084,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v22.16b, v22.16b, #12", - "dup v6.4s, v22.s[3]", - "zip2 v6.2d, v6.2d, v23.2d", + "ext v2.16b, v22.16b, v22.16b, #12", + "dup v3.4s, v22.s[3]", + "zip2 v3.2d, v3.2d, v23.2d", "movi v22.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v21.4s", @@ -1149,13 +1151,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1206,19 +1209,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", "ext v16.16b, v23.16b, v16.16b, #4", "add v21.4s, v21.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v21.16b, v21.16b, #12", - "dup v6.4s, v21.s[3]", - "zip2 v6.2d, v6.2d, v22.2d", + "ext v2.16b, v21.16b, v21.16b, #12", + "dup v3.4s, v21.s[3]", + "zip2 v3.2d, v3.2d, v22.2d", "movi v21.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v24.4s", @@ -1273,13 +1276,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1330,19 +1334,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v21.16b", "ext v16.16b, v22.16b, v16.16b, #4", "add v24.4s, v24.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v24.16b, v24.16b, #12", - "dup v6.4s, v24.s[3]", - "zip2 v6.2d, v6.2d, v21.2d", + "ext v2.16b, v24.16b, v24.16b, #12", + "dup v3.4s, v24.s[3]", + "zip2 v3.2d, v3.2d, v21.2d", "movi v24.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v23.4s", @@ -1397,13 +1401,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1454,19 +1459,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v24.16b", "ext v16.16b, v21.16b, v16.16b, #4", "add v23.4s, v23.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v23.16b, v23.16b, #12", - "dup v6.4s, v23.s[3]", - "zip2 v6.2d, v6.2d, v24.2d", + "ext v2.16b, v23.16b, v23.16b, #12", + "dup v3.4s, v23.s[3]", + "zip2 v3.2d, v3.2d, v24.2d", "movi v23.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v22.4s", @@ -1521,13 +1526,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1578,19 +1584,19 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v23.16b", "ext v16.16b, v24.16b, v16.16b, #4", "add v22.4s, v22.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v22.16b, v22.16b, #12", - "dup v6.4s, v22.s[3]", - "zip2 v6.2d, v6.2d, v23.2d", + "ext v2.16b, v22.16b, v22.16b, #12", + "dup v3.4s, v22.s[3]", + "zip2 v3.2d, v3.2d, v23.2d", "movi v22.2d, #0x0", "unimplemented (Unimplemented)", "add v16.4s, v16.4s, v21.4s", @@ -1645,13 +1651,14 @@ "add w22, w22, w24", "mov w24, v20.s[3]", "add w21, w21, w24", - "mov v5.16b, v20.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v20.16b, v2.16b", "mov v20.s[0], w23", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w21, v20.s[1]", "mov w22, v20.s[0]", "mov w23, v17.s[1]", @@ -1702,27 +1709,27 @@ "add w22, w22, w24", "mov w24, v17.s[3]", "add w21, w21, w24", - "mov v5.16b, v17.16b", - "mov v5.s[3], w22", - "mov v5.s[2], w30", - "mov v5.s[1], w21", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w22", + "mov v2.s[2], w30", + "mov v2.s[1], w21", + "mov v17.16b, v2.16b", "mov v17.s[0], w23", "mov v16.16b, v22.16b", "ext v16.16b, v23.16b, v16.16b, #4", - "ldr q5, [x29, x20, sxtx]", - "add v23.4s, v23.4s, v5.4s", + "ldr q2, [x29, x20, sxtx]", + "add v23.4s, v23.4s, v2.4s", "add v21.4s, v21.4s, v16.4s", "ldr q16, [x29, x20, sxtx]", - "ext v5.16b, v21.16b, v21.16b, #12", - "dup v6.4s, v21.s[3]", - "zip2 v6.2d, v6.2d, v22.2d", + "ext v2.16b, v21.16b, v21.16b, #12", + "dup v3.4s, v21.s[3]", + "zip2 v3.2d, v3.2d, v22.2d", "movi v21.2d, #0x0", "unimplemented (Unimplemented)", - "ldr q5, [x29, x20, sxtx]", - "add v22.4s, v22.4s, v5.4s", - "ldr q5, [x29, x20, sxtx]", - "add v21.4s, v21.4s, v5.4s", + "ldr q2, [x29, x20, sxtx]", + "add v22.4s, v22.4s, v2.4s", + "ldr q2, [x29, x20, sxtx]", + "add v21.4s, v21.4s, v2.4s", "add v16.4s, v16.4s, v24.4s", "mov w20, v17.s[1]", "mov w21, v17.s[0]", @@ -1774,13 +1781,14 @@ "add w21, w21, w23", "mov w23, v20.s[3]", "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v20.16b, v2.16b", "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", + "dup v2.4s, v16.s[0]", + "ext v16.16b, v16.16b, v2.16b, #8", "mov w20, v20.s[1]", "mov w21, v20.s[0]", "mov w22, v17.s[1]", @@ -1831,11 +1839,11 @@ "add w21, w21, w23", "mov w23, v17.s[3]", "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v17.16b, v2.16b", "mov v17.s[0], w22", "mov v16.16b, v23.16b", "mov w20, v17.s[1]", @@ -1888,13 +1896,14 @@ "add w21, w21, w23", "mov w23, v20.s[3]", "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v20.16b, v2.16b", "mov v20.s[0], w22", - "tbl v16.16b, {v23.16b}, v4.16b", + "dup v2.4s, v23.s[0]", + "ext v16.16b, v23.16b, v2.16b, #8", "mov w20, v20.s[1]", "mov w21, v20.s[0]", "mov w22, v17.s[1]", @@ -1945,11 +1954,11 @@ "add w21, w21, w23", "mov w23, v17.s[3]", "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v17.16b, v2.16b", "mov v17.s[0], w22", "mov v16.16b, v22.16b", "mov w20, v17.s[1]", @@ -2002,13 +2011,14 @@ "add w21, w21, w23", "mov w23, v20.s[3]", "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v20.16b, v2.16b", "mov v20.s[0], w22", - "tbl v16.16b, {v22.16b}, v4.16b", + "dup v2.4s, v22.s[0]", + "ext v16.16b, v22.16b, v2.16b, #8", "mov w20, v20.s[1]", "mov w21, v20.s[0]", "mov w22, v17.s[1]", @@ -2059,11 +2069,11 @@ "add w21, w21, w23", "mov w23, v17.s[3]", "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v17.16b, v2.16b", "mov v17.s[0], w22", "mov v16.16b, v21.16b", "mov w20, v17.s[1]", @@ -2116,13 +2126,14 @@ "add w21, w21, w23", "mov w23, v20.s[3]", "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", + "mov v2.16b, v20.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v20.16b, v2.16b", "mov v20.s[0], w22", - "tbl v16.16b, {v21.16b}, v4.16b", + "dup v2.4s, v21.s[0]", + "ext v16.16b, v21.16b, v2.16b, #8", "mov w20, v20.s[1]", "mov w21, v20.s[0]", "mov w22, v17.s[1]", @@ -2173,16 +2184,17 @@ "add w21, w21, w23", "mov w23, v17.s[3]", "add w20, w20, w23", - "mov v4.16b, v17.16b", - "mov v4.s[3], w21", - "mov v4.s[2], w25", - "mov v4.s[1], w20", - "mov v17.16b, v4.16b", + "mov v2.16b, v17.16b", + "mov v2.s[3], w21", + "mov v2.s[2], w25", + "mov v2.s[1], w20", + "mov v17.16b, v2.16b", "mov v17.s[0], w22", "add v20.4s, v20.4s, v18.4s", "add v17.4s, v17.4s, v19.4s", - "tbl v20.16b, {v20.16b}, v2.16b", - "tbl v17.16b, {v17.16b}, v3.16b", + "rev64 v20.4s, v20.4s", + "rev64 v2.4s, v17.4s", + "ext v17.16b, v2.16b, v2.16b, #8", "mov v16.16b, v17.16b", "mov v16.d[1], v20.d[1]", "ext v20.16b, v17.16b, v20.16b, #8", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 53a47e2e6..2077b3b8b 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -577,6 +577,18 @@ "dup v16.4s, v2.s[3]" ] }, + "pshufd xmm0, [rax], 00_00_11_10b": { + "ExpectedInstructionCount": 3, + "Comment": [ + "Inverse elements", + "0x66 0x0f 0x70" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x4]", + "dup v3.4s, v2.s[0]", + "ext v16.16b, v2.16b, v3.16b, #8" + ] + }, "pshufd xmm0, [rax], 00_01_00_01b": { "ExpectedInstructionCount": 3, "Comment": [ @@ -589,6 +601,18 @@ "zip1 v16.2d, v2.2d, v2.2d" ] }, + "pshufd xmm0, [rax], 00_01_10_11b": { + "ExpectedInstructionCount": 3, + "Comment": [ + "Inverse elements", + "0x66 0x0f 0x70" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x4]", + "rev64 v2.4s, v2.4s", + "ext v16.16b, v2.16b, v2.16b, #8" + ] + }, "pshufd xmm0, [rax], 00_10_00_10b": { "ExpectedInstructionCount": 3, "Comment": [ @@ -707,6 +731,17 @@ "zip1 v16.2d, v2.2d, v2.2d" ] }, + "pshufd xmm0, [rax], 10_11_00_01b": { + "ExpectedInstructionCount": 2, + "Comment": [ + "Inverse elements", + "0x66 0x0f 0x70" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x4]", + "rev64 v16.4s, v2.4s" + ] + }, "pshufd xmm0, [rax], 10_11_10_11b": { "ExpectedInstructionCount": 3, "Comment": [