From b79083e510e347ce899b7aca8abd753b944f02e7 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sun, 12 Apr 2020 17:46:42 -0700
Subject: [PATCH 1/2] Implements CVTSD2SI

---
 External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 761c012ea..944e07fa9 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5726,6 +5726,7 @@ void InstallOpcodeHandlers() {
     {0x19, 7, &OpDispatchBuilder::NOPOp},
     {0x2A, 1, &OpDispatchBuilder::CVTGPR_To_FPR<8, true>},
     {0x2C, 1, &OpDispatchBuilder::CVTFPR_To_GPR<8, true>},
+    {0x2D, 1, &OpDispatchBuilder::CVTFPR_To_GPR<8, true>},
     {0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 8, true>},
     //x52 = Invalid
     {0x58, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFADD, 8>},

From 3f0798721cfe7d0e529f36e0932c689ace68d1fd Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sun, 12 Apr 2020 17:46:58 -0700
Subject: [PATCH 2/2] Adds unit test for CVTSD2SI

---
 unittests/ASM/REPNE/F2_2D.asm | 46 +++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 unittests/ASM/REPNE/F2_2D.asm

diff --git a/unittests/ASM/REPNE/F2_2D.asm b/unittests/ASM/REPNE/F2_2D.asm
new file mode 100644
index 000000000..a40ffb214
--- /dev/null
+++ b/unittests/ASM/REPNE/F2_2D.asm
@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x1",
+    "RBX": "0x2",
+    "RCX": "0x3",
+    "RDX": "0x4"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+mov rdx, 0xe0000000
+
+mov rax, 0x3FF0000000000000
+mov [rdx + 8 * 0], rax
+mov rax, 0x5152535455565758
+mov [rdx + 8 * 1], rax
+
+mov rax, 0x4000000000000000
+mov [rdx + 8 * 2], rax
+mov rax, 0x5152535455565758
+mov [rdx + 8 * 3], rax
+
+mov rax, 0x4008000000000000
+mov [rdx + 8 * 4], rax
+mov rax, 0x5152535455565758
+mov [rdx + 8 * 5], rax
+
+mov rax, 0x4010000000000000
+mov [rdx + 8 * 6], rax
+mov rax, 0x5152535455565758
+mov [rdx + 8 * 7], rax
+
+movapd xmm0, [rdx + 8 * 0]
+movapd xmm1, [rdx + 8 * 2]
+
+cvtsd2si eax, xmm0
+cvtsd2si rbx, xmm1
+
+cvtsd2si ecx, [rdx + 8 * 4]
+cvtsd2si rdx, [rdx + 8 * 6]
+
+hlt