From cfbeece09ff3f6837567853239fe9b58f4a380ee Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 21 Feb 2024 17:02:47 -0400 Subject: [PATCH] JIT: use GetZeroableReg for CondAddNZCV Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 3aa13dad9..63a527c24 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -283,9 +283,7 @@ DEF_OP(CondAddNZCV) { ARMEmitter::StatusFlags Flags = (ARMEmitter::StatusFlags)Op->FalseNZCV; uint64_t Const = 0; - auto Src1 = IsInlineConstant(Op->Src1, &Const) ? ARMEmitter::Reg::zr : - GetReg(Op->Src1.ID()); - LOGMAN_THROW_A_FMT(Const == 0, "Unsupported inline constant"); + auto Src1 = GetZeroableReg(Op->Src1); if (IsInlineConstant(Op->Src2, &Const)) { ccmn(EmitSize, Src1, Const, Flags, MapSelectCC(Op->Cond));