From d3b2ddf6410fe16903f730dfbf3c4e5a90d041ed Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sat, 30 Mar 2024 13:35:01 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../InstructionCountCI/FlagM/FlagOpts.json | 27 +- .../FlagM/PrimaryGroup.json | 292 +++++++------- .../InstructionCountCI/PrimaryGroup.json | 368 +++++++++--------- 3 files changed, 351 insertions(+), 336 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index a1e03dab2..68d73e803 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -197,25 +197,24 @@ ] }, "Variable rotate-through-carry dead": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "x86Insts": [ "rcr rax, cl", "test rax, rdx" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr x21, x20, x5", - "cset w22, hs", - "and x23, x5, #0x3f", - "cbz x23, #+0x2c", - "neg x24, x23", - "lsl x25, x20, x24", - "orr x21, x21, x25, lsl #1", - "sub x23, x23, #0x1 (1)", - "lsr x20, x20, x23", - "rmif x20, #63, #nzCv", - "lsl x20, x22, x24", - "orr x4, x21, x20", + "and x20, x5, #0x3f", + "cbz x20, #+0x34", + "lsr x20, x4, x5", + "cset w21, hs", + "neg x22, x5", + "lsl x23, x4, x22", + "orr x20, x20, x23, lsl #1", + "sub x23, x5, #0x1 (1)", + "lsr x23, x4, x23", + "rmif x23, #63, #nzCv", + "lsl x21, x21, x22", + "orr x4, x20, x21", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV", "ands x26, x4, x6" diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index dd7ce4bd1..8596b0f24 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -934,23 +934,25 @@ ] }, "rcl al, 2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 20, "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "cset w21, hs", - "uxtb w22, w4", - "bfi x20, x22, #55, #8", - "bfi x20, x21, #63, #1", - "bfi x20, x22, #46, #8", - "bfi x20, x21, #54, #1", - "bfi x20, x22, #37, #8", - "bfi x20, x21, #45, #1", - "bfi x20, x22, #28, #8", - "bfi x20, x21, #36, #1", - "bfi x20, x22, #19, #8", - "bfi x20, x21, #27, #1", - "bfxil x20, x22, #0, #8", + "uxtb w20, w4", + "mov w21, #0x0", + "cset w22, hs", + "bfi x21, x20, #55, #8", + "bfi x21, x22, #63, #1", + "bfi x21, x20, #46, #8", + "bfi x21, x22, #54, #1", + "bfi x21, x20, #37, #8", + "bfi x21, x22, #45, #1", + "bfi x21, x20, #28, #8", + "bfi x21, x22, #36, #1", + "bfi x21, x20, #19, #8", + "bfi x21, x22, #27, #1", + "mov x0, x21", + "bfxil x0, x20, #0, #8", + "mov x20, x0", "ror x21, x20, #62", "bfxil x4, x21, #0, #8", "ror x20, x20, #61", @@ -969,7 +971,7 @@ "bfi x20, x20, #9, #9", "bfi x20, x20, #18, #18", "bfi x20, x20, #36, #9", - "lsr x21, x20, #2", + "lsr w21, w20, #2", "bfxil x4, x21, #0, #8", "rmif x20, #0, #nzCv" ] @@ -1063,19 +1065,21 @@ ] }, "rcl ax, 2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "cset w21, hs", - "uxth w22, w4", - "bfi x20, x22, #47, #16", - "bfi x20, x21, #63, #1", - "bfi x20, x22, #30, #16", - "bfi x20, x21, #46, #1", - "bfi x20, x22, #13, #16", - "bfi x20, x21, #29, #1", - "bfxil x20, x22, #0, #16", + "uxth w20, w4", + "mov w21, #0x0", + "cset w22, hs", + "bfi x21, x20, #47, #16", + "bfi x21, x22, #63, #1", + "bfi x21, x20, #30, #16", + "bfi x21, x22, #46, #1", + "bfi x21, x20, #13, #16", + "bfi x21, x22, #29, #1", + "mov x0, x21", + "bfxil x0, x20, #0, #16", + "mov x20, x0", "ror x21, x20, #62", "bfxil x4, x21, #0, #16", "ror x20, x20, #61", @@ -1115,7 +1119,7 @@ "mov x20, x0", "bfi x20, x20, #17, #17", "bfi x20, x20, #34, #17", - "lsr x21, x20, #2", + "lsr w21, w20, #2", "bfxil x4, x21, #0, #16", "rmif x20, #0, #nzCv" ] @@ -1624,31 +1628,31 @@ "ExpectedInstructionCount": 28, "Comment": "GROUP2 0xd2 /2", "ExpectedArm64ASM": [ - "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x68", - "uxtb w22, w4", - "mov w23, #0x0", - "bfi x23, x22, #55, #8", - "bfi x23, x20, #63, #1", - "bfi x23, x22, #46, #8", - "bfi x23, x20, #54, #1", - "bfi x23, x22, #37, #8", - "bfi x23, x20, #45, #1", - "bfi x23, x22, #28, #8", - "bfi x23, x20, #36, #1", - "bfi x23, x22, #19, #8", - "mov x0, x23", - "bfi x0, x20, #27, #1", - "mov x20, x0", - "bfxil x20, x22, #0, #8", - "mov w22, #0x40", - "sub w22, w22, w21", - "ror x22, x20, x22", + "and w20, w5, #0x1f", + "cbz x20, #+0x6c", + "and w20, w5, #0x1f", + "uxtb w21, w4", + "mov w22, #0x0", + "cset w23, hs", + "bfi x22, x21, #55, #8", + "bfi x22, x23, #63, #1", + "bfi x22, x21, #46, #8", + "bfi x22, x23, #54, #1", + "bfi x22, x21, #37, #8", + "bfi x22, x23, #45, #1", + "bfi x22, x21, #28, #8", + "bfi x22, x23, #36, #1", + "bfi x22, x21, #19, #8", + "bfi x22, x23, #27, #1", + "mov x0, x22", + "bfxil x0, x21, #0, #8", + "mov x21, x0", + "neg w22, w20", + "ror x22, x21, x22", "bfxil x4, x22, #0, #8", "mov w23, #0x3f", - "sub x21, x23, x21", - "ror x20, x20, x21", + "sub x20, x23, x20", + "ror x20, x21, x20", "rmif x20, #63, #nzCv", "eor x20, x20, x22, lsr #7", "rmif x20, #0, #nzcV" @@ -1658,22 +1662,22 @@ "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd2 /3", "ExpectedArm64ASM": [ + "and w20, w5, #0x1f", + "cbz x20, #+0x40", "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x3c", - "uxtb w22, w4", - "mov x0, x22", + "uxtb w21, w4", + "mov x0, x21", "bfi x0, x20, #8, #1", "mov x20, x0", "bfi x20, x20, #9, #9", "bfi x20, x20, #18, #18", "bfi x20, x20, #36, #9", - "lsr x22, x20, x21", - "bfxil x4, x22, #0, #8", - "sub w21, w21, #0x1 (1)", - "lsr x20, x20, x21", + "lsr w21, w20, w5", + "bfxil x4, x21, #0, #8", + "sub w22, w5, #0x1 (1)", + "lsr w20, w20, w22", "rmif x20, #63, #nzCv", - "eor x20, x22, x22, lsr #1", + "eor w20, w21, w21, lsr #1", "rmif x20, #6, #nzcV" ] }, @@ -1830,71 +1834,69 @@ "ExpectedInstructionCount": 24, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x58", - "uxth w22, w4", - "mov w23, #0x0", - "bfi x23, x22, #47, #16", - "bfi x23, x20, #63, #1", - "bfi x23, x22, #30, #16", - "bfi x23, x20, #46, #1", - "bfi x23, x22, #13, #16", - "mov x0, x23", - "bfi x0, x20, #29, #1", - "mov x20, x0", - "bfxil x20, x22, #0, #16", - "mov w22, #0x40", - "sub w22, w22, w21", - "ror x22, x20, x22", + "and w20, w5, #0x1f", + "cbz x20, #+0x5c", + "and w20, w5, #0x1f", + "uxth w21, w4", + "mov w22, #0x0", + "cset w23, hs", + "bfi x22, x21, #47, #16", + "bfi x22, x23, #63, #1", + "bfi x22, x21, #30, #16", + "bfi x22, x23, #46, #1", + "bfi x22, x21, #13, #16", + "bfi x22, x23, #29, #1", + "mov x0, x22", + "bfxil x0, x21, #0, #16", + "mov x21, x0", + "neg w22, w20", + "ror x22, x21, x22", "bfxil x4, x22, #0, #16", "mov w23, #0x3f", - "sub x21, x23, x21", - "ror x20, x20, x21", + "sub x20, x23, x20", + "ror x20, x21, x20", "rmif x20, #63, #nzCv", "eor x20, x20, x22, lsr #15", "rmif x20, #0, #nzcV" ] }, "rcl eax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl w21, w20, w5", - "cset w22, hs", - "and w23, w5, #0x1f", - "cbz x23, #+0x2c", - "neg w24, w23", - "lsr w25, w20, w24", - "orr w21, w21, w25, lsr #1", - "lsr w20, w20, w24", - "rmif x20, #63, #nzCv", - "sub w23, w23, #0x1 (1)", - "lsl x22, x22, x23", - "orr w4, w21, w22", - "eor w20, w4, w20, lsl #31", + "and w20, w5, #0x1f", + "cbz x20, #+0x34", + "lsl w20, w4, w5", + "cset w21, hs", + "neg w22, w5", + "lsr w23, w4, w22", + "orr w20, w20, w23, lsr #1", + "lsr w22, w4, w22", + "rmif x22, #63, #nzCv", + "sub w23, w5, #0x1 (1)", + "lsl w21, w21, w23", + "orr w4, w20, w21", + "eor w20, w4, w22, lsl #31", "rmif x20, #31, #nzcV" ] }, "rcl rax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl x21, x20, x5", - "cset w22, hs", - "and x23, x5, #0x3f", - "cbz x23, #+0x2c", - "neg x24, x23", - "lsr x25, x20, x24", - "orr x21, x21, x25, lsr #1", - "lsr x20, x20, x24", - "rmif x20, #63, #nzCv", - "sub x23, x23, #0x1 (1)", - "lsl x22, x22, x23", - "orr x4, x21, x22", - "eor x20, x4, x20, lsl #63", + "and x20, x5, #0x3f", + "cbz x20, #+0x34", + "lsl x20, x4, x5", + "cset w21, hs", + "neg x22, x5", + "lsr x23, x4, x22", + "orr x20, x20, x23, lsr #1", + "lsr x22, x4, x22", + "rmif x22, #63, #nzCv", + "sub x23, x5, #0x1 (1)", + "lsl x21, x21, x23", + "orr x4, x20, x21", + "eor x20, x4, x22, lsl #63", "rmif x20, #63, #nzcV" ] }, @@ -1902,62 +1904,60 @@ "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ + "and w20, w5, #0x1f", + "cbz x20, #+0x3c", "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x38", - "uxth w22, w4", - "mov x0, x22", + "uxth w21, w4", + "mov x0, x21", "bfi x0, x20, #16, #1", "mov x20, x0", "bfi x20, x20, #17, #17", "bfi x20, x20, #34, #17", - "lsr x22, x20, x21", - "bfxil x4, x22, #0, #16", - "sub w21, w21, #0x1 (1)", - "lsr x20, x20, x21", + "lsr w21, w20, w5", + "bfxil x4, x21, #0, #16", + "sub w22, w5, #0x1 (1)", + "lsr w20, w20, w22", "rmif x20, #63, #nzCv", - "eor x20, x22, x22, lsr #1", + "eor w20, w21, w21, lsr #1", "rmif x20, #14, #nzcV" ] }, "rcr eax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr w21, w20, w5", - "cset w22, hs", - "and w23, w5, #0x1f", - "cbz x23, #+0x2c", - "neg w24, w23", - "lsl w25, w20, w24", - "orr w21, w21, w25, lsl #1", - "sub w23, w23, #0x1 (1)", - "lsr w20, w20, w23", - "rmif x20, #63, #nzCv", - "lsl w20, w22, w24", - "orr w4, w21, w20", + "and w20, w5, #0x1f", + "cbz x20, #+0x34", + "lsr w20, w4, w5", + "cset w21, hs", + "neg w22, w5", + "lsl w23, w4, w22", + "orr w20, w20, w23, lsl #1", + "sub w23, w5, #0x1 (1)", + "lsr w23, w4, w23", + "rmif x23, #63, #nzCv", + "lsl w21, w21, w22", + "orr w4, w20, w21", "eor w20, w4, w4, lsr #1", "rmif x20, #30, #nzcV" ] }, "rcr rax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr x21, x20, x5", - "cset w22, hs", - "and x23, x5, #0x3f", - "cbz x23, #+0x2c", - "neg x24, x23", - "lsl x25, x20, x24", - "orr x21, x21, x25, lsl #1", - "sub x23, x23, #0x1 (1)", - "lsr x20, x20, x23", - "rmif x20, #63, #nzCv", - "lsl x20, x22, x24", - "orr x4, x21, x20", + "and x20, x5, #0x3f", + "cbz x20, #+0x34", + "lsr x20, x4, x5", + "cset w21, hs", + "neg x22, x5", + "lsl x23, x4, x22", + "orr x20, x20, x23, lsl #1", + "sub x23, x5, #0x1 (1)", + "lsr x23, x4, x23", + "rmif x23, #63, #nzCv", + "lsl x21, x21, x22", + "orr x4, x20, x21", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV" ] diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 66426ee8c..118a352f3 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -1029,33 +1029,38 @@ ] }, "rcl al, 2": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 25, "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "cset w21, hs", - "uxtb w22, w4", - "bfi x20, x22, #55, #8", - "bfi x20, x21, #63, #1", - "bfi x20, x22, #46, #8", - "bfi x20, x21, #54, #1", - "bfi x20, x22, #37, #8", - "bfi x20, x21, #45, #1", - "bfi x20, x22, #28, #8", - "bfi x20, x21, #36, #1", - "bfi x20, x22, #19, #8", - "bfi x20, x21, #27, #1", - "bfxil x20, x22, #0, #8", + "uxtb w20, w4", + "mov w21, #0x0", + "cset w22, hs", + "bfi x21, x20, #55, #8", + "bfi x21, x22, #63, #1", + "bfi x21, x20, #46, #8", + "bfi x21, x22, #54, #1", + "bfi x21, x20, #37, #8", + "bfi x21, x22, #45, #1", + "bfi x21, x20, #28, #8", + "bfi x21, x22, #36, #1", + "bfi x21, x20, #19, #8", + "bfi x21, x22, #27, #1", + "mov x0, x21", + "bfxil x0, x20, #0, #8", + "mov x20, x0", "ror x21, x20, #62", "bfxil x4, x21, #0, #8", "ror x20, x20, #61", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rcr al, 2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xC0 /3", "ExpectedArm64ASM": [ "cset w20, hs", @@ -1066,10 +1071,13 @@ "bfi x20, x20, #9, #9", "bfi x20, x20, #18, #18", "bfi x20, x20, #36, #9", - "lsr x21, x20, #2", + "lsr w21, w20, #2", "bfxil x4, x21, #0, #8", "ubfx x20, x20, #1, #1", - "lsl x20, x20, #29", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -1195,24 +1203,29 @@ ] }, "rcl ax, 2": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 21, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "cset w21, hs", - "uxth w22, w4", - "bfi x20, x22, #47, #16", - "bfi x20, x21, #63, #1", - "bfi x20, x22, #30, #16", - "bfi x20, x21, #46, #1", - "bfi x20, x22, #13, #16", - "bfi x20, x21, #29, #1", - "bfxil x20, x22, #0, #16", + "uxth w20, w4", + "mov w21, #0x0", + "cset w22, hs", + "bfi x21, x20, #47, #16", + "bfi x21, x22, #63, #1", + "bfi x21, x20, #30, #16", + "bfi x21, x22, #46, #1", + "bfi x21, x20, #13, #16", + "bfi x21, x22, #29, #1", + "mov x0, x21", + "bfxil x0, x20, #0, #16", + "mov x20, x0", "ror x21, x20, #62", "bfxil x4, x21, #0, #16", "ror x20, x20, #61", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -1243,7 +1256,7 @@ ] }, "rcr ax, 2": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "cset w20, hs", @@ -1253,10 +1266,13 @@ "mov x20, x0", "bfi x20, x20, #17, #17", "bfi x20, x20, #34, #17", - "lsr x21, x20, #2", + "lsr w21, w20, #2", "bfxil x4, x21, #0, #16", "ubfx x20, x20, #1, #1", - "lsl x20, x20, #29", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -1953,31 +1969,31 @@ "ExpectedInstructionCount": 36, "Comment": "GROUP2 0xd2 /2", "ExpectedArm64ASM": [ - "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x88", - "uxtb w22, w4", - "mov w23, #0x0", - "bfi x23, x22, #55, #8", - "bfi x23, x20, #63, #1", - "bfi x23, x22, #46, #8", - "bfi x23, x20, #54, #1", - "bfi x23, x22, #37, #8", - "bfi x23, x20, #45, #1", - "bfi x23, x22, #28, #8", - "bfi x23, x20, #36, #1", - "bfi x23, x22, #19, #8", - "mov x0, x23", - "bfi x0, x20, #27, #1", - "mov x20, x0", - "bfxil x20, x22, #0, #8", - "mov w22, #0x40", - "sub w22, w22, w21", - "ror x22, x20, x22", + "and w20, w5, #0x1f", + "cbz x20, #+0x8c", + "and w20, w5, #0x1f", + "uxtb w21, w4", + "mov w22, #0x0", + "cset w23, hs", + "bfi x22, x21, #55, #8", + "bfi x22, x23, #63, #1", + "bfi x22, x21, #46, #8", + "bfi x22, x23, #54, #1", + "bfi x22, x21, #37, #8", + "bfi x22, x23, #45, #1", + "bfi x22, x21, #28, #8", + "bfi x22, x23, #36, #1", + "bfi x22, x21, #19, #8", + "bfi x22, x23, #27, #1", + "mov x0, x22", + "bfxil x0, x21, #0, #8", + "mov x21, x0", + "neg w22, w20", + "ror x22, x21, x22", "bfxil x4, x22, #0, #8", "mov w23, #0x3f", - "sub x21, x23, x21", - "ror x20, x20, x21", + "sub x20, x23, x20", + "ror x20, x21, x20", "ubfx x21, x20, #0, #1", "mrs x23, nzcv", "mov w0, w23", @@ -1995,26 +2011,26 @@ "ExpectedInstructionCount": 23, "Comment": "GROUP2 0xd2 /3", "ExpectedArm64ASM": [ + "and w20, w5, #0x1f", + "cbz x20, #+0x58", "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x54", - "uxtb w22, w4", - "mov x0, x22", + "uxtb w21, w4", + "mov x0, x21", "bfi x0, x20, #8, #1", "mov x20, x0", "bfi x20, x20, #9, #9", "bfi x20, x20, #18, #18", "bfi x20, x20, #36, #9", - "lsr x22, x20, x21", - "bfxil x4, x22, #0, #8", - "sub w21, w21, #0x1 (1)", - "lsr x20, x20, x21", + "lsr w21, w20, w5", + "bfxil x4, x21, #0, #8", + "sub w22, w5, #0x1 (1)", + "lsr w20, w20, w22", "ubfx x20, x20, #0, #1", - "mrs x21, nzcv", - "mov w0, w21", + "mrs x22, nzcv", + "mov w0, w22", "bfi w0, w20, #29, #1", "mov w20, w0", - "eor x21, x22, x22, lsr #1", + "eor w21, w21, w21, lsr #1", "ubfx x21, x21, #6, #1", "bfi w20, w21, #28, #1", "msr nzcv, x20" @@ -2214,27 +2230,27 @@ "ExpectedInstructionCount": 32, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x78", - "uxth w22, w4", - "mov w23, #0x0", - "bfi x23, x22, #47, #16", - "bfi x23, x20, #63, #1", - "bfi x23, x22, #30, #16", - "bfi x23, x20, #46, #1", - "bfi x23, x22, #13, #16", - "mov x0, x23", - "bfi x0, x20, #29, #1", - "mov x20, x0", - "bfxil x20, x22, #0, #16", - "mov w22, #0x40", - "sub w22, w22, w21", - "ror x22, x20, x22", + "and w20, w5, #0x1f", + "cbz x20, #+0x7c", + "and w20, w5, #0x1f", + "uxth w21, w4", + "mov w22, #0x0", + "cset w23, hs", + "bfi x22, x21, #47, #16", + "bfi x22, x23, #63, #1", + "bfi x22, x21, #30, #16", + "bfi x22, x23, #46, #1", + "bfi x22, x21, #13, #16", + "bfi x22, x23, #29, #1", + "mov x0, x22", + "bfxil x0, x21, #0, #16", + "mov x21, x0", + "neg w22, w20", + "ror x22, x21, x22", "bfxil x4, x22, #0, #16", "mov w23, #0x3f", - "sub x21, x23, x21", - "ror x20, x20, x21", + "sub x20, x23, x20", + "ror x20, x21, x20", "ubfx x21, x20, #0, #1", "mrs x23, nzcv", "mov w0, w23", @@ -2249,58 +2265,56 @@ ] }, "rcl eax, cl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl w21, w20, w5", - "cset w22, hs", - "and w23, w5, #0x1f", - "cbz x23, #+0x4c", - "neg w24, w23", - "lsr w25, w20, w24", - "orr w21, w21, w25, lsr #1", - "lsr w20, w20, w24", - "ubfx x24, x20, #0, #1", - "mrs x25, nzcv", - "mov w0, w25", - "bfi w0, w24, #29, #1", - "mov w24, w0", - "sub w23, w23, #0x1 (1)", - "lsl x22, x22, x23", - "orr w4, w21, w22", - "eor w20, w4, w20, lsl #31", - "ubfx x20, x20, #31, #1", + "and w20, w5, #0x1f", + "cbz x20, #+0x54", + "lsl w20, w4, w5", + "cset w21, hs", + "neg w22, w5", + "lsr w23, w4, w22", + "orr w20, w20, w23, lsr #1", + "lsr w22, w4, w22", + "ubfx x23, x22, #0, #1", + "mrs x24, nzcv", "mov w0, w24", + "bfi w0, w23, #29, #1", + "mov w23, w0", + "sub w24, w5, #0x1 (1)", + "lsl w21, w21, w24", + "orr w4, w20, w21", + "eor w20, w4, w22, lsl #31", + "ubfx x20, x20, #31, #1", + "mov w0, w23", "bfi w0, w20, #28, #1", "mov w20, w0", "msr nzcv, x20" ] }, "rcl rax, cl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl x21, x20, x5", - "cset w22, hs", - "and x23, x5, #0x3f", - "cbz x23, #+0x4c", - "neg x24, x23", - "lsr x25, x20, x24", - "orr x21, x21, x25, lsr #1", - "lsr x20, x20, x24", - "ubfx x24, x20, #0, #1", - "mrs x25, nzcv", - "mov w0, w25", - "bfi w0, w24, #29, #1", - "mov w24, w0", - "sub x23, x23, #0x1 (1)", - "lsl x22, x22, x23", - "orr x4, x21, x22", - "eor x20, x4, x20, lsl #63", - "lsr x20, x20, #63", + "and x20, x5, #0x3f", + "cbz x20, #+0x54", + "lsl x20, x4, x5", + "cset w21, hs", + "neg x22, x5", + "lsr x23, x4, x22", + "orr x20, x20, x23, lsr #1", + "lsr x22, x4, x22", + "ubfx x23, x22, #0, #1", + "mrs x24, nzcv", "mov w0, w24", + "bfi w0, w23, #29, #1", + "mov w23, w0", + "sub x24, x5, #0x1 (1)", + "lsl x21, x21, x24", + "orr x4, x20, x21", + "eor x20, x4, x22, lsl #63", + "lsr x20, x20, #63", + "mov w0, w23", "bfi w0, w20, #28, #1", "mov w20, w0", "msr nzcv, x20" @@ -2310,81 +2324,83 @@ "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ + "and w20, w5, #0x1f", + "cbz x20, #+0x54", "cset w20, hs", - "and w21, w5, #0x1f", - "cbz x21, #+0x50", - "uxth w22, w4", - "mov x0, x22", + "uxth w21, w4", + "mov x0, x21", "bfi x0, x20, #16, #1", "mov x20, x0", "bfi x20, x20, #17, #17", "bfi x20, x20, #34, #17", - "lsr x22, x20, x21", - "bfxil x4, x22, #0, #16", - "sub w21, w21, #0x1 (1)", - "lsr x20, x20, x21", + "lsr w21, w20, w5", + "bfxil x4, x21, #0, #16", + "sub w22, w5, #0x1 (1)", + "lsr w20, w20, w22", "ubfx x20, x20, #0, #1", - "mrs x21, nzcv", - "mov w0, w21", + "mrs x22, nzcv", + "mov w0, w22", "bfi w0, w20, #29, #1", "mov w20, w0", - "eor x21, x22, x22, lsr #1", + "eor w21, w21, w21, lsr #1", "ubfx x21, x21, #14, #1", "bfi w20, w21, #28, #1", "msr nzcv, x20" ] }, "rcr eax, cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr w21, w20, w5", - "cset w22, hs", - "and w23, w5, #0x1f", - "cbz x23, #+0x44", - "neg w24, w23", - "lsl w25, w20, w24", - "orr w21, w21, w25, lsl #1", - "sub w23, w23, #0x1 (1)", - "lsr w20, w20, w23", - "ubfx x20, x20, #0, #1", - "mrs x23, nzcv", + "and w20, w5, #0x1f", + "cbz x20, #+0x54", + "lsr w20, w4, w5", + "cset w21, hs", + "neg w22, w5", + "lsl w23, w4, w22", + "orr w20, w20, w23, lsl #1", + "sub w23, w5, #0x1 (1)", + "lsr w23, w4, w23", + "ubfx x23, x23, #0, #1", + "mrs x24, nzcv", + "mov w0, w24", + "bfi w0, w23, #29, #1", + "mov w23, w0", + "lsl w21, w21, w22", + "orr w4, w20, w21", + "eor w20, w4, w4, lsr #1", + "ubfx x20, x20, #30, #1", "mov w0, w23", - "bfi w0, w20, #29, #1", + "bfi w0, w20, #28, #1", "mov w20, w0", - "lsl w22, w22, w24", - "orr w4, w21, w22", - "eor w21, w4, w4, lsr #1", - "ubfx x21, x21, #30, #1", - "bfi w20, w21, #28, #1", "msr nzcv, x20" ] }, "rcr rax, cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr x21, x20, x5", - "cset w22, hs", - "and x23, x5, #0x3f", - "cbz x23, #+0x44", - "neg x24, x23", - "lsl x25, x20, x24", - "orr x21, x21, x25, lsl #1", - "sub x23, x23, #0x1 (1)", - "lsr x20, x20, x23", - "ubfx x20, x20, #0, #1", - "mrs x23, nzcv", + "and x20, x5, #0x3f", + "cbz x20, #+0x54", + "lsr x20, x4, x5", + "cset w21, hs", + "neg x22, x5", + "lsl x23, x4, x22", + "orr x20, x20, x23, lsl #1", + "sub x23, x5, #0x1 (1)", + "lsr x23, x4, x23", + "ubfx x23, x23, #0, #1", + "mrs x24, nzcv", + "mov w0, w24", + "bfi w0, w23, #29, #1", + "mov w23, w0", + "lsl x21, x21, x22", + "orr x4, x20, x21", + "eor x20, x4, x4, lsr #1", + "ubfx x20, x20, #62, #1", "mov w0, w23", - "bfi w0, w20, #29, #1", + "bfi w0, w20, #28, #1", "mov w20, w0", - "lsl x22, x22, x24", - "orr x4, x21, x22", - "eor x21, x4, x4, lsr #1", - "ubfx x21, x21, #62, #1", - "bfi w20, w21, #28, #1", "msr nzcv, x20" ] },