From d5481efa6beea218ea19531d20d23fdff86413f6 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 12 Mar 2020 22:13:53 -0700
Subject: [PATCH] Fixes AtomicFetch{Add,Sub} for 8bit and 16bit ops in the x86
 JIT

---
 .../FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
index 8573c54c1..844fde21c 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -3193,13 +3193,13 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
             mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
             lock();
             xadd(byte [MemReg], cl);
-            mov(GetDst<RA_8>(Node), cl);
+            movzx(GetDst<RA_32>(Node), cl);
           break;
           case 2:
             mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
             lock();
-            xadd(word [MemReg], cl);
-            mov(GetDst<RA_16>(Node), cx);
+            xadd(word [MemReg], cx);
+            movzx(GetDst<RA_32>(Node), cx);
           break;
           case 4:
             mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
@@ -3236,14 +3236,14 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
             neg(cl);
             lock();
             xadd(byte [MemReg], cl);
-            mov(GetDst<RA_8>(Node), cl);
+            movzx(GetDst<RA_32>(Node), cl);
           break;
           case 2:
             mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
             neg(cx);
             lock();
-            xadd(word [MemReg], cl);
-            mov(GetDst<RA_16>(Node), cx);
+            xadd(word [MemReg], cx);
+            movzx(GetDst<RA_32>(Node), cx);
           break;
           case 4:
             mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));