From d5c039cdc7c2c2d94ece8979bdf587fef7eac077 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 14 Jun 2022 10:15:25 -0400 Subject: [PATCH] Arm64/EncryptionOps: Fix register specifiers in PCLMUL movs Prevents an assertion from firing in vixl, since the destination needs to be a scalar --- .../FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp index 5bc278ba9..9d2c334f4 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp @@ -114,11 +114,11 @@ DEF_OP(PCLMUL) { pmull(Dst, Src1, Src2); break; case 0b00000001: - mov(VTMP1.V2D(), Src1, 1); + mov(VTMP1.V1D(), Src1, 1); pmull(Dst, VTMP1.V2D(), Src2); break; case 0b00010000: - mov(VTMP1.V2D(), Src2, 1); + mov(VTMP1.V1D(), Src2, 1); pmull(Dst, VTMP1.V2D(), Src1); break; case 0b00010001: