From d65fcf7bb8fee59917ff3a342eaf73e050fabc87 Mon Sep 17 00:00:00 2001 From: Lioncache Date: Sat, 4 Feb 2023 05:04:21 -0500 Subject: [PATCH] ARMEmitter: Handle SVE SQRDMULH (vectors) --- .../Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl | 3 +++ External/FEXCore/unittests/Emitter/SVE_Tests.cpp | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl index 42c9902bc..b72f2f01e 100644 --- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl @@ -1403,6 +1403,9 @@ public: void sqdmulh(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) { SVE2IntegerMultiplyVectors(0b100, size, zm, zn, zd); } + void sqrdmulh(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) { + SVE2IntegerMultiplyVectors(0b101, size, zm, zn, zd); + } // SVE Bitwise Shift - Unpredicated // SVE bitwise shift by wide elements (unpredicated) diff --git a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp index 0378cd7d4..62a863bb2 100644 --- a/External/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/External/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -933,6 +933,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 signed saturating doublin TEST_SINGLE(sqdmulh(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.h, z29.h, z28.h"); TEST_SINGLE(sqdmulh(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.s, z29.s, z28.s"); TEST_SINGLE(sqdmulh(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqdmulh z30.d, z29.d, z28.d"); + + TEST_SINGLE(sqrdmulh(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.b, z29.b, z28.b"); + TEST_SINGLE(sqrdmulh(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.h, z29.h, z28.h"); + TEST_SINGLE(sqrdmulh(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.s, z29.s, z28.s"); + TEST_SINGLE(sqrdmulh(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "sqrdmulh z30.d, z29.d, z28.d"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise shift by wide elements (unpredicated)") {