From d6864871eded4f6847def39d3af5121684f768ea Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 26 Aug 2023 02:42:02 -0700 Subject: [PATCH] InstCountCI: Update for movmskps optimization --- .../InstructionCountCI/PrimaryGroup.json | 8 +-- unittests/InstructionCountCI/Secondary.json | 57 ++++++------------- .../InstructionCountCI/Secondary_OpSize.json | 4 +- .../InstructionCountCI/Secondary_REP.json | 2 +- .../InstructionCountCI/Secondary_REPNE.json | 2 +- .../InstructionCountCI/Secondary_SVE128.json | 24 ++++++++ unittests/InstructionCountCI/VEX_map1.json | 24 ++------ 7 files changed, 56 insertions(+), 65 deletions(-) diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 6036f5f18..185adffb5 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -3603,7 +3603,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1760]", + "ldr x3, [x28, #1768]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3614,7 +3614,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1776]", + "ldr x3, [x28, #1784]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3678,7 +3678,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1768]", + "ldr x3, [x28, #1776]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3691,7 +3691,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #1784]", + "ldr x3, [x28, #1792]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 4615f9302..de31ec5e7 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1000,50 +1000,29 @@ ] }, "movmskps eax, xmm0": { - "ExpectedInstructionCount": 17, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "mov w21, v16.s[0]", - "ubfx x21, x21, #31, #1", - "orr x20, x20, x21", - "mov w21, v16.s[1]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #1", - "orr x20, x20, x21", - "mov w21, v16.s[2]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #2", - "orr x20, x20, x21", - "mov w21, v16.s[3]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #3", - "orr x20, x20, x21", - "ubfx x4, x20, #0, #32" + "ushr v4.4s, v16.4s, #31", + "ldr x0, [x28, #1600]", + "ldr q5, [x0]", + "ushl v4.4s, v4.4s, v5.4s", + "addv s4, v4.4s", + "mov w4, v4.s[0]" ] }, "movmskps rax, xmm0": { - "ExpectedInstructionCount": 16, - "Optimal": "No", + "ExpectedInstructionCount": 6, + "Optimal": "Yes", "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "mov w21, v16.s[0]", - "ubfx x21, x21, #31, #1", - "orr x20, x20, x21", - "mov w21, v16.s[1]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #1", - "orr x20, x20, x21", - "mov w21, v16.s[2]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #2", - "orr x20, x20, x21", - "mov w21, v16.s[3]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #3", - "orr x4, x20, x21" + "ushr v4.4s, v16.4s, #31", + "ldr x0, [x28, #1600]", + "ldr q5, [x0]", + "ushl v4.4s, v4.4s, v5.4s", + "addv s4, v4.4s", + "mov w4, v4.s[0]" ] }, "sqrtps xmm0, xmm1": { @@ -1458,7 +1437,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d4, [x28, #768]", - "ldr x0, [x28, #1600]", + "ldr x0, [x28, #1608]", "ldr d5, [x0, #16]", "tbl v4.8b, {v4.16b}, v5.8b", "str d4, [x28, #752]" @@ -1470,7 +1449,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d4, [x4]", - "ldr x0, [x28, #1600]", + "ldr x0, [x28, #1608]", "ldr d5, [x0, #16]", "tbl v4.8b, {v4.16b}, v5.8b", "str d4, [x28, #752]" diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 98275afab..9df97f956 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -577,7 +577,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1616]", + "ldr x0, [x28, #1624]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b}, v4.16b" ] @@ -592,7 +592,7 @@ ], "ExpectedArm64ASM": [ "ldr q4, [x4]", - "ldr x0, [x28, #1616]", + "ldr x0, [x28, #1624]", "ldr q5, [x0, #16]", "tbl v16.16b, {v4.16b}, v5.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 060a8274a..508e2dc47 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -390,7 +390,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1608]", + "ldr x0, [x28, #1616]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b}, v4.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index e30dae1ad..6c91217ad 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -335,7 +335,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1600]", + "ldr x0, [x28, #1608]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b}, v4.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index d4e878c31..ae4cf5c44 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -9,6 +9,30 @@ ] }, "Instructions": { + "movmskps eax, xmm0": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": "0x0f 0x50", + "ExpectedArm64ASM": [ + "ushr v4.4s, v16.4s, #31", + "index z5.s, #0, #1", + "ushl v4.4s, v4.4s, v5.4s", + "addv s4, v4.4s", + "mov w4, v4.s[0]" + ] + }, + "movmskps rax, xmm0": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": "0x0f 0x50", + "ExpectedArm64ASM": [ + "ushr v4.4s, v16.4s, #31", + "index z5.s, #0, #1", + "ushl v4.4s, v4.4s, v5.4s", + "addv s4, v4.4s", + "mov w4, v4.s[0]" + ] + }, "psrlw mm0, mm1": { "ExpectedInstructionCount": 6, "Optimal": "No", diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index b1fff9915..1bc390f8d 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -522,30 +522,18 @@ ] }, "vmovmskps rax, xmm0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": [ "Map 1 0b00 0x50 128-bit" ], "ExpectedArm64ASM": [ "mov z4.d, p7/m, z16.d", - "mov w20, #0x0", - "mov w21, v4.s[0]", - "ubfx x21, x21, #31, #1", - "orr x20, x20, x21", - "mov w21, v4.s[1]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #1", - "orr x20, x20, x21", - "mov w21, v4.s[2]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #2", - "orr x20, x20, x21", - "mov w21, v4.s[3]", - "ubfx x21, x21, #31, #1", - "lsl w21, w21, #3", - "orr x20, x20, x21", - "ubfx x4, x20, #0, #32" + "ushr v4.4s, v4.4s, #31", + "index z5.s, #0, #1", + "ushl v4.4s, v4.4s, v5.4s", + "addv s4, v4.4s", + "mov w4, v4.s[0]" ] }, "vmovmskps rax, ymm0": {