From d6c3518b746fc07ed3fa403ca5758aa71afff291 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 22 Oct 2020 18:53:43 -0700
Subject: [PATCH] Adds unit tests for 32bit pusha

---
 unittests/32Bit_ASM/Primary/Primary_60.asm   | 44 ++++++++++++++++++++
 unittests/32Bit_ASM/Primary/Primary_60_2.asm | 42 +++++++++++++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 unittests/32Bit_ASM/Primary/Primary_60.asm
 create mode 100644 unittests/32Bit_ASM/Primary/Primary_60_2.asm

diff --git a/unittests/32Bit_ASM/Primary/Primary_60.asm b/unittests/32Bit_ASM/Primary/Primary_60.asm
new file mode 100644
index 000000000..6e400d0a1
--- /dev/null
+++ b/unittests/32Bit_ASM/Primary/Primary_60.asm
@@ -0,0 +1,44 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x6",
+    "RCX": "0x5",
+    "RDX": "0x4",
+    "RSP": "0xE0000020",
+    "RBX": "0x3",
+    "RBP": "0x2",
+    "RSI": "0x1",
+    "RDI": "0x0"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+mov esp, 0xe0000020
+
+mov eax, 0
+mov ecx, 1
+mov edx, 2
+mov ebx, 3
+mov ebp, 4
+mov esi, 5
+mov edi, 6
+
+pushad
+
+; Invert the order
+
+mov eax, [esp + 4 * 0]
+mov ecx, [esp + 4 * 1]
+mov edx, [esp + 4 * 2]
+; sp here
+mov ebx, [esp + 4 * 4]
+mov ebp, [esp + 4 * 5]
+mov esi, [esp + 4 * 6]
+mov edi, [esp + 4 * 7]
+
+; Load sp last
+mov esp, [esp + 4 * 3]
+
+
+hlt
diff --git a/unittests/32Bit_ASM/Primary/Primary_60_2.asm b/unittests/32Bit_ASM/Primary/Primary_60_2.asm
new file mode 100644
index 000000000..c8fc84163
--- /dev/null
+++ b/unittests/32Bit_ASM/Primary/Primary_60_2.asm
@@ -0,0 +1,42 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x6",
+    "RCX": "0x5",
+    "RDX": "0x4",
+    "RSP": "0xE0000020",
+    "RBX": "0x3",
+    "RBP": "0x2",
+    "RSI": "0x1",
+    "RDI": "0x0"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+mov esp, 0xe0000020
+
+mov eax, 0
+mov ecx, 1
+mov edx, 2
+mov ebx, 3
+mov ebp, 4
+mov esi, 5
+mov edi, 6
+
+o16 pusha
+
+; Invert the order
+mov ax, [esp + 2 * 0]
+mov cx, [esp + 2 * 1]
+mov dx, [esp + 2 * 2]
+; sp here
+mov bx, [esp + 2 * 4]
+mov bp, [esp + 2 * 5]
+mov si, [esp + 2 * 6]
+mov di, [esp + 2 * 7]
+
+; Load sp last
+mov sp, [esp + 2 * 3]
+
+hlt