From d91f2ed6b07bd319d1bb2fb9aa959eb78638dce4 Mon Sep 17 00:00:00 2001
From: lioncash <mai.iam2048@gmail.com>
Date: Thu, 29 Dec 2022 16:31:57 +0000
Subject: [PATCH] OpcodeDispatcher: Handle VPUNPCKLBW

---
 .../Interface/Core/OpcodeDispatcher.cpp       |  1 +
 .../Core/OpcodeDispatcher/Vector.cpp          |  2 +
 .../Interface/Core/X86Tables/VEXTables.cpp    |  2 +-
 unittests/ASM/VEX/vpunpcklbw.asm              | 39 +++++++++++++++++++
 4 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 unittests/ASM/VEX/vpunpcklbw.asm

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 6986d445b..e82faeb75 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5904,6 +5904,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b10, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMAX, 4>},
     {OPD(1, 0b11, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMAX, 8>},
 
+    {OPD(1, 0b01, 0x60), 1, &OpDispatchBuilder::VPUNPCKLOp<1>},
     {OPD(1, 0b01, 0x61), 1, &OpDispatchBuilder::VPUNPCKLOp<2>},
     {OPD(1, 0b01, 0x62), 1, &OpDispatchBuilder::VPUNPCKLOp<4>},
     {OPD(1, 0b01, 0x63), 1, &OpDispatchBuilder::VPACKSSOp<2>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index d13418da6..ba426bfa8 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -905,6 +905,8 @@ void OpDispatchBuilder::VPUNPCKLOp(OpcodeArgs) {
   StoreResult(FPRClass, Op, Result, -1);
 }
 
+template
+void OpDispatchBuilder::VPUNPCKLOp<1>(OpcodeArgs);
 template
 void OpDispatchBuilder::VPUNPCKLOp<2>(OpcodeArgs);
 template
diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
index 12d78e7c2..142cdabb8 100644
--- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
+++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -74,7 +74,7 @@ void InitializeVEXTables() {
     {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VXORPD",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(1, 0b01, 0x60), 1, X86InstInfo{"VPUNPCKLBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b01, 0x60), 1, X86InstInfo{"VPUNPCKLBW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0x61), 1, X86InstInfo{"VPUNPCKLWD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0x62), 1, X86InstInfo{"VPUNPCKLDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0x63), 1, X86InstInfo{"VPACKSSWB",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
diff --git a/unittests/ASM/VEX/vpunpcklbw.asm b/unittests/ASM/VEX/vpunpcklbw.asm
new file mode 100644
index 000000000..3acfab363
--- /dev/null
+++ b/unittests/ASM/VEX/vpunpcklbw.asm
@@ -0,0 +1,39 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM2": ["0x6545664667476848", "0x6141624263436444", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x6545664667476848", "0x6141624263436444", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0x6545664667476848", "0x6141624263436444", "0x55DD55DD44CC44CC", "0x77FF77FF66EE66EE"],
+    "XMM5": ["0x6545664667476848", "0x6141624263436444", "0x55DD55DD44CC44CC", "0x77FF77FF66EE66EE"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rdx + 32]
+
+vpunpcklbw xmm2, xmm0, [rdx + 32]
+vpunpcklbw xmm3, xmm0, xmm1
+
+vpunpcklbw ymm4, ymm0, [rdx + 32]
+vpunpcklbw ymm5, ymm0, ymm1
+
+hlt
+
+align 32
+.data:
+dq 0x4142434445464748
+dq 0x5152535455565758
+dq 0xFFFFEEEEDDDDCCCC
+dq 0xBBBBAAAA99998888
+
+dq 0x6162636465666768
+dq 0x7172737475767778
+dq 0x7777666655554444
+dq 0x3333222211110000