From db7b3d415d365337082d27c6ea14f54b2d984e2e Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 31 Oct 2019 16:06:16 -0700
Subject: [PATCH] Adds VBitcast IR op

Casts vector to a integer of the same width as the vector
---
 Source/Interface/Core/JIT/x86_64/JIT.cpp   |  5 +++++
 Source/Interface/Core/LLVMJIT/LLVMCore.cpp | 13 +++++++++++--
 Source/Interface/IR/IR.json                |  6 ++++++
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/Source/Interface/Core/JIT/x86_64/JIT.cpp b/Source/Interface/Core/JIT/x86_64/JIT.cpp
index b818460d0..e6c6ca6a2 100644
--- a/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -1434,6 +1434,11 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
           vpor(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
           break;
         }
+        case IR::OP_VBITCAST: {
+          auto Op = IROp->C<IR::IROp_VBitcast>();
+          movaps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
+        break;
+        }
         case IR::OP_VCMPEQ: {
           auto Op = IROp->C<IR::IROp_VCMPEQ>();
           LogMan::Throw::A(Op->RegisterSize == 16, "Can't handle register size of: %d", Op->RegisterSize);
diff --git a/Source/Interface/Core/LLVMJIT/LLVMCore.cpp b/Source/Interface/Core/LLVMJIT/LLVMCore.cpp
index 13071295f..6ca87a6e7 100644
--- a/Source/Interface/Core/LLVMJIT/LLVMCore.cpp
+++ b/Source/Interface/Core/LLVMJIT/LLVMCore.cpp
@@ -749,7 +749,7 @@ llvm::Value *LLVMJITCore::CastToOpaqueStructure(llvm::Value *Arg, llvm::Type *Ds
     Arg = JITState.IRBuilder->CreateBitCast(Arg, NewIntegerType);
   }
 
-  return JITState.IRBuilder->CreateZExtOrTrunc(Arg, DstType->getPointerElementType());
+  return JITState.IRBuilder->CreateZExtOrTrunc(Arg, DstType);
 }
 
 void LLVMJITCore::SetDest(IR::OrderedNodeWrapper Op, llvm::Value *Val) {
@@ -935,7 +935,7 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
       auto Op = IROp->C<IR::IROp_StoreContext>();
       auto Src = GetSrc(Op->Header.Args[0]);
       auto Value = CreateContextPtr(Op->Offset, Op->Size);
-      Src = CastToOpaqueStructure(Src, Value->getType());
+      Src = CastToOpaqueStructure(Src, Value->getType()->getPointerElementType());
 
       if ((Op->Offset % Op->Size) == 0)
         JITState.IRBuilder->CreateAlignedStore(Src, Value, Op->Size);
@@ -1472,6 +1472,15 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
       SetDest(*WrapperOp, Result);
     break;
     }
+    case IR::OP_VBITCAST: {
+      auto Op = IROp->C<IR::IROp_VBitcast>();
+      auto Src = GetSrc(Op->Header.Args[0]);
+
+      auto Result = CastToOpaqueStructure(Src, Type::getIntNTy(*Con, Src->getType()->getPrimitiveSizeInBits()));
+
+      SetDest(*WrapperOp, Result);
+    break;
+    }
     case IR::OP_VOR: {
       auto Op = IROp->C<IR::IROp_Or>();
       auto Src1 = GetSrc(Op->Header.Args[0]);
diff --git a/Source/Interface/IR/IR.json b/Source/Interface/IR/IR.json
index eecee8afa..9748e2bb7 100644
--- a/Source/Interface/IR/IR.json
+++ b/Source/Interface/IR/IR.json
@@ -540,6 +540,12 @@
         "uint8_t", "Index"
       ]
     },
+
+    "VBitcast": {
+      "HasDest": true,
+      "SSAArgs": "1"
+    },
+
     "Last": {
       "Last": true,
       "Args": []