diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 73bdd6257..932afd7ca 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5959,9 +5959,23 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x1D), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, {OPD(2, 0b01, 0x1E), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, + {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, + {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, + {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, + {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>}, + {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>}, + {OPD(2, 0b01, 0x25), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>}, + {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, + {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, + {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, + {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>}, + {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>}, + {OPD(2, 0b01, 0x35), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>}, + {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x39), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index d394661e5..5f150e955 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -410,6 +410,9 @@ public: template void AVXVectorUnaryOp(OpcodeArgs); + template + void AVXExtendVectorElements(OpcodeArgs); + template void AVXVectorRound(OpcodeArgs); @@ -681,6 +684,9 @@ private: void AVXVectorScalarALUOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize); void AVXVectorUnaryOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize, bool Scalar); + OrderedNode* ExtendVectorElementsImpl(OpcodeArgs, size_t ElementSize, + size_t DstElementSize, bool Signed); + OrderedNode* PSIGNImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src1, OrderedNode *Src2); diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 527b70a9c..b60b6148b 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2609,24 +2609,42 @@ void OpDispatchBuilder::PSADBW(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } -template -void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) { - auto Size = GetDstSize(Op); +OrderedNode* OpDispatchBuilder::ExtendVectorElementsImpl(OpcodeArgs, size_t ElementSize, + size_t DstElementSize, bool Signed) { + const auto DstSize = GetDstSize(Op); - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + const auto GetSrc = [&] { + if (Op->Src[0].IsGPR()) { + return LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], DstSize, Op->Flags, -1); + } else { + // For memory operands the 256-bit variant loads twice the size specified in the table. + const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE; + const auto SrcSize = GetSrcSize(Op); + const auto LoadSize = Is256Bit ? SrcSize * 2 : SrcSize; - OrderedNode *Result {Src}; + return LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], LoadSize, Op->Flags, -1); + } + }; + + OrderedNode *Src = GetSrc(); + OrderedNode *Result{Src}; for (size_t CurrentElementSize = ElementSize; CurrentElementSize != DstElementSize; CurrentElementSize <<= 1) { - if constexpr (Signed) { - Result = _VSXTL(Size, CurrentElementSize, Result); - } - else { - Result = _VUXTL(Size, CurrentElementSize, Result); + if (Signed) { + Result = _VSXTL(DstSize, CurrentElementSize, Result); + } else { + Result = _VUXTL(DstSize, CurrentElementSize, Result); } } + + return Result; +} + +template +void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) { + OrderedNode *Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed); StoreResult(FPRClass, Op, Result, -1); } @@ -2656,6 +2674,45 @@ void OpDispatchBuilder::ExtendVectorElements<2, 8, true>(OpcodeArgs); template void OpDispatchBuilder::ExtendVectorElements<4, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements(OpcodeArgs) { + const auto DstSize = GetDstSize(Op); + const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE; + + OrderedNode *Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed); + + if (Is128Bit) { + Result = _VMov(16, Result); + } + StoreResult(FPRClass, Op, Result, -1); +} + +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>(OpcodeArgs); + +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>(OpcodeArgs); + OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { const auto Size = GetDstSize(Op); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index f803ea869..e19d0a5e3 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -289,12 +289,12 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x1D), 1, X86InstInfo{"VPABSW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x1E), 1, X86InstInfo{"VPABSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x28), 1, X86InstInfo{"VPMULDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x29), 1, X86InstInfo{"VPCMPEQQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, @@ -305,12 +305,12 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x2E), 1, X86InstInfo{"VMASKMOVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x2F), 1, X86InstInfo{"VMASKMOVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, + {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x37), 1, X86InstInfo{"VPCMPGTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxbd.asm b/unittests/ASM/VEX/vpmovsxbd.asm new file mode 100644 index 000000000..523d50d82 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000004300000044", "0x0000004100000042"], + "XMM3": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000004300000044", "0x0000004100000042"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbd xmm1, [rdx] +vpmovsxbd ymm2, [rdx] + +; Register only +vpmovsxbd xmm3, xmm0 +vpmovsxbd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovsxbq.asm b/unittests/ASM/VEX/vpmovsxbq.asm new file mode 100644 index 000000000..423f76616 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0xFFFFFFFFFFFFFF86", "0xFFFFFFFFFFFFFF85"], + "XMM3": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0xFFFFFFFFFFFFFF86", "0xFFFFFFFFFFFFFF85"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbq xmm1, [rdx] +vpmovsxbq ymm2, [rdx] + +; Register only +vpmovsxbq xmm3, xmm0 +vpmovsxbq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovsxbw.asm b/unittests/ASM/VEX/vpmovsxbw.asm new file mode 100644 index 000000000..f4b667e58 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbw.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"], + "XMM3": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbw xmm1, [rdx] +vpmovsxbw ymm2, [rdx] + +; Register only +vpmovsxbw xmm3, xmm0 +vpmovsxbw ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovsxdq.asm b/unittests/ASM/VEX/vpmovsxdq.asm new file mode 100644 index 000000000..2cdfd6db3 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxdq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"], + "XMM3": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxdq xmm1, [rdx] +vpmovsxdq ymm2, [rdx] + +; Register only +vpmovsxdq xmm3, xmm0 +vpmovsxdq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovsxwd.asm b/unittests/ASM/VEX/vpmovsxwd.asm new file mode 100644 index 000000000..a2f06c636 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxwd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"], + "XMM3": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxwd xmm1, [rdx] +vpmovsxwd ymm2, [rdx] + +; Register only +vpmovsxwd xmm3, xmm0 +vpmovsxwd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovsxwq.asm b/unittests/ASM/VEX/vpmovsxwq.asm new file mode 100644 index 000000000..f73f0ea5b --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxwq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000004344", "0x0000000000004142"], + "XMM3": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000004344", "0x0000000000004142"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxwq xmm1, [rdx] +vpmovsxwq ymm2, [rdx] + +; Register only +vpmovsxwq xmm3, xmm0 +vpmovsxwq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxbd.asm b/unittests/ASM/VEX/vpmovzxbd.asm new file mode 100644 index 000000000..f407944ef --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000008700000088", "0x0000008500000086", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000008700000088", "0x0000008500000086", "0x0000004300000044", "0x0000004100000042"], + "XMM3": ["0x0000008700000088", "0x0000008500000086", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000008700000088", "0x0000008500000086", "0x0000004300000044", "0x0000004100000042"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbd xmm1, [rdx] +vpmovzxbd ymm2, [rdx] + +; Register only +vpmovzxbd xmm3, xmm0 +vpmovzxbd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxbq.asm b/unittests/ASM/VEX/vpmovzxbq.asm new file mode 100644 index 000000000..fe57eb4f1 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000086", "0x0000000000000085"], + "XMM3": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000086", "0x0000000000000085"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbq xmm1, [rdx] +vpmovzxbq ymm2, [rdx] + +; Register only +vpmovzxbq xmm3, xmm0 +vpmovzxbq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxbw.asm b/unittests/ASM/VEX/vpmovzxbw.asm new file mode 100644 index 000000000..1b7ca97d1 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbw.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0085008600870088", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0085008600870088", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"], + "XMM3": ["0x0085008600870088", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0085008600870088", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbw xmm1, [rdx] +vpmovzxbw ymm2, [rdx] + +; Register only +vpmovzxbw xmm3, xmm0 +vpmovzxbw ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxdq.asm b/unittests/ASM/VEX/vpmovzxdq.asm new file mode 100644 index 000000000..b81331f6a --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxdq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000085868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000085868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"], + "XMM3": ["0x0000000085868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000085868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxdq xmm1, [rdx] +vpmovzxdq ymm2, [rdx] + +; Register only +vpmovzxdq xmm3, xmm0 +vpmovzxdq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxwd.asm b/unittests/ASM/VEX/vpmovzxwd.asm new file mode 100644 index 000000000..ab7c038f7 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxwd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"], + "XMM3": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxwd xmm1, [rdx] +vpmovzxwd ymm2, [rdx] + +; Register only +vpmovzxwd xmm3, xmm0 +vpmovzxwd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 diff --git a/unittests/ASM/VEX/vpmovzxwq.asm b/unittests/ASM/VEX/vpmovzxwq.asm new file mode 100644 index 000000000..463de4b15 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxwq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000000008788", "0x0000000000008586", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000000008788", "0x0000000000008586", "0x0000000000004344", "0x0000000000004142"], + "XMM3": ["0x0000000000008788", "0x0000000000008586", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000000008788", "0x0000000000008586", "0x0000000000004344", "0x0000000000004142"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxwq xmm1, [rdx] +vpmovzxwq ymm2, [rdx] + +; Register only +vpmovzxwq xmm3, xmm0 +vpmovzxwq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758