From bc31f98f16c060fb9de6434e866f1515b8de5ab0 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 15:59:15 +0000 Subject: [PATCH 01/13] OpcodeDispatcher: Move ExtendVectorElements impl to regular function This can be reused for the AVX versions. --- .../Source/Interface/Core/OpcodeDispatcher.h | 6 +++ .../Core/OpcodeDispatcher/Vector.cpp | 51 +++++++++++++++---- 2 files changed, 47 insertions(+), 10 deletions(-) diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index d394661e5..5f150e955 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -410,6 +410,9 @@ public: template void AVXVectorUnaryOp(OpcodeArgs); + template + void AVXExtendVectorElements(OpcodeArgs); + template void AVXVectorRound(OpcodeArgs); @@ -681,6 +684,9 @@ private: void AVXVectorScalarALUOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize); void AVXVectorUnaryOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize, bool Scalar); + OrderedNode* ExtendVectorElementsImpl(OpcodeArgs, size_t ElementSize, + size_t DstElementSize, bool Signed); + OrderedNode* PSIGNImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src1, OrderedNode *Src2); diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index cf91e023d..ed83ad655 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2609,24 +2609,42 @@ void OpDispatchBuilder::PSADBW(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } -template -void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) { - auto Size = GetDstSize(Op); +OrderedNode* OpDispatchBuilder::ExtendVectorElementsImpl(OpcodeArgs, size_t ElementSize, + size_t DstElementSize, bool Signed) { + const auto DstSize = GetDstSize(Op); - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + const auto GetSrc = [&] { + if (Op->Src[0].IsGPR()) { + return LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], DstSize, Op->Flags, -1); + } else { + // For memory operands the 256-bit variant loads twice the size specified in the table. + const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE; + const auto SrcSize = GetSrcSize(Op); + const auto LoadSize = Is256Bit ? SrcSize * 2 : SrcSize; - OrderedNode *Result {Src}; + return LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], LoadSize, Op->Flags, -1); + } + }; + + OrderedNode *Src = GetSrc(); + OrderedNode *Result{Src}; for (size_t CurrentElementSize = ElementSize; CurrentElementSize != DstElementSize; CurrentElementSize <<= 1) { - if constexpr (Signed) { - Result = _VSXTL(Size, CurrentElementSize, Result); - } - else { - Result = _VUXTL(Size, CurrentElementSize, Result); + if (Signed) { + Result = _VSXTL(DstSize, CurrentElementSize, Result); + } else { + Result = _VUXTL(DstSize, CurrentElementSize, Result); } } + + return Result; +} + +template +void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) { + OrderedNode *Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed); StoreResult(FPRClass, Op, Result, -1); } @@ -2656,6 +2674,19 @@ void OpDispatchBuilder::ExtendVectorElements<2, 8, true>(OpcodeArgs); template void OpDispatchBuilder::ExtendVectorElements<4, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements(OpcodeArgs) { + const auto DstSize = GetDstSize(Op); + const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE; + + OrderedNode *Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed); + + if (Is128Bit) { + Result = _VMov(16, Result); + } + StoreResult(FPRClass, Op, Result, -1); +} + OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { const auto Size = GetDstSize(Op); From 6bb0c5b24cecd28b954b0c2c7a60edf5376cb8ee Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:13:03 +0000 Subject: [PATCH 02/13] OpcodeDispatcher: Handle VPMOVZXBW --- .../Interface/Core/OpcodeDispatcher.cpp | 2 ++ .../Core/OpcodeDispatcher/Vector.cpp | 3 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxbw.asm | 33 +++++++++++++++++++ 4 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxbw.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 73bdd6257..bf8f42f49 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5962,6 +5962,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, + {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, + {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x39), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index ed83ad655..dbbf00bc0 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2687,6 +2687,9 @@ void OpDispatchBuilder::AVXExtendVectorElements(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>(OpcodeArgs); + OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { const auto Size = GetDstSize(Op); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 5b36f3fb0..6ec596d10 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -305,7 +305,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x2E), 1, X86InstInfo{"VMASKMOVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x2F), 1, X86InstInfo{"VMASKMOVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxbw.asm b/unittests/ASM/VEX/vpmovzxbw.asm new file mode 100644 index 000000000..1b7ca97d1 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbw.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0085008600870088", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0085008600870088", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"], + "XMM3": ["0x0085008600870088", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0085008600870088", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbw xmm1, [rdx] +vpmovzxbw ymm2, [rdx] + +; Register only +vpmovzxbw xmm3, xmm0 +vpmovzxbw ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From 2b5570a9109bcdd26a730f064169f37ff0ae8887 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:22:03 +0000 Subject: [PATCH 03/13] OpcodeDispatcher: Handle VPMOVZXBD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxbd.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxbd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index bf8f42f49..8768dc278 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5963,6 +5963,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, + {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index dbbf00bc0..25206b262 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2689,6 +2689,8 @@ void OpDispatchBuilder::AVXExtendVectorElements(OpcodeArgs) { template void OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 6ec596d10..6562186a0 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -306,7 +306,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x2F), 1, X86InstInfo{"VMASKMOVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxbd.asm b/unittests/ASM/VEX/vpmovzxbd.asm new file mode 100644 index 000000000..f407944ef --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000008700000088", "0x0000008500000086", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000008700000088", "0x0000008500000086", "0x0000004300000044", "0x0000004100000042"], + "XMM3": ["0x0000008700000088", "0x0000008500000086", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000008700000088", "0x0000008500000086", "0x0000004300000044", "0x0000004100000042"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbd xmm1, [rdx] +vpmovzxbd ymm2, [rdx] + +; Register only +vpmovzxbd xmm3, xmm0 +vpmovzxbd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From b4079cfea30f2d8126c5c1f044ca37ce926e85d2 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:30:06 +0000 Subject: [PATCH 04/13] OpcodeDispatcher: Handle VPMOVZXBQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxbq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxbq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 8768dc278..690ca3e83 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5964,6 +5964,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, + {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 25206b262..008b8d299 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2691,6 +2691,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 6562186a0..31922f648 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -307,7 +307,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxbq.asm b/unittests/ASM/VEX/vpmovzxbq.asm new file mode 100644 index 000000000..fe57eb4f1 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxbq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000086", "0x0000000000000085"], + "XMM3": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000000000088", "0x0000000000000087", "0x0000000000000086", "0x0000000000000085"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxbq xmm1, [rdx] +vpmovzxbq ymm2, [rdx] + +; Register only +vpmovzxbq xmm3, xmm0 +vpmovzxbq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From 5c8d40d9bece002c57fdf159bcd618171049cd46 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:34:39 +0000 Subject: [PATCH 05/13] OpcodeDispatcher: Handle VPMOVZXWD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxwd.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxwd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 690ca3e83..d907433a1 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5965,6 +5965,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x30), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, false>}, {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, + {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 008b8d299..e06164279 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2693,6 +2693,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 31922f648..1f29caa48 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -308,7 +308,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x30), 1, X86InstInfo{"VPMOVZXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxwd.asm b/unittests/ASM/VEX/vpmovzxwd.asm new file mode 100644 index 000000000..ab7c038f7 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxwd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"], + "XMM3": ["0x0000858600008788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000858600008788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxwd xmm1, [rdx] +vpmovzxwd ymm2, [rdx] + +; Register only +vpmovzxwd xmm3, xmm0 +vpmovzxwd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From 2895a091017e097375492fea3f9dda622a0f254e Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:39:21 +0000 Subject: [PATCH 06/13] OpcodeDispatcher: Handle VPMOVZXWQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxwq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxwq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index d907433a1..e70939cf2 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5966,6 +5966,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x31), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, false>}, {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>}, + {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index e06164279..031686bfb 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2695,6 +2695,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 1f29caa48..c7c3e6baa 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -309,7 +309,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x31), 1, X86InstInfo{"VPMOVZXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x37), 1, X86InstInfo{"VPCMPGTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxwq.asm b/unittests/ASM/VEX/vpmovzxwq.asm new file mode 100644 index 000000000..463de4b15 --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxwq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000000008788", "0x0000000000008586", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000000008788", "0x0000000000008586", "0x0000000000004344", "0x0000000000004142"], + "XMM3": ["0x0000000000008788", "0x0000000000008586", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000000008788", "0x0000000000008586", "0x0000000000004344", "0x0000000000004142"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxwq xmm1, [rdx] +vpmovzxwq ymm2, [rdx] + +; Register only +vpmovzxwq xmm3, xmm0 +vpmovzxwq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From 588a2611a71df122b961b778c451e3740f30298d Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:43:00 +0000 Subject: [PATCH 07/13] OpcodeDispatcher: Handle VPMOVZXDQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovzxdq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovzxdq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index e70939cf2..f9796e28b 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5967,6 +5967,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x32), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, false>}, {OPD(2, 0b01, 0x33), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>}, {OPD(2, 0b01, 0x34), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>}, + {OPD(2, 0b01, 0x35), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>}, {OPD(2, 0b01, 0x37), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x38), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 031686bfb..6d497a861 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2697,6 +2697,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<2, 4, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index c7c3e6baa..2f46b466e 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -310,7 +310,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x32), 1, X86InstInfo{"VPMOVZXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x33), 1, X86InstInfo{"VPMOVZXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x34), 1, X86InstInfo{"VPMOVZXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x35), 1, X86InstInfo{"VPMOVZXDQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x36), 1, X86InstInfo{"VPERMD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x37), 1, X86InstInfo{"VPCMPGTQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovzxdq.asm b/unittests/ASM/VEX/vpmovzxdq.asm new file mode 100644 index 000000000..b81331f6a --- /dev/null +++ b/unittests/ASM/VEX/vpmovzxdq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0x0000000085868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0x0000000085868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"], + "XMM3": ["0x0000000085868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x0000000085868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovzxdq xmm1, [rdx] +vpmovzxdq ymm2, [rdx] + +; Register only +vpmovzxdq xmm3, xmm0 +vpmovzxdq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From 21537a363685c6adbad76a042c5ee2a2da19cabf Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:48:34 +0000 Subject: [PATCH 08/13] OpcodeDispatcher: Handle VPMOVSXBW --- .../Interface/Core/OpcodeDispatcher.cpp | 2 ++ .../Core/OpcodeDispatcher/Vector.cpp | 3 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxbw.asm | 33 +++++++++++++++++++ 4 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxbw.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index f9796e28b..cc0732943 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5959,6 +5959,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x1D), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, {OPD(2, 0b01, 0x1E), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, + {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, + {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 6d497a861..3702f185e 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2700,6 +2700,9 @@ void OpDispatchBuilder::AVXExtendVectorElements<2, 8, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>(OpcodeArgs); + OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { const auto Size = GetDstSize(Op); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 2f46b466e..0973e7257 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -289,7 +289,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x1D), 1, X86InstInfo{"VPABSW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x1E), 1, X86InstInfo{"VPABSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxbw.asm b/unittests/ASM/VEX/vpmovsxbw.asm new file mode 100644 index 000000000..f4b667e58 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbw.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"], + "XMM3": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFF85FF86FF87FF88", "0x0041004200430044", "0x0055005600570058", "0x0051005200530054"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbw xmm1, [rdx] +vpmovsxbw ymm2, [rdx] + +; Register only +vpmovsxbw xmm3, xmm0 +vpmovsxbw ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From d7eab5f787c272809b0995ac8ad5e6655cdedbf5 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:52:31 +0000 Subject: [PATCH 09/13] OpcodeDispatcher: Handle VPMOVSXBD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxbd.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxbd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index cc0732943..adf626d35 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5960,6 +5960,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x1E), 1, &OpDispatchBuilder::AVXVectorUnaryOp}, {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, + {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 3702f185e..d2c7d3ccb 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2702,6 +2702,8 @@ void OpDispatchBuilder::AVXExtendVectorElements<4, 8, false>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 0973e7257..d4b92e326 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -290,7 +290,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x1E), 1, X86InstInfo{"VPABSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxbd.asm b/unittests/ASM/VEX/vpmovsxbd.asm new file mode 100644 index 000000000..523d50d82 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000004300000044", "0x0000004100000042"], + "XMM3": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFF87FFFFFF88", "0xFFFFFF85FFFFFF86", "0x0000004300000044", "0x0000004100000042"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbd xmm1, [rdx] +vpmovsxbd ymm2, [rdx] + +; Register only +vpmovsxbd xmm3, xmm0 +vpmovsxbd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From ce12ed60aef54a36bd97f7cbf69bbb67a9a3bbab Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:56:09 +0000 Subject: [PATCH 10/13] OpcodeDispatcher: Handle VPMOVSXBQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxbq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxbq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index adf626d35..39f6df2e3 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5961,6 +5961,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, + {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index d2c7d3ccb..d539fc2b5 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2704,6 +2704,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index d4b92e326..affde2029 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -291,7 +291,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxbq.asm b/unittests/ASM/VEX/vpmovsxbq.asm new file mode 100644 index 000000000..423f76616 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxbq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0xFFFFFFFFFFFFFF86", "0xFFFFFFFFFFFFFF85"], + "XMM3": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFFFFFFFF88", "0xFFFFFFFFFFFFFF87", "0xFFFFFFFFFFFFFF86", "0xFFFFFFFFFFFFFF85"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxbq xmm1, [rdx] +vpmovsxbq ymm2, [rdx] + +; Register only +vpmovsxbq xmm3, xmm0 +vpmovsxbq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From cccbb7f595c274b2d7020b0b1b06844da00082ba Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 17:59:53 +0000 Subject: [PATCH 11/13] OpcodeDispatcher: Handle VPMOVSXWD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxwd.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxwd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 39f6df2e3..a9327e67e 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5962,6 +5962,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x20), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 2, true>}, {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, + {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index d539fc2b5..50909a238 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2706,6 +2706,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index affde2029..3ae366d73 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -292,7 +292,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x20), 1, X86InstInfo{"VPMOVSXBW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxwd.asm b/unittests/ASM/VEX/vpmovsxwd.asm new file mode 100644 index 000000000..a2f06c636 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxwd.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"], + "XMM3": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFF8586FFFF8788", "0x0000414200004344", "0x0000555600005758", "0x0000515200005354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxwd xmm1, [rdx] +vpmovsxwd ymm2, [rdx] + +; Register only +vpmovsxwd xmm3, xmm0 +vpmovsxwd ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From aa63c7b94d23b8d0deb3341d9bed03941a55e5e2 Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 18:02:40 +0000 Subject: [PATCH 12/13] OpcodeDispatcher: Handle VPMOVSXWQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxwq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxwq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index a9327e67e..ee096328f 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5963,6 +5963,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x21), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 4, true>}, {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>}, + {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 50909a238..18f6fc133 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2708,6 +2708,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 3ae366d73..f97c5a840 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -293,7 +293,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x21), 1, X86InstInfo{"VPMOVSXBD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x28), 1, X86InstInfo{"VPMULDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxwq.asm b/unittests/ASM/VEX/vpmovsxwq.asm new file mode 100644 index 000000000..f73f0ea5b --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxwq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000004344", "0x0000000000004142"], + "XMM3": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFFFFFF8788", "0xFFFFFFFFFFFF8586", "0x0000000000004344", "0x0000000000004142"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxwq xmm1, [rdx] +vpmovsxwq ymm2, [rdx] + +; Register only +vpmovsxwq xmm3, xmm0 +vpmovsxwq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758 From b12503fe327b973501fed6393195afcbe7888fad Mon Sep 17 00:00:00 2001 From: lioncash Date: Thu, 15 Dec 2022 18:09:01 +0000 Subject: [PATCH 13/13] OpcodeDispatcher: Handle VPMOVSXDQ --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 ++ .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vpmovsxdq.asm | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vpmovsxdq.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index ee096328f..932afd7ca 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5964,6 +5964,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x22), 1, &OpDispatchBuilder::AVXExtendVectorElements<1, 8, true>}, {OPD(2, 0b01, 0x23), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>}, {OPD(2, 0b01, 0x24), 1, &OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>}, + {OPD(2, 0b01, 0x25), 1, &OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>}, {OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 18f6fc133..46b909c0f 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2710,6 +2710,8 @@ template void OpDispatchBuilder::AVXExtendVectorElements<2, 4, true>(OpcodeArgs); template void OpDispatchBuilder::AVXExtendVectorElements<2, 8, true>(OpcodeArgs); +template +void OpDispatchBuilder::AVXExtendVectorElements<4, 8, true>(OpcodeArgs); OrderedNode* OpDispatchBuilder::VectorRoundImpl(OpcodeArgs, size_t ElementSize, OrderedNode *Src, uint64_t Mode) { diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index f97c5a840..9a668d4d5 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -294,7 +294,7 @@ void InitializeVEXTables() { {OPD(2, 0b01, 0x22), 1, X86InstInfo{"VPMOVSXBQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x23), 1, X86InstInfo{"VPMOVSXWD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x24), 1, X86InstInfo{"VPMOVSXWQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x25), 1, X86InstInfo{"VPMOVSXDQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x28), 1, X86InstInfo{"VPMULDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(2, 0b01, 0x29), 1, X86InstInfo{"VPCMPEQQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vpmovsxdq.asm b/unittests/ASM/VEX/vpmovsxdq.asm new file mode 100644 index 000000000..2cdfd6db3 --- /dev/null +++ b/unittests/ASM/VEX/vpmovsxdq.asm @@ -0,0 +1,33 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434485868788", "0x5152535455565758", "0x4142434485868788", "0x5152535455565758"], + "XMM1": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"], + "XMM3": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xFFFFFFFF85868788", "0x0000000041424344", "0x0000000055565758", "0x0000000051525354"] + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] + +; Memory operands +vpmovsxdq xmm1, [rdx] +vpmovsxdq ymm2, [rdx] + +; Register only +vpmovsxdq xmm3, xmm0 +vpmovsxdq ymm4, xmm0 + +hlt + +align 32 +.data: +dq 0x4142434485868788 +dq 0x5152535455565758 +dq 0x4142434485868788 +dq 0x5152535455565758