From dcfbd90dd7b9f83bc1ea63bae0afeae958a42f09 Mon Sep 17 00:00:00 2001 From: lioncash Date: Mon, 21 Nov 2022 20:42:24 +0000 Subject: [PATCH] OpcodeDispatcher: Handle VMOVLPS --- .../Interface/Core/OpcodeDispatcher.cpp | 3 ++ .../Source/Interface/Core/OpcodeDispatcher.h | 2 ++ .../Core/OpcodeDispatcher/Vector.cpp | 12 +++++++ .../Interface/Core/X86Tables/VEXTables.cpp | 4 +-- unittests/ASM/VEX/vmovlps.asm | 36 +++++++++++++++++++ 5 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 unittests/ASM/VEX/vmovlps.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 985b31d0e..f9ed94de0 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5694,6 +5694,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x11), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, {OPD(1, 0b01, 0x11), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op}, + {OPD(1, 0b00, 0x12), 1, &OpDispatchBuilder::VMOVLPOp}, + {OPD(1, 0b00, 0x13), 1, &OpDispatchBuilder::VMOVLPOp}, + {OPD(1, 0b00, 0x28), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, {OPD(1, 0b01, 0x28), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, {OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index b4e1087ba..56bea8cef 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -408,6 +408,8 @@ public: void VMOVAPS_VMOVAPD_Op(OpcodeArgs); void VMOVUPS_VMOVUPD_Op(OpcodeArgs); + void VMOVLPOp(OpcodeArgs); + // X87 Ops template void FLD(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7dd3ee36f..8a0a8b877 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -112,6 +112,18 @@ void OpDispatchBuilder::MOVLPOp(OpcodeArgs) { } } +void OpDispatchBuilder::VMOVLPOp(OpcodeArgs) { + if (Op->Dest.IsGPR()) { + OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 16); + OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags, 8); + OrderedNode *Result = _VInsElement(16, 8, 0, 0, Src1, Src2); + StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, 32, -1); + } else { + OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 8); + StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, 8, 8); + } +} + void OpDispatchBuilder::MOVSHDUPOp(OpcodeArgs) { OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 8); OrderedNode *Result = _VInsElement(16, 4, 3, 3, Src, Src); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index bc9eba3fb..98dd2dfa5 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -27,12 +27,12 @@ void InitializeVEXTables() { {OPD(1, 0b10, 0x11), 1, X86InstInfo{"VMOVSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x11), 1, X86InstInfo{"VMOVSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x12), 1, X86InstInfo{"VMOVLPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x12), 1, X86InstInfo{"VMOVLPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS | FLAGS_VEX_1ST_SRC, 0, nullptr}}, {OPD(1, 0b01, 0x12), 1, X86InstInfo{"VMOVLPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b10, 0x12), 1, X86InstInfo{"VMOVSLDUP", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x12), 1, X86InstInfo{"VMOVDDUP", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x13), 1, X86InstInfo{"VMOVLPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x13), 1, X86InstInfo{"VMOVLPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x13), 1, X86InstInfo{"VMOVLPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b00, 0x14), 1, X86InstInfo{"VUNPCKLPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vmovlps.asm b/unittests/ASM/VEX/vmovlps.asm new file mode 100644 index 000000000..53b185561 --- /dev/null +++ b/unittests/ASM/VEX/vmovlps.asm @@ -0,0 +1,36 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM1": ["0xEEEEEEEEEEEEEEEE", "0xDDDDDDDDDDDDDDDD", "0x0000000000000000", "0x0000000000000000"], + "XMM2": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF"], + "XMM3": ["0xFFFFFFFFFFFFFFFF", "0xDDDDDDDDDDDDDDDD", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0xCCCCCCCCCCCCCCCC", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"] + } +} +%endif + +lea rdx, [rel .data] + +;; Register as DST tests +; Load inputs +vmovapd ymm1, [rdx] +vmovapd ymm2, [rdx + 32] + +vmovlps xmm1, xmm2, [rdx + 48] +vmovlps xmm3, xmm1, [rdx + 56] + +;; Store to memory test +; Overwrite beginning of data, then yank it back into a vector +; Nothing in memory should be modified except the first 64 bits. +vmovlps [rdx], xmm2 +vmovapd ymm4, [rdx] + +hlt + +align 32 +.data: +db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF +db 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD +db 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF