From a216ea465c1660283baedc409a3dc65965f9d48d Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sun, 27 Aug 2023 01:41:06 -0700
Subject: [PATCH] InstCountCI: Test rorx at max mask size

Just to ensure we capture the nop nature of passing in the rotate amount
of the operating size.
---
 unittests/InstructionCountCI/VEX_map3.json | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index d612efd29..31503fa67 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -5118,6 +5118,17 @@
         "ror w4, w20, #31"
       ]
     },
+    "rorx eax, ebx, 32": {
+      "ExpectedInstructionCount": 2,
+      "Optimal": "No",
+      "Comment": [
+        "Map 3 0b11 0xf0 32-bit"
+      ],
+      "ExpectedArm64ASM": [
+        "ubfx x20, x7, #0, #32",
+        "ror w4, w20, #0"
+      ]
+    },
     "rorx rax, rbx, 0": {
       "ExpectedInstructionCount": 1,
       "Optimal": "Yes",
@@ -5137,6 +5148,16 @@
       "ExpectedArm64ASM": [
         "ror x4, x7, #63"
       ]
+    },
+    "rorx rax, rbx, 64": {
+      "ExpectedInstructionCount": 1,
+      "Optimal": "No",
+      "Comment": [
+        "Map 3 0b11 0xf0 64-bit"
+      ],
+      "ExpectedArm64ASM": [
+        "ror x4, x7, #0"
+      ]
     }
   }
 }