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OpcodeDispatcher: Handle VMOVAPS

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lioncash committed 2022-11-15 19:57:05 +00:00
1 parent 580f06fe00
commit ecf82c90ee
6 files changed
+95 -2
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+3
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@@ -6986,6 +6986,9 @@ constexpr uint16_t PF_F2 = 3;
#define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> VEXTable[] = {
{OPD(1, 0b00, 0x28), 1, &OpDispatchBuilder::VMOVAPSOp},
{OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::VMOVAPSOp},
{OPD(1, 0b01, 0x6E), 2, &OpDispatchBuilder::UnimplementedOp},
{OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::UnimplementedOp},
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
Vendored
+3
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@@ -404,6 +404,9 @@ public:
// ADX Ops
void ADXOp(OpcodeArgs);
// AVX Ops
void VMOVAPSOp(OpcodeArgs);
// X87 Ops
template<size_t width>
void FLD(OpcodeArgs);
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
Vendored
+12
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@@ -38,6 +38,18 @@ void OpDispatchBuilder::MOVAPSOp(OpcodeArgs) {
StoreResult(FPRClass, Op, Src, -1);
}
void OpDispatchBuilder::VMOVAPSOp(OpcodeArgs) {
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
const auto Is128BitDest = GetDstSize(Op) == Core::CPUState::XMM_SSE_REG_SIZE;
if (Op->Dest.IsGPR() && Is128BitDest) {
// Perform 32 byte store to clear the upper lane.
StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, 32, -1);
} else {
StoreResult(FPRClass, Op, Src, -1);
}
}
void OpDispatchBuilder::MOVUPSOp(OpcodeArgs) {
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 1);
StoreResult(FPRClass, Op, Src, 1);
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
Vendored
+2 -2
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@@ -112,10 +112,10 @@ void InitializeVEXTables() {
// This table doesn't state which VEX.pp is for which instruction
// XXX: Confirm all the above encoding opcodes
{OPD(1, 0b00, 0x28), 1, X86InstInfo{"VMOVAPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x28), 1, X86InstInfo{"VMOVAPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x28), 1, X86InstInfo{"VMOVAPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x29), 1, X86InstInfo{"VMOVAPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x29), 1, X86InstInfo{"VMOVAPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x29), 1, X86InstInfo{"VMOVAPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b10, 0x2A), 1, X86InstInfo{"VCVTSI2SS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},