From f8e3571c660be048fbc92db5b973f42e8b6800d8 Mon Sep 17 00:00:00 2001 From: Simon Scherer Date: Wed, 5 Aug 2026 13:20:28 +0200 Subject: [PATCH] JIT: Skip redundant rounding in Vector_F64ToI32 --- FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp b/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp index c25b5c49d..03cc9af41 100644 --- a/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp @@ -558,16 +558,18 @@ DEF_OP(Vector_F64ToI32) { } } else { ///< Round float to integral depending on rounding mode. + ///< skip TowardsZero as fcvtzs below already truncates toward zero on its own + auto CVTReg = Dst.Q(); switch (Round) { case IR::RoundMode::Nearest: frintn(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break; case IR::RoundMode::NegInfinity: frintm(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break; case IR::RoundMode::PosInfinity: frintp(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break; - case IR::RoundMode::TowardsZero: frintz(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break; + case IR::RoundMode::TowardsZero: CVTReg = Vector.Q(); break; case IR::RoundMode::Host: frinti(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break; } ///< Convert f64 directly to i64 - fcvtzs(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Dst.Q()); + fcvtzs(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), CVTReg); ///< Saturating narrow i64 -> i32 ///