From 39392133364a3366967379aa5158271362afa8ed Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 24 Mar 2025 12:40:16 -0400 Subject: [PATCH 1/2] RegisterAllocationPass: rm useless assertion Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp index 61f735296..0ac2d7328 100644 --- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp +++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp @@ -260,7 +260,6 @@ private: Class = Op->Class; Reg = Op->Reg; } else if (IROp->Op == OP_STOREREGISTER) { - LOGMAN_THROW_A_FMT(IROp->Op == OP_STOREREGISTER, "node is SRA"); const IROp_StoreRegister* Op = IROp->C(); Class = Op->Class; From 9f399f331385c0a1110adf9295401f1b300b2dc8 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 24 Mar 2025 15:41:58 -0400 Subject: [PATCH 2/2] RegisterAllocationPass: rm unused arg to DecodeSRAReg Signed-off-by: Alyssa Rosenzweig --- .../Source/Interface/IR/Passes/RegisterAllocationPass.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp index 0ac2d7328..b2547e20d 100644 --- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp +++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp @@ -248,7 +248,7 @@ private: return nullptr; }; - PhysicalRegister DecodeSRAReg(const IROp_Header* IROp, Ref Node) { + PhysicalRegister DecodeSRAReg(const IROp_Header* IROp) { RegisterClassType Class {}; uint8_t Reg {}; @@ -519,7 +519,7 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) { // each register, used below. Since we initialized Class->Available, // RegToSSA is otherwise undefined so we can stash our temps there. if (auto Node = DecodeSRANode(IROp, CodeNode); Node != nullptr) { - auto Reg = DecodeSRAReg(IROp, Node); + auto Reg = DecodeSRAReg(IROp); PreferredReg[IR->GetID(Node).Value] = Reg; GetClass(Reg)->RegToSSA[Reg.Reg] = CodeNode; @@ -566,7 +566,7 @@ void ConstrainedRAPass::Run(IREmitter* IREmit_) { // Static registers must be consistent at SRA load/store. Evict to ensure. if (auto Node = DecodeSRANode(IROp, CodeNode); Node != nullptr) { - auto Reg = DecodeSRAReg(IROp, Node); + auto Reg = DecodeSRAReg(IROp); RegisterClass* Class = &Classes[Reg.Class]; if (!(Class->Available & (1u << Reg.Reg))) {