diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 91691f563..440b41bd0 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -21,6 +21,13 @@ "This lowers throughput from 1 IPC to 1/2IPC", "This instruction implementation might not be correct.", "0x0f 0x0f 0x0c" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "mov v4.h[1], v4.h[2]", + "sxtl v4.4s, v4.4h", + "scvtf v4.4s, v4.4s", + "str d4, [x28, #752]" ] }, "pi2fd mm0, mm1": { @@ -30,6 +37,11 @@ "FPConvert instruction using 128-bit conversion instead of 64-bit.", "This lowers throughput from 1 IPC to 1/2IPC", "0x0f 0x0f 0x0d" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "scvtf v4.4s, v4.4s", + "str d4, [x28, #752]" ] }, "pf2iw mm0, mm1": { @@ -40,6 +52,13 @@ "This lowers throughput from 1 IPC to 1/2IPC", "This instruction implementation might not be correct.", "0x0f 0x0f 0x1c" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fcvtzs v4.4s, v4.4s", + "mov v4.h[1], v4.h[2]", + "sxtl v4.4s, v4.4h", + "str d4, [x28, #752]" ] }, "pf2id mm0, mm1": { @@ -49,6 +68,11 @@ "FPConvert instruction using 128-bit conversion instead of 64-bit.", "This lowers throughput from 1 IPC to 1/2IPC", "0x0f 0x0f 0x1d" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" ] }, "pfrcpv mm0, mm1": { @@ -57,6 +81,12 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x0f 0x86" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fmov v0.4s, #0x70 (1.0000)", + "fdiv v4.4s, v0.4s, v4.4s", + "str d4, [x28, #752]" ] }, "pfrsqrtv mm0, mm1": { @@ -65,27 +95,68 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x0f 0x87" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fmov v0.4s, #0x70 (1.0000)", + "fsqrt v1.4s, v4.4s", + "fdiv v4.4s, v0.4s, v1.4s", + "str d4, [x28, #752]" ] }, "pfnacc mm0, mm1": { "ExpectedInstructionCount": 8, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0x8a" + "Comment": "0x0f 0x0f 0x8a", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "dup v6.4s, v4.s[1]", + "dup v7.4s, v5.s[1]", + "fsub s4, s4, s6", + "fsub s5, s5, s7", + "mov v4.s[1], v5.s[0]", + "str d4, [x28, #752]" + ] }, "pfpnacc mm0, mm1": { "ExpectedInstructionCount": 7, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0x8e" + "Comment": "0x0f 0x0f 0x8e", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "dup v6.4s, v4.s[1]", + "fsub s4, s4, s6", + "faddp v5.4s, v5.4s, v5.4s", + "mov v4.s[1], v5.s[0]", + "str d4, [x28, #752]" + ] }, "pfcmpge mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0x90" + "Comment": "0x0f 0x0f 0x90", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fcmge v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfmin mm0, mm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x0f 0x94" + "Comment": "0x0f 0x0f 0x94", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fcmgt v0.4s, v4.4s, v5.4s", + "mov v1.16b, v5.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "str d4, [x28, #752]" + ] }, "pfrcp mm0, mm1": { "ExpectedInstructionCount": 5, @@ -93,6 +164,13 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x0f 0x96" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fmov s0, #0x70 (1.0000)", + "fdiv s4, s0, s4", + "dup v4.4s, v4.s[0]", + "str d4, [x28, #752]" ] }, "pfrsqrt mm0, mm1": { @@ -101,72 +179,149 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x0f 0x97" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s4", + "fdiv s4, s0, s1", + "dup v4.4s, v4.s[0]", + "str d4, [x28, #752]" ] }, "pfsub mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0x9a" + "Comment": "0x0f 0x0f 0x9a", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fsub v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfadd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0x9e" + "Comment": "0x0f 0x0f 0x9e", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fadd v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfcmpgt mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xa0" + "Comment": "0x0f 0x0f 0xa0", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fcmgt v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfmax mm0, mm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x0f 0xa4" + "Comment": "0x0f 0x0f 0xa4", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fcmgt v0.4s, v4.4s, v5.4s", + "mov v1.16b, v5.16b", + "bit v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "str d4, [x28, #752]" + ] }, "pfrcpit1 mm0, mm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xa6" + "Comment": "0x0f 0x0f 0xa6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "str d4, [x28, #752]" + ] }, "pfrcpit1 mm0, mm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x0f 0xa6" + "Comment": "0x0f 0x0f 0xa6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "pfrsqit1 mm0, mm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xa7" + "Comment": "0x0f 0x0f 0xa7", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "str d4, [x28, #752]" + ] }, "pfrsqit1 mm0, mm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x0f 0xa7" + "Comment": "0x0f 0x0f 0xa7", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "pfsubr mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xaa" + "Comment": "0x0f 0x0f 0xaa", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fsub v4.4s, v4.4s, v5.4s", + "str d4, [x28, #752]" + ] }, "pfcmpeq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xb0" + "Comment": "0x0f 0x0f 0xb0", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fcmeq v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfmul mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xb4" + "Comment": "0x0f 0x0f 0xb4", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "fmul v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "pfrcpit2 mm0, mm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xb6" + "Comment": "0x0f 0x0f 0xb6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "str d4, [x28, #752]" + ] }, "pfrcpit2 mm0, mm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x0f 0xb6" + "Comment": "0x0f 0x0f 0xb6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "db 0x0f, 0x0f, 0xc1, 0xb7": { "ExpectedInstructionCount": 8, @@ -176,17 +331,38 @@ "pmulhrw mm0, mm1", "Might be able to use sqdmulh", "0x0f 0x0f 0xb7" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "smull v4.4s, v4.4h, v5.4h", + "mov x20, #0x800000008000", + "dup v5.2d, x20", + "add v4.4s, v4.4s, v5.4s", + "shrn v4.4h, v4.4s, #16", + "str d4, [x28, #752]" ] }, "pswapd mm0, mm1": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xbb" + "Comment": "0x0f 0x0f 0xbb", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "rev64 v4.2s, v4.2s", + "str d4, [x28, #752]" + ] }, "pavgusb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x0f 0xbf" + "Comment": "0x0f 0x0f 0xbf", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "urhadd v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 7ad8f9959..38f434af1 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -13,6 +13,14 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x00" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "movi v6.16b, #0x87", + "and v5.16b, v5.16b, v6.16b", + "tbl v4.8b, {v4.16b}, v5.8b", + "str d4, [x28, #752]" ] }, "pshufb xmm0, xmm1": { @@ -20,6 +28,11 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x00" + ], + "ExpectedArm64ASM": [ + "movi v4.16b, #0x8f", + "and v4.16b, v17.16b, v4.16b", + "tbl v16.16b, {v16.16b}, v4.16b" ] }, "phaddw mm0, mm1": { @@ -27,6 +40,12 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x01" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "addp v4.4h, v5.4h, v4.4h", + "str d4, [x28, #752]" ] }, "phaddw xmm0, xmm1": { @@ -34,6 +53,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x01" + ], + "ExpectedArm64ASM": [ + "addp v16.8h, v16.8h, v17.8h" ] }, "phaddd mm0, mm1": { @@ -41,6 +63,12 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x02" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "addp v4.2s, v5.2s, v4.2s", + "str d4, [x28, #752]" ] }, "phaddd xmm0, xmm1": { @@ -48,6 +76,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x02" + ], + "ExpectedArm64ASM": [ + "addp v16.4s, v16.4s, v17.4s" ] }, "phaddsw mm0, mm1": { @@ -55,6 +86,14 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x03" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "uzp1 v6.4h, v4.4h, v5.4h", + "uzp2 v4.4h, v4.4h, v5.4h", + "sqadd v4.8h, v6.8h, v4.8h", + "str d4, [x28, #752]" ] }, "phaddsw xmm0, xmm1": { @@ -62,6 +101,11 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x03" + ], + "ExpectedArm64ASM": [ + "uzp1 v4.8h, v16.8h, v17.8h", + "uzp2 v5.8h, v16.8h, v17.8h", + "sqadd v16.8h, v4.8h, v5.8h" ] }, "pmaddubsw mm0, mm1": { @@ -69,6 +113,17 @@ "Optimal": "Unknown", "Comment": [ "NP 0x0f 0x38 0x04" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "uxtl v4.8h, v4.8b", + "sxtl v5.8h, v5.8b", + "smull v6.4s, v4.4h, v5.4h", + "smull2 v4.4s, v4.8h, v5.8h", + "addp v4.4s, v6.4s, v4.4s", + "sqxtn v4.4h, v4.4s", + "str d4, [x28, #752]" ] }, "pmaddubsw xmm0, xmm1": { @@ -76,6 +131,22 @@ "Optimal": "Unknown", "Comment": [ "0x66 0x0f 0x38 0x04" + ], + "ExpectedArm64ASM": [ + "uxtl v4.8h, v16.8b", + "uxtl2 v5.8h, v16.16b", + "sxtl v6.8h, v17.8b", + "sxtl2 v7.8h, v17.16b", + "smull v8.4s, v4.4h, v6.4h", + "smull2 v4.4s, v4.8h, v6.8h", + "smull v6.4s, v5.4h, v7.4h", + "smull2 v5.4s, v5.8h, v7.8h", + "addp v4.4s, v8.4s, v4.4s", + "addp v5.4s, v6.4s, v5.4s", + "sqxtn v4.4h, v4.4s", + "mov v0.16b, v4.16b", + "sqxtn2 v0.8h, v5.4s", + "mov v16.16b, v0.16b" ] }, "phsubw mm0, mm1": { @@ -84,6 +155,20 @@ "Comment": [ "Should be able to be optimized like phsubsw", "NP 0x0f 0x38 0x05" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "neg v6.8h, v4.8h", + "neg v7.8h, v5.8h", + "uzp1 v4.4h, v4.4h, v4.4h", + "uzp1 v5.4h, v5.4h, v5.4h", + "uzp2 v6.4h, v6.4h, v6.4h", + "uzp2 v7.4h, v7.4h, v7.4h", + "zip1 v4.4h, v4.4h, v6.4h", + "zip1 v5.4h, v5.4h, v7.4h", + "addp v4.4h, v4.4h, v5.4h", + "str d4, [x28, #752]" ] }, "phsubw xmm0, xmm1": { @@ -92,6 +177,17 @@ "Comment": [ "Should be able to be optimized like phsubsw", "0x66 0x0f 0x38 0x05" + ], + "ExpectedArm64ASM": [ + "neg v4.8h, v16.8h", + "neg v5.8h, v17.8h", + "uzp1 v6.8h, v16.8h, v16.8h", + "uzp1 v7.8h, v17.8h, v17.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "uzp2 v5.8h, v5.8h, v5.8h", + "zip1 v4.8h, v6.8h, v4.8h", + "zip1 v5.8h, v7.8h, v5.8h", + "addp v16.8h, v4.8h, v5.8h" ] }, "phsubd mm0, mm1": { @@ -100,6 +196,16 @@ "Comment": [ "Should be able to be optimized like phsubsw", "NP 0x0f 0x38 0x06" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "neg v6.4s, v4.4s", + "neg v7.4s, v5.4s", + "mov v4.s[1], v6.s[1]", + "mov v5.s[1], v7.s[1]", + "addp v4.2s, v4.2s, v5.2s", + "str d4, [x28, #752]" ] }, "phsubd xmm0, xmm1": { @@ -108,6 +214,17 @@ "Comment": [ "Should be able to be optimized like phsubsw", "0x66 0x0f 0x38 0x06" + ], + "ExpectedArm64ASM": [ + "neg v4.4s, v16.4s", + "neg v5.4s, v17.4s", + "uzp1 v6.4s, v16.4s, v16.4s", + "uzp1 v7.4s, v17.4s, v17.4s", + "uzp2 v4.4s, v4.4s, v4.4s", + "uzp2 v5.4s, v5.4s, v5.4s", + "zip1 v4.4s, v6.4s, v4.4s", + "zip1 v5.4s, v7.4s, v5.4s", + "addp v16.4s, v4.4s, v5.4s" ] }, "phsubsw mm0, mm1": { @@ -115,6 +232,14 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x07" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "uzp1 v6.4h, v4.4h, v5.4h", + "uzp2 v4.4h, v4.4h, v5.4h", + "sqsub v4.8h, v6.8h, v4.8h", + "str d4, [x28, #752]" ] }, "phsubsw xmm0, xmm1": { @@ -122,6 +247,11 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x07" + ], + "ExpectedArm64ASM": [ + "uzp1 v4.8h, v16.8h, v17.8h", + "uzp2 v5.8h, v16.8h, v17.8h", + "sqsub v16.8h, v4.8h, v5.8h" ] }, "psignb mm0, mm1": { @@ -129,6 +259,21 @@ "Optimal": "Unknown", "Comment": [ "NP 0x0f 0x38 0x08" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "movi d6, #0x0", + "neg v7.16b, v5.16b", + "cmlt v8.16b, v4.16b, #0", + "cmeq v9.16b, v4.16b, #0", + "cmgt v4.16b, v4.16b, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "str d4, [x28, #752]" ] }, "psignb xmm0, xmm1": { @@ -136,6 +281,18 @@ "Optimal": "Unknown", "Comment": [ "0x66 0x0f 0x38 0x08" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "neg v5.16b, v16.16b", + "cmlt v6.16b, v17.16b, #0", + "cmeq v7.16b, v17.16b, #0", + "cmgt v8.16b, v17.16b, #0", + "and v5.16b, v6.16b, v5.16b", + "and v4.16b, v7.16b, v4.16b", + "and v6.16b, v8.16b, v16.16b", + "orr v4.16b, v5.16b, v4.16b", + "orr v16.16b, v6.16b, v4.16b" ] }, "psignw mm0, mm1": { @@ -143,6 +300,21 @@ "Optimal": "Unknown", "Comment": [ "NP 0x0f 0x38 0x09" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "movi d6, #0x0", + "neg v7.8h, v5.8h", + "cmlt v8.8h, v4.8h, #0", + "cmeq v9.8h, v4.8h, #0", + "cmgt v4.8h, v4.8h, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "str d4, [x28, #752]" ] }, "psignw xmm0, xmm1": { @@ -150,6 +322,18 @@ "Optimal": "Unknown", "Comment": [ "0x66 0x0f 0x38 0x09" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "neg v5.8h, v16.8h", + "cmlt v6.8h, v17.8h, #0", + "cmeq v7.8h, v17.8h, #0", + "cmgt v8.8h, v17.8h, #0", + "and v5.16b, v6.16b, v5.16b", + "and v4.16b, v7.16b, v4.16b", + "and v6.16b, v8.16b, v16.16b", + "orr v4.16b, v5.16b, v4.16b", + "orr v16.16b, v6.16b, v4.16b" ] }, "psignd mm0, mm1": { @@ -157,6 +341,21 @@ "Optimal": "Unknown", "Comment": [ "NP 0x0f 0x38 0x0a" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "movi d6, #0x0", + "neg v7.4s, v5.4s", + "cmlt v8.4s, v4.4s, #0", + "cmeq v9.4s, v4.4s, #0", + "cmgt v4.4s, v4.4s, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v4.16b, v5.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "str d4, [x28, #752]" ] }, "psignd xmm0, xmm1": { @@ -164,6 +363,18 @@ "Optimal": "Unknown", "Comment": [ "0x66 0x0f 0x38 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "neg v5.4s, v16.4s", + "cmlt v6.4s, v17.4s, #0", + "cmeq v7.4s, v17.4s, #0", + "cmgt v8.4s, v17.4s, #0", + "and v5.16b, v6.16b, v5.16b", + "and v4.16b, v7.16b, v4.16b", + "and v6.16b, v8.16b, v16.16b", + "orr v4.16b, v5.16b, v4.16b", + "orr v16.16b, v6.16b, v4.16b" ] }, "pmulhrsw mm0, mm1": { @@ -172,6 +383,16 @@ "Comment": [ "Might be able to use sqdmulh", "NP 0x0f 0x38 0x0b" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "smull v4.4s, v4.4h, v5.4h", + "sshr v4.4s, v4.4s, #14", + "movi v5.4s, #0x1, lsl #0", + "add v4.4s, v4.4s, v5.4s", + "shrn v4.4h, v4.4s, #1", + "str d4, [x28, #752]" ] }, "pmulhrsw xmm0, xmm1": { @@ -180,6 +401,19 @@ "Comment": [ "Might be able to use sqdmulh", "0x66 0x0f 0x38 0x0b" + ], + "ExpectedArm64ASM": [ + "smull v4.4s, v16.4h, v17.4h", + "smull2 v5.4s, v16.8h, v17.8h", + "sshr v4.4s, v4.4s, #14", + "sshr v5.4s, v5.4s, #14", + "movi v6.4s, #0x1, lsl #0", + "add v4.4s, v4.4s, v6.4s", + "add v5.4s, v5.4s, v6.4s", + "shrn v4.4h, v4.4s, #1", + "mov v0.16b, v4.16b", + "shrn2 v0.8h, v5.4s, #1", + "mov v16.16b, v0.16b" ] }, "pblendvb xmm0, xmm1": { @@ -187,6 +421,13 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0x10" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "sshr v5.16b, v16.16b, #7", + "mov v0.16b, v5.16b", + "bsl v0.16b, v17.16b, v4.16b", + "mov v16.16b, v0.16b" ] }, "blendvps xmm0, xmm1": { @@ -194,6 +435,13 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0x14" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "sshr v5.4s, v16.4s, #31", + "mov v0.16b, v5.16b", + "bsl v0.16b, v17.16b, v4.16b", + "mov v16.16b, v0.16b" ] }, "blendvpd xmm0, xmm1": { @@ -201,6 +449,13 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0x15" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "sshr v5.2d, v16.2d, #63", + "mov v0.16b, v5.16b", + "bsl v0.16b, v17.16b, v4.16b", + "mov v16.16b, v0.16b" ] }, "ptest xmm0, xmm1": { @@ -208,6 +463,31 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0x17" + ], + "ExpectedArm64ASM": [ + "and v4.16b, v16.16b, v17.16b", + "bic v5.16b, v17.16b, v16.16b", + "cnt v4.16b, v4.16b", + "cnt v5.16b, v5.16b", + "addv h4, v4.8h", + "addv h5, v5.8h", + "umov w20, v4.h[0]", + "umov w21, v5.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "pabsb mm0, mm1": { @@ -215,6 +495,11 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x1c" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "abs v4.16b, v4.16b", + "str d4, [x28, #752]" ] }, "pabsb xmm0, xmm1": { @@ -222,6 +507,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x1c" + ], + "ExpectedArm64ASM": [ + "abs v16.16b, v17.16b" ] }, "pabsw mm0, mm1": { @@ -229,6 +517,11 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x1d" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "abs v4.8h, v4.8h", + "str d4, [x28, #752]" ] }, "pabsw xmm0, xmm1": { @@ -236,6 +529,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x1d" + ], + "ExpectedArm64ASM": [ + "abs v16.8h, v17.8h" ] }, "pabsd mm0, mm1": { @@ -243,6 +539,11 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x38 0x1e" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "abs v4.4s, v4.4s", + "str d4, [x28, #752]" ] }, "pabsd xmm0, xmm1": { @@ -250,6 +551,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x1e" + ], + "ExpectedArm64ASM": [ + "abs v16.4s, v17.4s" ] }, "pmovzxbw xmm0, xmm1": { @@ -257,6 +561,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x30" + ], + "ExpectedArm64ASM": [ + "uxtl v16.8h, v17.8b" ] }, "pmovzxbd xmm0, xmm1": { @@ -264,6 +571,10 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x31" + ], + "ExpectedArm64ASM": [ + "uxtl v4.8h, v17.8b", + "uxtl v16.4s, v4.4h" ] }, "pmovzxbq xmm0, xmm1": { @@ -271,6 +582,11 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x32" + ], + "ExpectedArm64ASM": [ + "uxtl v4.8h, v17.8b", + "uxtl v4.4s, v4.4h", + "uxtl v16.2d, v4.2s" ] }, "pmovzxwd xmm0, xmm1": { @@ -278,6 +594,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x33" + ], + "ExpectedArm64ASM": [ + "uxtl v16.4s, v17.4h" ] }, "pmovzxwq xmm0, xmm1": { @@ -285,6 +604,10 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x34" + ], + "ExpectedArm64ASM": [ + "uxtl v4.4s, v17.4h", + "uxtl v16.2d, v4.2s" ] }, "pmovzxdq xmm0, xmm1": { @@ -292,6 +615,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x35" + ], + "ExpectedArm64ASM": [ + "uxtl v16.2d, v17.2s" ] }, "pcmpgtq xmm0, xmm1": { @@ -299,6 +625,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x37" + ], + "ExpectedArm64ASM": [ + "cmgt v16.2d, v16.2d, v17.2d" ] }, "pminsb xmm0, xmm1": { @@ -306,6 +635,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x38" + ], + "ExpectedArm64ASM": [ + "smin v16.16b, v16.16b, v17.16b" ] }, "pminsd xmm0, xmm1": { @@ -313,6 +645,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x39" + ], + "ExpectedArm64ASM": [ + "smin v16.4s, v16.4s, v17.4s" ] }, "pminuw xmm0, xmm1": { @@ -320,6 +655,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3a" + ], + "ExpectedArm64ASM": [ + "umin v16.8h, v16.8h, v17.8h" ] }, "pminud xmm0, xmm1": { @@ -327,6 +665,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3b" + ], + "ExpectedArm64ASM": [ + "umin v16.4s, v16.4s, v17.4s" ] }, "pmaxsb xmm0, xmm1": { @@ -334,6 +675,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3c" + ], + "ExpectedArm64ASM": [ + "smax v16.16b, v16.16b, v17.16b" ] }, "pmaxsd xmm0, xmm1": { @@ -341,6 +685,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3d" + ], + "ExpectedArm64ASM": [ + "smax v16.4s, v16.4s, v17.4s" ] }, "pmaxuw xmm0, xmm1": { @@ -348,6 +695,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3e" + ], + "ExpectedArm64ASM": [ + "umax v16.8h, v16.8h, v17.8h" ] }, "pmaxud xmm0, xmm1": { @@ -355,6 +705,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x3f" + ], + "ExpectedArm64ASM": [ + "umax v16.4s, v16.4s, v17.4s" ] }, "pmulld xmm0, xmm1": { @@ -362,6 +715,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0x40" + ], + "ExpectedArm64ASM": [ + "mul v16.4s, v16.4s, v17.4s" ] }, "phminposuw xmm0, xmm1": { @@ -369,6 +725,45 @@ "Optimal": "Unknown", "Comment": [ "0x66 0x0f 0x38 0x41" + ], + "ExpectedArm64ASM": [ + "uminv h4, v17.8h", + "mov w20, #0x0", + "orr w20, wzr, #0x1", + "orr w21, wzr, #0x2", + "orr w22, wzr, #0x3", + "orr w23, wzr, #0x4", + "mov w24, #0x5", + "orr w25, wzr, #0x6", + "orr w26, wzr, #0x7", + "umov w27, v4.h[0]", + "umov w30, v17.h[7]", + "cmp w30, w27", + "csel x26, x26, x26, eq", + "umov w30, v17.h[6]", + "cmp w30, w27", + "csel x25, x25, x26, eq", + "umov w26, v17.h[5]", + "cmp w26, w27", + "csel x24, x24, x25, eq", + "umov w25, v17.h[4]", + "cmp w25, w27", + "csel x23, x23, x24, eq", + "umov w24, v17.h[3]", + "cmp w24, w27", + "csel x22, x22, x23, eq", + "umov w23, v17.h[2]", + "cmp w23, w27", + "csel x21, x21, x22, eq", + "umov w22, v17.h[1]", + "cmp w22, w27", + "csel x20, x20, x21, eq", + "umov w21, v17.h[0]", + "mov w22, #0x0", + "cmp w21, w27", + "csel x20, x22, x20, eq", + "mov v16.16b, v4.16b", + "mov v16.h[1], w20" ] }, "sha1nexte xmm0, xmm1": { @@ -376,6 +771,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xc8" + ], + "ExpectedArm64ASM": [ + "mov w20, v16.s[3]", + "ror w20, w20, #2", + "mov w21, v17.s[3]", + "add w20, w21, w20", + "mov v16.16b, v17.16b", + "mov v16.s[3], w20" ] }, "sha1msg1 xmm0, xmm1": { @@ -383,6 +786,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xc9" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[3], v16.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v16.s[0]", + "mov v4.s[1], v17.s[3]", + "mov v4.s[0], v17.s[2]", + "eor v16.16b, v16.16b, v4.16b" ] }, "sha1msg2 xmm0, xmm1": { @@ -390,6 +802,31 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xca" + ], + "ExpectedArm64ASM": [ + "mov w20, v17.s[2]", + "mov w21, v17.s[1]", + "mov w22, v17.s[0]", + "mov w23, v16.s[3]", + "eor w20, w23, w20", + "ror w20, w20, #31", + "mov w23, v16.s[2]", + "eor w21, w23, w21", + "ror w21, w21, #31", + "mov w23, v16.s[1]", + "eor w22, w23, w22", + "ror w22, w22, #31", + "mov w23, v16.s[0]", + "eor w23, w23, w20", + "ror w23, w23, #31", + "mov v4.16b, v16.16b", + "mov v4.s[3], w20", + "mov v4.16b, v4.16b", + "mov v4.s[2], w21", + "mov v4.16b, v4.16b", + "mov v4.s[1], w22", + "mov v16.16b, v4.16b", + "mov v16.s[0], w23" ] }, "sha256rnds2 xmm0, xmm1": { @@ -397,6 +834,117 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xcb" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0x120 (288)", + "mov v4.16b, v16.16b", + "mov w20, v17.s[3]", + "mov w21, v17.s[2]", + "mov w22, v4.s[3]", + "mov w23, v4.s[2]", + "str w23, [sp]", + "mov w23, v17.s[1]", + "mov w24, v17.s[0]", + "mov w25, v4.s[1]", + "mov w26, v4.s[0]", + "mov w27, v16.s[0]", + "mov w30, v16.s[1]", + "str w30, [sp, #32]", + "and w30, w23, w24", + "str w24, [sp, #64]", + "bic w24, w25, w23", + "str w25, [sp, #96]", + "eor w24, w30, w24", + "ror w25, w23, #6", + "ror w30, w23, #11", + "eor w25, w25, w30", + "ror w30, w23, #25", + "eor w25, w25, w30", + "add w24, w24, w25", + "add w24, w24, w27", + "add w24, w24, w26", + "and w25, w20, w21", + "and w30, w20, w22", + "eor w25, w25, w30", + "and w30, w21, w22", + "str w21, [sp, #160]", + "str w22, [sp, #128]", + "eor w21, w25, w30", + "add w21, w24, w21", + "ror w22, w20, #2", + "ror w24, w20, #13", + "eor w22, w22, w24", + "ror w24, w20, #22", + "eor w22, w22, w24", + "add w21, w21, w22", + "str w21, [sp, #192]", + "ldr w21, [sp, #64]", + "and w22, w23, w21", + "ldr w24, [sp, #96]", + "bic w25, w24, w23", + "eor w22, w22, w25", + "ror w25, w23, #6", + "ror w30, w23, #11", + "eor w25, w25, w30", + "ror w30, w23, #25", + "eor w25, w25, w30", + "add w22, w22, w25", + "add w22, w22, w27", + "add w22, w22, w26", + "ldr w25, [sp]", + "add w22, w22, w25", + "and w25, w22, w23", + "bic w26, w21, w22", + "eor w25, w25, w26", + "ror w26, w22, #6", + "ror w27, w22, #11", + "eor w26, w26, w27", + "ror w27, w22, #25", + "eor w26, w26, w27", + "add w25, w25, w26", + "ldr w26, [sp, #32]", + "add w25, w25, w26", + "str w26, [sp, #256]", + "add w25, w25, w24", + "str w24, [sp, #224]", + "ldr w24, [sp, #192]", + "and w26, w24, w20", + "ldr w27, [sp, #160]", + "and w30, w24, w27", + "eor w26, w26, w30", + "and w20, w20, w27", + "eor w20, w26, w20", + "add w20, w25, w20", + "ror w25, w24, #2", + "ror w26, w24, #13", + "eor w25, w25, w26", + "ror w26, w24, #22", + "eor w25, w25, w26", + "add w20, w20, w25", + "and w23, w22, w23", + "bic w21, w21, w22", + "eor w21, w23, w21", + "ror w23, w22, #6", + "ror w25, w22, #11", + "eor w23, w23, w25", + "ror w25, w22, #25", + "eor w23, w23, w25", + "add w21, w21, w23", + "ldr w23, [sp, #256]", + "add w21, w21, w23", + "ldr w23, [sp, #224]", + "add w21, w21, w23", + "ldr w23, [sp, #128]", + "add w21, w21, w23", + "mov v4.16b, v4.16b", + "mov v4.s[3], w20", + "mov v4.16b, v4.16b", + "mov v4.s[2], w24", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w22", + "add sp, sp, #0x120 (288)" ] }, "sha256msg1 xmm0, xmm1": { @@ -404,6 +952,45 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xcc" + ], + "ExpectedArm64ASM": [ + "mov w20, v17.s[0]", + "mov w21, v16.s[3]", + "mov w22, v16.s[2]", + "mov w23, v16.s[1]", + "mov w24, v16.s[0]", + "ror w25, w20, #7", + "ror w26, w20, #18", + "eor w25, w25, w26", + "lsr w20, w20, #3", + "eor w20, w25, w20", + "add w20, w21, w20", + "ror w25, w21, #7", + "ror w26, w21, #18", + "eor w25, w25, w26", + "lsr w21, w21, #3", + "eor w21, w25, w21", + "add w21, w22, w21", + "ror w25, w22, #7", + "ror w26, w22, #18", + "eor w25, w25, w26", + "lsr w22, w22, #3", + "eor w22, w25, w22", + "add w22, w23, w22", + "ror w25, w23, #7", + "ror w26, w23, #18", + "eor w25, w25, w26", + "lsr w23, w23, #3", + "eor w23, w25, w23", + "add w23, w24, w23", + "mov v4.16b, v16.16b", + "mov v4.s[3], w20", + "mov v4.16b, v4.16b", + "mov v4.s[2], w21", + "mov v4.16b, v4.16b", + "mov v4.s[1], w22", + "mov v16.16b, v4.16b", + "mov v16.s[0], w23" ] }, "sha256msg2 xmm0, xmm1": { @@ -411,6 +998,46 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xcd" + ], + "ExpectedArm64ASM": [ + "mov w20, v17.s[2]", + "mov w21, v17.s[3]", + "mov w22, v16.s[0]", + "ror w23, w20, #17", + "ror w24, w20, #19", + "eor w23, w23, w24", + "lsr w20, w20, #10", + "eor w20, w23, w20", + "add w20, w22, w20", + "mov w22, v16.s[1]", + "ror w23, w21, #17", + "ror w24, w21, #19", + "eor w23, w23, w24", + "lsr w21, w21, #10", + "eor w21, w23, w21", + "add w21, w22, w21", + "mov w22, v16.s[2]", + "ror w23, w20, #17", + "ror w24, w20, #19", + "eor w23, w23, w24", + "lsr w24, w20, #10", + "eor w23, w23, w24", + "add w22, w22, w23", + "mov w23, v16.s[3]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w25, w21, #10", + "eor w24, w24, w25", + "add w23, w23, w24", + "mov v4.16b, v16.16b", + "mov v4.s[3], w23", + "mov v4.16b, v4.16b", + "mov v4.s[2], w22", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w20" ] }, "aesimc xmm0, xmm1": { @@ -418,6 +1045,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0xdb" + ], + "ExpectedArm64ASM": [ + "unimplemented (Unimplemented)" ] }, "aesenc xmm0, xmm1": { @@ -425,6 +1055,13 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xdc" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v16.16b", + "unimplemented (Unimplemented)", + "unimplemented (Unimplemented)", + "eor v16.16b, v0.16b, v17.16b" ] }, "aesenclast xmm0, xmm1": { @@ -432,6 +1069,12 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xdd" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v16.16b", + "unimplemented (Unimplemented)", + "eor v16.16b, v0.16b, v17.16b" ] }, "aesdec xmm0, xmm1": { @@ -439,6 +1082,13 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xde" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v16.16b", + "unimplemented (Unimplemented)", + "unimplemented (Unimplemented)", + "eor v16.16b, v0.16b, v17.16b" ] }, "aesdeclast xmm0, xmm1": { @@ -446,6 +1096,12 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xdf" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v16.16b", + "unimplemented (Unimplemented)", + "eor v16.16b, v0.16b, v17.16b" ] }, "movbe ax, word [rbx]": { @@ -453,6 +1109,12 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xf0" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x7]", + "rev w20, w20", + "lsr w20, w20, #16", + "bfxil x4, x20, #0, #16" ] }, "movbe eax, dword [rbx]": { @@ -460,6 +1122,10 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x38 0xf0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x7]", + "rev w4, w20" ] }, "movbe rax, qword [rbx]": { @@ -467,6 +1133,10 @@ "Optimal": "Yes", "Comment": [ "REX.W 0x66 0x0f 0x38 0xf0" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x7]", + "rev x4, x20" ] }, "crc32 eax, bl": { @@ -474,6 +1144,11 @@ "Optimal": "No", "Comment": [ "0xf2 0x0f 0x38 0xf0" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "uxtb x21, w7", + "crc32cb w4, w20, w21" ] }, "crc32 eax, bx": { @@ -481,6 +1156,11 @@ "Optimal": "No", "Comment": [ "0xf2 0x0f 0x38 0xf1" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "uxth x21, w7", + "crc32ch w4, w20, w21" ] }, "crc32 eax, ebx": { @@ -488,6 +1168,11 @@ "Optimal": "No", "Comment": [ "0xf2 0x0f 0x38 0xf1" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x7, #0, #32", + "crc32cw w4, w20, w21" ] }, "crc32 rax, bl": { @@ -495,6 +1180,10 @@ "Optimal": "No", "Comment": [ "0xf2 0x0f 0x38 0xf0" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "crc32cb w4, w4, w20" ] }, "crc32 rax, rbx": { @@ -502,6 +1191,9 @@ "Optimal": "Yes", "Comment": [ "0xf2 0x0f 0x38 0xf1" + ], + "ExpectedArm64ASM": [ + "crc32cx w4, w4, x7" ] }, "adcx eax, ebx": { @@ -509,6 +1201,22 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x7, #0, #32", + "ubfx x23, x4, #0, #32", + "add w24, w22, w21", + "add w4, w23, w24", + "cmp w4, w22", + "cset x23, lo", + "cmp w4, w22", + "cset x22, ls", + "cmp x21, #0x1 (1)", + "csel x21, x22, x23, eq", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" ] }, "adcx rax, rbx": { @@ -516,6 +1224,20 @@ "Optimal": "Unknown", "Comment": [ "0x66 REX.W 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "add x22, x7, x21", + "add x4, x4, x22", + "cmp x4, x7", + "cset x22, lo", + "cmp x4, x7", + "cset x23, ls", + "cmp x21, #0x1 (1)", + "csel x21, x23, x22, eq", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" ] }, "adox eax, ebx": { @@ -523,6 +1245,22 @@ "Optimal": "No", "Comment": [ "0xf3 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "ubfx x22, x7, #0, #32", + "ubfx x23, x4, #0, #32", + "add w24, w22, w21", + "add w4, w23, w24", + "cmp w4, w22", + "cset x23, lo", + "cmp w4, w22", + "cset x22, ls", + "cmp x21, #0x1 (1)", + "csel x21, x22, x23, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" ] }, "adox rax, rbx": { @@ -530,7 +1268,21 @@ "Optimal": "Unknown", "Comment": [ "0xf3 REX.W 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "add x22, x7, x21", + "add x4, x4, x22", + "cmp x4, x7", + "cset x22, lo", + "cmp x4, x7", + "cset x23, ls", + "cmp x21, #0x1 (1)", + "csel x21, x23, x22, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index f360c8079..7f9e052e7 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -17,6 +17,12 @@ "Optimal": "No", "Comment": [ "NP 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "ext v4.8b, v5.8b, v4.8b, #0", + "str d4, [x28, #752]" ] }, "palignr mm0, mm1, 1": { @@ -24,6 +30,12 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "ext v4.8b, v5.8b, v4.8b, #1", + "str d4, [x28, #752]" ] }, "palignr mm0, mm1, 255": { @@ -31,6 +43,10 @@ "Optimal": "Yes", "Comment": [ "NP 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "movi d4, #0x0", + "str d4, [x28, #752]" ] }, "roundps xmm0, xmm1, 00000000b": { @@ -39,6 +55,9 @@ "Comment": [ "Nearest rounding", "0x66 0x0f 0x3a 0x08" + ], + "ExpectedArm64ASM": [ + "frinti v16.4s, v17.4s" ] }, "roundps xmm0, xmm1, 00000001b": { @@ -47,6 +66,9 @@ "Comment": [ "-inf rounding", "0x66 0x0f 0x3a 0x08" + ], + "ExpectedArm64ASM": [ + "frintm v16.4s, v17.4s" ] }, "roundps xmm0, xmm1, 00000010b": { @@ -55,6 +77,9 @@ "Comment": [ "+inf rounding", "0x66 0x0f 0x3a 0x08" + ], + "ExpectedArm64ASM": [ + "frintp v16.4s, v17.4s" ] }, "roundps xmm0, xmm1, 00000011b": { @@ -63,6 +88,9 @@ "Comment": [ "truncate rounding", "0x66 0x0f 0x3a 0x08" + ], + "ExpectedArm64ASM": [ + "frintz v16.4s, v17.4s" ] }, "roundps xmm0, xmm1, 00000100b": { @@ -71,6 +99,9 @@ "Comment": [ "host rounding mode rounding", "0x66 0x0f 0x3a 0x08" + ], + "ExpectedArm64ASM": [ + "frinti v16.4s, v17.4s" ] }, "roundpd xmm0, xmm1, 00000000b": { @@ -79,6 +110,9 @@ "Comment": [ "Nearest rounding", "0x66 0x0f 0x3a 0x09" + ], + "ExpectedArm64ASM": [ + "frinti v16.2d, v17.2d" ] }, "roundpd xmm0, xmm1, 00000001b": { @@ -87,6 +121,9 @@ "Comment": [ "-inf rounding", "0x66 0x0f 0x3a 0x09" + ], + "ExpectedArm64ASM": [ + "frintm v16.2d, v17.2d" ] }, "roundpd xmm0, xmm1, 00000010b": { @@ -95,6 +132,9 @@ "Comment": [ "+inf rounding", "0x66 0x0f 0x3a 0x09" + ], + "ExpectedArm64ASM": [ + "frintp v16.2d, v17.2d" ] }, "roundpd xmm0, xmm1, 00000011b": { @@ -103,6 +143,9 @@ "Comment": [ "truncate rounding", "0x66 0x0f 0x3a 0x09" + ], + "ExpectedArm64ASM": [ + "frintz v16.2d, v17.2d" ] }, "roundpd xmm0, xmm1, 00000100b": { @@ -111,6 +154,9 @@ "Comment": [ "host rounding mode rounding", "0x66 0x0f 0x3a 0x09" + ], + "ExpectedArm64ASM": [ + "frinti v16.2d, v17.2d" ] }, "roundss xmm0, xmm1, 00000000b": { @@ -121,6 +167,13 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "frinti v4.4s, v4.4s", + "mov v16.s[0], v4.s[0]" ] }, "roundss xmm0, xmm1, 00000001b": { @@ -131,6 +184,13 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "frintm v4.4s, v4.4s", + "mov v16.s[0], v4.s[0]" ] }, "roundss xmm0, xmm1, 00000010b": { @@ -141,6 +201,13 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "frintp v4.4s, v4.4s", + "mov v16.s[0], v4.s[0]" ] }, "roundss xmm0, xmm1, 00000011b": { @@ -151,6 +218,13 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "frintz v4.4s, v4.4s", + "mov v16.s[0], v4.s[0]" ] }, "roundss xmm0, xmm1, 00000100b": { @@ -161,6 +235,13 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0a" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "frinti v4.4s, v4.4s", + "mov v16.s[0], v4.s[0]" ] }, "roundsd xmm0, xmm1, 00000000b": { @@ -171,6 +252,11 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "frinti v4.2d, v4.2d", + "mov v16.d[0], v4.d[0]" ] }, "roundsd xmm0, xmm1, 00000001b": { @@ -181,6 +267,11 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "frintm v4.2d, v4.2d", + "mov v16.d[0], v4.d[0]" ] }, "roundsd xmm0, xmm1, 00000010b": { @@ -191,6 +282,11 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "frintp v4.2d, v4.2d", + "mov v16.d[0], v4.d[0]" ] }, "roundsd xmm0, xmm1, 00000011b": { @@ -201,6 +297,11 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "frintz v4.2d, v4.2d", + "mov v16.d[0], v4.d[0]" ] }, "roundsd xmm0, xmm1, 00000100b": { @@ -211,6 +312,11 @@ "FPConvert instruction using vector conversion instead of scalar.", "This lowers throughput from 1 IPC to 1/2IPC", "0x66 0x0f 0x3a 0x0b" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "frinti v4.2d, v4.2d", + "mov v16.d[0], v4.d[0]" ] }, "blendps xmm0, xmm1, 0000b": { @@ -218,6 +324,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" ] }, "blendps xmm0, xmm1, 0001b": { @@ -225,6 +335,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v16.s[0], v17.s[0]" ] }, "blendps xmm0, xmm1, 0010b": { @@ -232,6 +345,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v16.s[1], v17.s[1]" ] }, "blendps xmm0, xmm1, 0011b": { @@ -239,6 +355,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[1], v17.s[1]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 0100b": { @@ -246,6 +370,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v16.s[2], v17.s[2]" ] }, "blendps xmm0, xmm1, 0101b": { @@ -253,6 +380,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[2], v17.s[2]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 0110b": { @@ -260,6 +395,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[1], v17.s[1]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[2], v17.s[2]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 0111b": { @@ -267,6 +410,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[1]", + "mov v0.16b, v4.16b", + "mov v0.s[2], v17.s[2]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1000b": { @@ -274,6 +426,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v16.s[3], v17.s[3]" ] }, "blendps xmm0, xmm1, 1001b": { @@ -281,6 +436,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1010b": { @@ -288,6 +451,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[1], v17.s[1]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1011b": { @@ -295,6 +466,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[1]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1100b": { @@ -302,6 +482,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[2], v17.s[2]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1101b": { @@ -309,6 +497,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v17.s[2]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1110b": { @@ -316,6 +513,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[1], v17.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v17.s[2]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendps xmm0, xmm1, 1111b": { @@ -323,6 +529,16 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0c" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[1]", + "mov v4.s[2], v17.s[2]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" ] }, "blendpd xmm0, xmm1, 00b": { @@ -330,6 +546,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0d" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" ] }, "blendpd xmm0, xmm1, 01b": { @@ -337,6 +557,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0d" + ], + "ExpectedArm64ASM": [ + "mov v16.d[0], v17.d[0]" ] }, "blendpd xmm0, xmm1, 10b": { @@ -344,6 +567,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0d" + ], + "ExpectedArm64ASM": [ + "mov v16.d[1], v17.d[1]" ] }, "blendpd xmm0, xmm1, 11b": { @@ -351,6 +577,14 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0d" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.d[0], v17.d[0]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.d[1], v17.d[1]", + "mov v16.16b, v0.16b" ] }, "pblendw xmm0, xmm1, 00000000b": { @@ -358,6 +592,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0e" + ], + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" ] }, "pblendw xmm0, xmm1, 00000001b": { @@ -365,6 +603,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0e" + ], + "ExpectedArm64ASM": [ + "mov v16.h[0], v17.h[0]" ] }, "pblendw xmm0, xmm1, 11111111b": { @@ -372,6 +613,20 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0e" + ], + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.h[0], v17.h[0]", + "mov v4.16b, v0.16b", + "mov v4.h[1], v17.h[1]", + "mov v4.h[2], v17.h[2]", + "mov v4.h[3], v17.h[3]", + "mov v4.h[4], v17.h[4]", + "mov v4.h[5], v17.h[5]", + "mov v4.h[6], v17.h[6]", + "mov v0.16b, v4.16b", + "mov v0.h[7], v17.h[7]", + "mov v16.16b, v0.16b" ] }, "palignr xmm0, xmm1, 0": { @@ -379,6 +634,9 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "ext v16.16b, v17.16b, v16.16b, #0" ] }, "palignr xmm0, xmm1, 1": { @@ -386,6 +644,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "ext v16.16b, v17.16b, v16.16b, #1" ] }, "palignr xmm0, xmm1, 255": { @@ -393,6 +654,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x0f" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "pextrb eax, xmm0, 0000b": { @@ -400,6 +664,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x14" + ], + "ExpectedArm64ASM": [ + "umov w20, v16.b[0]", + "uxtb x4, w20" ] }, "pextrb eax, xmm0, 1111b": { @@ -407,6 +675,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x14" + ], + "ExpectedArm64ASM": [ + "umov w20, v16.b[15]", + "uxtb x4, w20" ] }, "pextrw eax, xmm0, 000b": { @@ -414,6 +686,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x15" + ], + "ExpectedArm64ASM": [ + "umov w20, v16.h[0]", + "uxth x4, w20" ] }, "pextrw eax, xmm0, 111b": { @@ -421,6 +697,10 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x15" + ], + "ExpectedArm64ASM": [ + "umov w20, v16.h[7]", + "uxth x4, w20" ] }, "pextrd eax, xmm0, 00b": { @@ -428,6 +708,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x16" + ], + "ExpectedArm64ASM": [ + "mov w4, v16.s[0]" ] }, "pextrd eax, xmm0, 11b": { @@ -435,6 +718,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x16" + ], + "ExpectedArm64ASM": [ + "mov w4, v16.s[3]" ] }, "pextrq rax, xmm0, 0b": { @@ -442,6 +728,9 @@ "Optimal": "Yes", "Comment": [ "0x66 REX.W 0x0f 0x3a 0x16" + ], + "ExpectedArm64ASM": [ + "mov x4, v16.d[0]" ] }, "pextrq rax, xmm0, 1b": { @@ -449,6 +738,9 @@ "Optimal": "Yes", "Comment": [ "0x66 REX.W 0x0f 0x3a 0x16" + ], + "ExpectedArm64ASM": [ + "mov x4, v16.d[1]" ] }, "extractps eax, xmm0, 00b": { @@ -456,6 +748,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x17" + ], + "ExpectedArm64ASM": [ + "mov w4, v16.s[0]" ] }, "extractps eax, xmm0, 11b": { @@ -463,6 +758,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x17" + ], + "ExpectedArm64ASM": [ + "mov w4, v16.s[3]" ] }, "pinsrb xmm0, eax, 0000b": { @@ -470,6 +768,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov v16.16b, v16.16b", + "mov v16.b[0], w20" ] }, "pinsrb xmm0, eax, 0001b": { @@ -477,6 +780,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov v16.16b, v16.16b", + "mov v16.b[1], w20" ] }, "pinsrb xmm0, eax, 1111b": { @@ -484,6 +792,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov v16.16b, v16.16b", + "mov v16.b[15], w20" ] }, "insertps xmm0, xmm1, 00000000b": { @@ -491,6 +804,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x21" + ], + "ExpectedArm64ASM": [ + "mov v16.s[0], v17.s[0]" ] }, "insertps xmm0, xmm1, 00001111b": { @@ -498,6 +814,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x21" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "insertps xmm0, xmm1, 00010000b": { @@ -505,6 +824,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x21" + ], + "ExpectedArm64ASM": [ + "mov v16.s[1], v17.s[0]" ] }, "pinsrd xmm0, eax, 00b": { @@ -512,6 +834,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov v16.16b, v16.16b", + "mov v16.s[0], w20" ] }, "pinsrd xmm0, eax, 01b": { @@ -519,6 +846,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov v16.16b, v16.16b", + "mov v16.s[1], w20" ] }, "pinsrd xmm0, eax, 11b": { @@ -526,6 +858,11 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov v16.16b, v16.16b", + "mov v16.s[3], w20" ] }, "pinsrq xmm0, rax, 0b": { @@ -533,6 +870,10 @@ "Optimal": "No", "Comment": [ "0x66 REX.W 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "mov v16.16b, v16.16b", + "mov v16.d[0], x4" ] }, "pinsrq xmm0, rax, 1b": { @@ -540,6 +881,10 @@ "Optimal": "No", "Comment": [ "0x66 REX.W 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "mov v16.16b, v16.16b", + "mov v16.d[1], x4" ] }, "dpps xmm0, xmm1, 00000000b": { @@ -547,6 +892,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x40" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "dpps xmm0, xmm1, 00001111b": { @@ -554,6 +902,22 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x40" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "fmul v5.4s, v16.4s, v17.4s", + "mov v5.s[0], v4.s[0]", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v5.s[3], v4.s[0]", + "faddp v5.4s, v5.4s, v4.4s", + "faddp v5.4s, v5.4s, v4.4s", + "mov v4.s[0], v5.s[0]", + "mov v4.s[1], v5.s[0]", + "mov v4.s[2], v5.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v5.s[0]", + "mov v16.16b, v0.16b" ] }, "dpps xmm0, xmm1, 11110000b": { @@ -561,6 +925,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x40" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "dpps xmm0, xmm1, 11111111b": { @@ -568,6 +935,18 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x40" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "fmul v5.4s, v16.4s, v17.4s", + "faddp v5.4s, v5.4s, v4.4s", + "faddp v5.4s, v5.4s, v4.4s", + "mov v4.s[0], v5.s[0]", + "mov v4.s[1], v5.s[0]", + "mov v4.s[2], v5.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v5.s[0]", + "mov v16.16b, v0.16b" ] }, "dppd xmm0, xmm1, 00000000b": { @@ -575,6 +954,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x41" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "dppd xmm0, xmm1, 00001111b": { @@ -582,6 +964,17 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x41" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "fmul v5.2d, v16.2d, v17.2d", + "mov v5.d[0], v4.d[0]", + "mov v5.d[1], v4.d[0]", + "faddp v5.2d, v5.2d, v4.2d", + "mov v4.d[0], v5.d[0]", + "mov v0.16b, v4.16b", + "mov v0.d[1], v5.d[0]", + "mov v16.16b, v0.16b" ] }, "dppd xmm0, xmm1, 11110000b": { @@ -589,6 +982,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x41" + ], + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" ] }, "dppd xmm0, xmm1, 11111111b": { @@ -596,6 +992,15 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x41" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "fmul v5.2d, v16.2d, v17.2d", + "faddp v5.2d, v5.2d, v4.2d", + "mov v4.d[0], v5.d[0]", + "mov v0.16b, v4.16b", + "mov v0.d[1], v5.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 000b": { @@ -603,6 +1008,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[0]", + "ext v5.16b, v16.16b, v16.16b, #0", + "ext v6.16b, v16.16b, v16.16b, #1", + "ext v7.16b, v16.16b, v16.16b, #2", + "ext v8.16b, v16.16b, v16.16b, #3", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 001b": { @@ -610,6 +1034,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[1]", + "ext v5.16b, v16.16b, v16.16b, #0", + "ext v6.16b, v16.16b, v16.16b, #1", + "ext v7.16b, v16.16b, v16.16b, #2", + "ext v8.16b, v16.16b, v16.16b, #3", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 010b": { @@ -617,6 +1060,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[2]", + "ext v5.16b, v16.16b, v16.16b, #0", + "ext v6.16b, v16.16b, v16.16b, #1", + "ext v7.16b, v16.16b, v16.16b, #2", + "ext v8.16b, v16.16b, v16.16b, #3", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 011b": { @@ -624,6 +1086,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[3]", + "ext v5.16b, v16.16b, v16.16b, #0", + "ext v6.16b, v16.16b, v16.16b, #1", + "ext v7.16b, v16.16b, v16.16b, #2", + "ext v8.16b, v16.16b, v16.16b, #3", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 100b": { @@ -631,6 +1112,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[0]", + "ext v5.16b, v16.16b, v16.16b, #4", + "ext v6.16b, v16.16b, v16.16b, #5", + "ext v7.16b, v16.16b, v16.16b, #6", + "ext v8.16b, v16.16b, v16.16b, #7", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 101b": { @@ -638,6 +1138,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[1]", + "ext v5.16b, v16.16b, v16.16b, #4", + "ext v6.16b, v16.16b, v16.16b, #5", + "ext v7.16b, v16.16b, v16.16b, #6", + "ext v8.16b, v16.16b, v16.16b, #7", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 110b": { @@ -645,6 +1164,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[2]", + "ext v5.16b, v16.16b, v16.16b, #4", + "ext v6.16b, v16.16b, v16.16b, #5", + "ext v7.16b, v16.16b, v16.16b, #6", + "ext v8.16b, v16.16b, v16.16b, #7", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "mpsadbw xmm0, xmm1, 111b": { @@ -652,6 +1190,25 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0x42" + ], + "ExpectedArm64ASM": [ + "dup v4.4s, v17.s[3]", + "ext v5.16b, v16.16b, v16.16b, #4", + "ext v6.16b, v16.16b, v16.16b, #5", + "ext v7.16b, v16.16b, v16.16b, #6", + "ext v8.16b, v16.16b, v16.16b, #7", + "uabdl v5.8h, v5.8b, v4.8b", + "uabdl v6.8h, v6.8b, v4.8b", + "uabdl v7.8h, v7.8b, v4.8b", + "uabdl v4.8h, v8.8b, v4.8b", + "addp v5.8h, v5.8h, v6.8h", + "addp v4.8h, v7.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v16.16b, v0.16b" ] }, "pclmulqdq xmm0, xmm1, 00000b": { @@ -659,6 +1216,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x44" + ], + "ExpectedArm64ASM": [ + "unallocated (Unallocated)" ] }, "pclmulqdq xmm0, xmm1, 00001b": { @@ -666,6 +1226,10 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x44" + ], + "ExpectedArm64ASM": [ + "dup v0.2d, v16.d[1]", + "unallocated (Unallocated)" ] }, "pclmulqdq xmm0, xmm1, 10000b": { @@ -673,6 +1237,10 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x44" + ], + "ExpectedArm64ASM": [ + "dup v0.2d, v17.d[1]", + "unallocated (Unallocated)" ] }, "pclmulqdq xmm0, xmm1, 10001b": { @@ -680,6 +1248,9 @@ "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x44" + ], + "ExpectedArm64ASM": [ + "unallocated (Unallocated)" ] }, "sha1rnds4 xmm0, xmm1, 00b": { @@ -687,6 +1258,69 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xcc" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0x20 (32)", + "mov w20, #0x7999", + "movk w20, #0x5a82, lsl #16", + "mov w20, v17.s[3]", + "mov w21, v17.s[2]", + "mov w22, v17.s[1]", + "mov w23, v17.s[0]", + "str w23, [sp]", + "mov w23, v16.s[3]", + "mov w24, v16.s[2]", + "mov w25, v16.s[1]", + "mov w26, v16.s[0]", + "and w27, w24, w25", + "bic w30, w26, w24", + "eor w27, w27, w30", + "ror w30, w23, #27", + "add w27, w27, w30", + "add w20, w27, w20", + "mov w27, #0x7999", + "movk w27, #0x5a82, lsl #16", + "add w20, w20, w27", + "ror w24, w24, #2", + "and w27, w23, w24", + "bic w30, w25, w23", + "eor w27, w27, w30", + "ror w30, w20, #27", + "add w27, w27, w30", + "add w21, w27, w21", + "add w21, w21, w26", + "mov w26, #0x7999", + "movk w26, #0x5a82, lsl #16", + "add w21, w21, w26", + "ror w23, w23, #2", + "and w27, w20, w23", + "bic w30, w24, w20", + "eor w27, w27, w30", + "ror w30, w21, #27", + "add w27, w27, w30", + "add w22, w27, w22", + "add w22, w22, w25", + "add w22, w22, w26", + "ror w20, w20, #2", + "and w25, w21, w20", + "bic w23, w23, w21", + "eor w23, w25, w23", + "ror w25, w22, #27", + "add w23, w23, w25", + "ldr w25, [sp]", + "add w23, w23, w25", + "add w23, w23, w24", + "add w23, w23, w26", + "ror w21, w21, #2", + "mov v4.16b, v16.16b", + "mov v4.s[3], w23", + "mov v4.16b, v4.16b", + "mov v4.s[2], w22", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w20", + "add sp, sp, #0x20 (32)" ] }, "sha1rnds4 xmm0, xmm1, 01b": { @@ -694,6 +1328,65 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xcc" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0x20 (32)", + "mov w20, #0xeba1", + "movk w20, #0x6ed9, lsl #16", + "mov w20, v17.s[3]", + "mov w21, v17.s[2]", + "mov w22, v17.s[1]", + "mov w23, v17.s[0]", + "str w23, [sp]", + "mov w23, v16.s[3]", + "mov w24, v16.s[2]", + "mov w25, v16.s[1]", + "mov w26, v16.s[0]", + "eor w27, w24, w25", + "eor w27, w27, w26", + "ror w30, w23, #27", + "add w27, w27, w30", + "add w20, w27, w20", + "mov w27, #0xeba1", + "movk w27, #0x6ed9, lsl #16", + "add w20, w20, w27", + "ror w24, w24, #2", + "eor w27, w23, w24", + "eor w27, w27, w25", + "ror w30, w20, #27", + "add w27, w27, w30", + "add w21, w27, w21", + "add w21, w21, w26", + "mov w26, #0xeba1", + "movk w26, #0x6ed9, lsl #16", + "add w21, w21, w26", + "ror w23, w23, #2", + "eor w27, w20, w23", + "eor w27, w27, w24", + "ror w30, w21, #27", + "add w27, w27, w30", + "add w22, w27, w22", + "add w22, w22, w25", + "add w22, w22, w26", + "ror w20, w20, #2", + "eor w25, w21, w20", + "eor w23, w25, w23", + "ror w25, w22, #27", + "add w23, w23, w25", + "ldr w25, [sp]", + "add w23, w23, w25", + "add w23, w23, w24", + "add w23, w23, w26", + "ror w21, w21, #2", + "mov v4.16b, v16.16b", + "mov v4.s[3], w23", + "mov v4.16b, v4.16b", + "mov v4.s[2], w22", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w20", + "add sp, sp, #0x20 (32)" ] }, "sha1rnds4 xmm0, xmm1, 10b": { @@ -701,6 +1394,77 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xcc" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0x20 (32)", + "mov w20, #0xbcdc", + "movk w20, #0x8f1b, lsl #16", + "mov w20, v17.s[3]", + "mov w21, v17.s[2]", + "mov w22, v17.s[1]", + "mov w23, v17.s[0]", + "str w23, [sp]", + "mov w23, v16.s[3]", + "mov w24, v16.s[2]", + "mov w25, v16.s[1]", + "mov w26, v16.s[0]", + "and w27, w24, w25", + "and w30, w24, w26", + "eor w27, w27, w30", + "and w30, w25, w26", + "eor w27, w27, w30", + "ror w30, w23, #27", + "add w27, w27, w30", + "add w20, w27, w20", + "mov w27, #0xbcdc", + "movk w27, #0x8f1b, lsl #16", + "add w20, w20, w27", + "ror w24, w24, #2", + "and w27, w23, w24", + "and w30, w23, w25", + "eor w27, w27, w30", + "and w30, w24, w25", + "eor w27, w27, w30", + "ror w30, w20, #27", + "add w27, w27, w30", + "add w21, w27, w21", + "add w21, w21, w26", + "mov w26, #0xbcdc", + "movk w26, #0x8f1b, lsl #16", + "add w21, w21, w26", + "ror w23, w23, #2", + "and w27, w20, w23", + "and w30, w20, w24", + "eor w27, w27, w30", + "and w30, w23, w24", + "eor w27, w27, w30", + "ror w30, w21, #27", + "add w27, w27, w30", + "add w22, w27, w22", + "add w22, w22, w25", + "add w22, w22, w26", + "ror w20, w20, #2", + "and w25, w21, w20", + "and w27, w21, w23", + "eor w25, w25, w27", + "and w23, w20, w23", + "eor w23, w25, w23", + "ror w25, w22, #27", + "add w23, w23, w25", + "ldr w25, [sp]", + "add w23, w23, w25", + "add w23, w23, w24", + "add w23, w23, w26", + "ror w21, w21, #2", + "mov v4.16b, v16.16b", + "mov v4.s[3], w23", + "mov v4.16b, v4.16b", + "mov v4.s[2], w22", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w20", + "add sp, sp, #0x20 (32)" ] }, "sha1rnds4 xmm0, xmm1, 11b": { @@ -708,6 +1472,65 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xcc" + ], + "ExpectedArm64ASM": [ + "sub sp, sp, #0x20 (32)", + "mov w20, #0xc1d6", + "movk w20, #0xca62, lsl #16", + "mov w20, v17.s[3]", + "mov w21, v17.s[2]", + "mov w22, v17.s[1]", + "mov w23, v17.s[0]", + "str w23, [sp]", + "mov w23, v16.s[3]", + "mov w24, v16.s[2]", + "mov w25, v16.s[1]", + "mov w26, v16.s[0]", + "eor w27, w24, w25", + "eor w27, w27, w26", + "ror w30, w23, #27", + "add w27, w27, w30", + "add w20, w27, w20", + "mov w27, #0xc1d6", + "movk w27, #0xca62, lsl #16", + "add w20, w20, w27", + "ror w24, w24, #2", + "eor w27, w23, w24", + "eor w27, w27, w25", + "ror w30, w20, #27", + "add w27, w27, w30", + "add w21, w27, w21", + "add w21, w21, w26", + "mov w26, #0xc1d6", + "movk w26, #0xca62, lsl #16", + "add w21, w21, w26", + "ror w23, w23, #2", + "eor w27, w20, w23", + "eor w27, w27, w24", + "ror w30, w21, #27", + "add w27, w27, w30", + "add w22, w27, w22", + "add w22, w22, w25", + "add w22, w22, w26", + "ror w20, w20, #2", + "eor w25, w21, w20", + "eor w23, w25, w23", + "ror w25, w22, #27", + "add w23, w23, w25", + "ldr w25, [sp]", + "add w23, w23, w25", + "add w23, w23, w24", + "add w23, w23, w26", + "ror w21, w21, #2", + "mov v4.16b, v16.16b", + "mov v4.s[3], w23", + "mov v4.16b, v4.16b", + "mov v4.s[2], w22", + "mov v4.16b, v4.16b", + "mov v4.s[1], w21", + "mov v16.16b, v4.16b", + "mov v16.s[0], w20", + "add sp, sp, #0x20 (32)" ] }, "aeskeygenassist xmm0, xmm1, 0": { @@ -715,6 +1538,18 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xdf" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v17.16b", + "unimplemented (Unimplemented)", + "ldr q2, pc+12", + "tbl v16.16b, {v0.16b}, v2.16b", + "b #+0x14", + "add w4, w8, w14", + "umin z1.b, p3/m, z1.b, z16.b", + "unallocated (Unallocated)", + "unallocated (Unallocated)" ] }, "aeskeygenassist xmm0, xmm1, 0xFF": { @@ -722,7 +1557,22 @@ "Optimal": "No", "Comment": [ "0x66 0x0f 0x3a 0xdf" + ], + "ExpectedArm64ASM": [ + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v17.16b", + "unimplemented (Unimplemented)", + "ldr q2, pc+24", + "tbl v0.16b, {v0.16b}, v2.16b", + "orr x0, xzr, #0xff00000000", + "dup v1.2d, x0", + "eor v16.16b, v0.16b, v1.16b", + "b #+0x14", + "add w4, w8, w14", + "umin z1.b, p3/m, z1.b, z16.b", + "unallocated (Unallocated)", + "unallocated (Unallocated)" ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 75f6d75f8..aaaed7d28 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -11,22 +11,119 @@ "add bl, cl": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x00" + "Comment": "0x00", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "add w22, w21, w20", + "bfxil x7, x22, #0, #8", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add bx, cx": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x01" + "Comment": "0x01", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "add w22, w21, w20", + "bfxil x7, x22, #0, #16", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add ebx, ecx": { "ExpectedInstructionCount": "20", "Optimal": "No", - "Comment": "0x01" + "Comment": "0x01", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "add w7, w21, w20", + "eor w22, w21, w20", + "eor w22, w22, w7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst w7, w7", + "mrs x22, nzcv", + "cmp w7, w20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w20, w21, w20", + "eor w21, w7, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add rbx, rcx": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x01" + "Comment": "0x01", + "ExpectedArm64ASM": [ + "mov x20, x7", + "add x7, x20, x5", + "eor x21, x20, x5", + "eor x21, x21, x7", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x7, #0x1", + "strb w21, [x28, #706]", + "tst x7, x7", + "mrs x21, nzcv", + "cmp x7, x5", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, x5", + "eor x20, x7, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "db 0x02, 0xcb": { "ExpectedInstructionCount": "25", @@ -34,6 +131,33 @@ "Comment": [ "0x02", "add bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "add w22, w21, w20", + "bfxil x5, x22, #0, #8", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x66, 0x03, 0xcb": { @@ -42,6 +166,33 @@ "Comment": [ "0x03", "add bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "add w22, w21, w20", + "bfxil x5, x22, #0, #16", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x03, 0xcb": { @@ -50,6 +201,28 @@ "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "add w5, w21, w20", + "eor w22, w21, w20", + "eor w22, w22, w5", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x5, #0x1", + "strb w22, [x28, #706]", + "tst w5, w5", + "mrs x22, nzcv", + "cmp w5, w20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w20, w21, w20", + "eor w21, w5, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x48, 0x03, 0xcb": { @@ -58,47 +231,216 @@ "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov x20, x5", + "add x5, x20, x7", + "eor x21, x20, x7", + "eor x21, x21, x5", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x5, #0x1", + "strb w21, [x28, #706]", + "tst x5, x5", + "mrs x21, nzcv", + "cmp x5, x7", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, x7", + "eor x20, x5, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "add al, 1": { "ExpectedInstructionCount": "24", "Optimal": "No", - "Comment": "0x04" + "Comment": "0x04", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w21, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add ax, 1": { "ExpectedInstructionCount": "24", "Optimal": "No", - "Comment": "0x05" + "Comment": "0x05", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #16", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w21, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add eax, 1": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x05" + "Comment": "0x05", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "add w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add rax, 1": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x05" + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "or bl, cl": { "ExpectedInstructionCount": "14", "Optimal": "No", - "Comment": "0x08" + "Comment": "0x08", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "orr w20, w21, w20", + "bfxil x7, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "or bx, cx": { "ExpectedInstructionCount": "14", "Optimal": "No", - "Comment": "0x09" + "Comment": "0x09", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "orr w20, w21, w20", + "bfxil x7, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "or ebx, ecx": { "ExpectedInstructionCount": "10", "Optimal": "No", - "Comment": "0x09" + "Comment": "0x09", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "orr w7, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "or rbx, rcx": { "ExpectedInstructionCount": "8", "Optimal": "No", - "Comment": "0x09" + "Comment": "0x09", + "ExpectedArm64ASM": [ + "orr x7, x7, x5", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "db 0x0A, 0xcb": { "ExpectedInstructionCount": "14", @@ -106,6 +448,22 @@ "Comment": [ "0x0A", "or bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "orr w20, w21, w20", + "bfxil x5, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x66, 0x0B, 0xcb": { @@ -114,6 +472,22 @@ "Comment": [ "0x0B", "or bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "orr w20, w21, w20", + "bfxil x5, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x0B, 0xcb": { @@ -122,6 +496,18 @@ "Comment": [ "0x0B", "or ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "orr w5, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "db 0x48, 0x0B, 0xcb": { @@ -130,47 +516,233 @@ "Comment": [ "0x0B", "or rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "orr x5, x5, x7", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "or al, 1": { "ExpectedInstructionCount": "13", "Optimal": "No", - "Comment": "0x0C" + "Comment": "0x0C", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "orr w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "or ax, 1": { "ExpectedInstructionCount": "13", "Optimal": "No", - "Comment": "0x0D" + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "orr w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "or eax, 1": { "ExpectedInstructionCount": "9", "Optimal": "No", - "Comment": "0x0D" + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "orr w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "or rax, 1": { "ExpectedInstructionCount": "8", "Optimal": "No", - "Comment": "0x0D" + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "adc bl, cl": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x10" + "Comment": "0x10", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxtb x23, w7", + "add w22, w23, w22", + "bfxil x7, x22, #0, #8", + "uxtb x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "adc bx, cx": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x11" + "Comment": "0x11", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxth x23, w7", + "add w22, w23, w22", + "bfxil x7, x22, #0, #16", + "uxth x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "adc ebx, ecx": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x11" + "Comment": "0x11", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "ubfx x23, x7, #0, #32", + "add w7, w23, w22", + "eor w22, w23, w20", + "eor w22, w22, w7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst w7, w7", + "mrs x22, nzcv", + "cmp w7, w20", + "cset x24, lo", + "cmp w7, w20", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x22, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w7, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "adc rbx, rcx": { "ExpectedInstructionCount": "26", "Optimal": "No", - "Comment": "0x11" + "Comment": "0x11", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x20, x20, #29, #1", + "add x21, x5, x20", + "mov x22, x7", + "add x7, x22, x21", + "eor x21, x22, x5", + "eor x21, x21, x7", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x7, #0x1", + "strb w21, [x28, #706]", + "tst x7, x7", + "mrs x21, nzcv", + "cmp x7, x5", + "cset x23, lo", + "cmp x7, x5", + "cset x24, ls", + "cmp x20, #0x1 (1)", + "csel x20, x24, x23, eq", + "orr x20, x21, x20, lsl #29", + "eor x21, x22, x5", + "eor x22, x7, x22", + "bic x21, x22, x21", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "db 0x12, 0xcb": { "ExpectedInstructionCount": "32", @@ -178,6 +750,40 @@ "Comment": [ "0x12", "adc bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxtb x23, w5", + "add w22, w23, w22", + "bfxil x5, x22, #0, #8", + "uxtb x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x66, 0x13, 0xcb": { @@ -186,6 +792,40 @@ "Comment": [ "0x13", "adc bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxth x23, w5", + "add w22, w23, w22", + "bfxil x5, x22, #0, #16", + "uxth x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x13, 0xcb": { @@ -194,6 +834,35 @@ "Comment": [ "0x13", "adc ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "ubfx x23, x5, #0, #32", + "add w5, w23, w22", + "eor w22, w23, w20", + "eor w22, w22, w5", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x5, #0x1", + "strb w22, [x28, #706]", + "tst w5, w5", + "mrs x22, nzcv", + "cmp w5, w20", + "cset x24, lo", + "cmp w5, w20", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x22, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w5, w23", + "bic w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x48, 0x13, 0xcb": { @@ -202,47 +871,326 @@ "Comment": [ "0x13", "adc rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x20, x20, #29, #1", + "add x21, x7, x20", + "mov x22, x5", + "add x5, x22, x21", + "eor x21, x22, x7", + "eor x21, x21, x5", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x5, #0x1", + "strb w21, [x28, #706]", + "tst x5, x5", + "mrs x21, nzcv", + "cmp x5, x7", + "cset x23, lo", + "cmp x5, x7", + "cset x24, ls", + "cmp x20, #0x1 (1)", + "csel x20, x24, x23, eq", + "orr x20, x21, x20, lsl #29", + "eor x21, x22, x7", + "eor x22, x5, x22", + "bic x21, x22, x21", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" ] }, "adc al, 1": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x14" + "Comment": "0x14", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxtb x22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #24", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "bic w20, w20, w23", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "adc ax, 1": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x15" + "Comment": "0x15", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxth x22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #16", + "uxth x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "adc eax, 1": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x15" + "Comment": "0x15", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "add w4, w22, w20", + "eor w20, w22, #0x1", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, #0x1 (1)", + "cset x23, lo", + "cmp w4, #0x1 (1)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x1", + "eor w22, w4, w22", + "bic w21, w22, w21", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "adc rax, 1": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x15" + "Comment": "0x15", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "add x4, x22, x20", + "eor x20, x22, #0x1", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, #0x1 (1)", + "cset x23, lo", + "cmp x4, #0x1 (1)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x1", + "eor x22, x4, x22", + "bic x21, x22, x21", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb bl, cl": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x18" + "Comment": "0x18", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxtb x23, w7", + "sub w22, w23, w22", + "bfxil x7, x22, #0, #8", + "uxtb x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb bx, cx": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x19" + "Comment": "0x19", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxth x23, w7", + "sub w22, w23, w22", + "bfxil x7, x22, #0, #16", + "uxth x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb ebx, ecx": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x19" + "Comment": "0x19", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "ubfx x23, x7, #0, #32", + "sub w7, w23, w22", + "eor w22, w23, w20", + "eor w22, w22, w7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst w7, w7", + "mrs x22, nzcv", + "cmp w7, w23", + "cset x24, hi", + "cmp w7, w23", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x22, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w7, w23", + "and w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb rbx, rcx": { "ExpectedInstructionCount": "26", "Optimal": "No", - "Comment": "0x19" + "Comment": "0x19", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x20, x20, #29, #1", + "add x21, x5, x20", + "mov x22, x7", + "sub x7, x22, x21", + "eor x21, x22, x5", + "eor x21, x21, x7", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x7, #0x1", + "strb w21, [x28, #706]", + "tst x7, x7", + "mrs x21, nzcv", + "cmp x7, x22", + "cset x23, hi", + "cmp x7, x22", + "cset x24, hs", + "cmp x20, #0x1 (1)", + "csel x20, x24, x23, eq", + "orr x20, x21, x20, lsl #29", + "eor x21, x22, x5", + "eor x22, x7, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "db 0x1A, 0xcb": { "ExpectedInstructionCount": "32", @@ -250,6 +1198,40 @@ "Comment": [ "0x1A", "sbb bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxtb x23, w5", + "sub w22, w23, w22", + "bfxil x5, x22, #0, #8", + "uxtb x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x66, 0x1B, 0xcb": { @@ -258,6 +1240,40 @@ "Comment": [ "0x1B", "sbb bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "uxth x23, w5", + "sub w22, w23, w22", + "bfxil x5, x22, #0, #16", + "uxth x22, w22", + "eor w24, w23, w20", + "eor w24, w24, w22", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x22, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr x21, x24, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x1B, 0xcb": { @@ -266,6 +1282,35 @@ "Comment": [ "0x1B", "sbb ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w22, w20, w21", + "ubfx x23, x5, #0, #32", + "sub w5, w23, w22", + "eor w22, w23, w20", + "eor w22, w22, w5", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x5, #0x1", + "strb w22, [x28, #706]", + "tst w5, w5", + "mrs x22, nzcv", + "cmp w5, w23", + "cset x24, hi", + "cmp w5, w23", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x22, x21, lsl #29", + "eor w20, w23, w20", + "eor w22, w5, w23", + "and w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x48, 0x1B, 0xcb": { @@ -274,47 +1319,255 @@ "Comment": [ "0x1B", "sbb rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x20, x20, #29, #1", + "add x21, x7, x20", + "mov x22, x5", + "sub x5, x22, x21", + "eor x21, x22, x7", + "eor x21, x21, x5", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x5, #0x1", + "strb w21, [x28, #706]", + "tst x5, x5", + "mrs x21, nzcv", + "cmp x5, x22", + "cset x23, hi", + "cmp x5, x22", + "cset x24, hs", + "cmp x20, #0x1 (1)", + "csel x20, x24, x23, eq", + "orr x20, x21, x20, lsl #29", + "eor x21, x22, x7", + "eor x22, x5, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" ] }, "sbb al, 1": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x1C" + "Comment": "0x1C", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxtb x22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #24", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb ax, 1": { "ExpectedInstructionCount": "32", "Optimal": "No", - "Comment": "0x1D" + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxth x22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #16", + "uxth x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "and w20, w23, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb eax, 1": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x1D" + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "sub w4, w22, w20", + "eor w20, w22, #0x1", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, w22", + "cset x23, hi", + "cmp w4, w22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x1", + "eor w22, w4, w22", + "and w21, w21, w22", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb rax, 1": { "ExpectedInstructionCount": "27", "Optimal": "No", - "Comment": "0x1D" + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "sub x4, x22, x20", + "eor x20, x22, #0x1", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, x22", + "cset x23, hi", + "cmp x4, x22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x1", + "eor x22, x4, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "and bl, cl": { "ExpectedInstructionCount": "14", "Optimal": "No", - "Comment": "0x20" + "Comment": "0x20", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "and w20, w21, w20", + "bfxil x7, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "and bx, cx": { "ExpectedInstructionCount": "14", "Optimal": "No", - "Comment": "0x21" + "Comment": "0x21", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "and w20, w21, w20", + "bfxil x7, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "and ebx, ecx": { "ExpectedInstructionCount": "10", "Optimal": "No", - "Comment": "0x21" + "Comment": "0x21", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "and w7, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "and rbx, rcx": { "ExpectedInstructionCount": "8", "Optimal": "No", - "Comment": "0x21" + "Comment": "0x21", + "ExpectedArm64ASM": [ + "and x7, x7, x5", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "db 0x22, 0xcb": { "ExpectedInstructionCount": "14", @@ -322,6 +1575,22 @@ "Comment": [ "0x22", "and bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "and w20, w21, w20", + "bfxil x5, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x66, 0x23, 0xcb": { @@ -330,6 +1599,22 @@ "Comment": [ "0x23", "and bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "and w20, w21, w20", + "bfxil x5, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x23, 0xcb": { @@ -338,6 +1623,18 @@ "Comment": [ "0x23", "and ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "and w5, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "db 0x48, 0x23, 0xcb": { @@ -346,47 +1643,205 @@ "Comment": [ "0x23", "and rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "and x5, x5, x7", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "and al, 1": { "ExpectedInstructionCount": "13", "Optimal": "No", - "Comment": "0x24" + "Comment": "0x24", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "and w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "and ax, 1": { "ExpectedInstructionCount": "13", "Optimal": "No", - "Comment": "0x25" + "Comment": "0x25", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "and w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "and eax, 1": { "ExpectedInstructionCount": "9", "Optimal": "No", - "Comment": "0x25" + "Comment": "0x25", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "and w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "and rax, 1": { "ExpectedInstructionCount": "8", "Optimal": "No", - "Comment": "0x25" + "Comment": "0x25", + "ExpectedArm64ASM": [ + "and x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "sub bl, cl": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x28" + "Comment": "0x28", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "sub w22, w21, w20", + "bfxil x7, x22, #0, #8", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub bx, cx": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x29" + "Comment": "0x29", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "sub w22, w21, w20", + "bfxil x7, x22, #0, #16", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub ebx, ecx": { "ExpectedInstructionCount": "20", "Optimal": "No", - "Comment": "0x29" + "Comment": "0x29", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "sub w7, w21, w20", + "eor w22, w21, w20", + "eor w22, w22, w7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst w7, w7", + "mrs x22, nzcv", + "cmp w21, w20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w20, w21, w20", + "eor w21, w7, w21", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub rbx, rcx": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x29" + "Comment": "0x29", + "ExpectedArm64ASM": [ + "mov x20, x7", + "sub x7, x20, x5", + "eor x21, x20, x5", + "eor x21, x21, x7", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x7, #0x1", + "strb w21, [x28, #706]", + "tst x7, x7", + "mrs x21, nzcv", + "cmp x20, x5", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, x5", + "eor x20, x7, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "db 0x2A, 0xcb": { "ExpectedInstructionCount": "25", @@ -394,6 +1849,33 @@ "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "sub w22, w21, w20", + "bfxil x5, x22, #0, #8", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x66, 0x2B, 0xcb": { @@ -402,6 +1884,33 @@ "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "sub w22, w21, w20", + "bfxil x5, x22, #0, #16", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x2B, 0xcb": { @@ -410,6 +1919,28 @@ "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "sub w5, w21, w20", + "eor w22, w21, w20", + "eor w22, w22, w5", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x5, #0x1", + "strb w22, [x28, #706]", + "tst w5, w5", + "mrs x22, nzcv", + "cmp w21, w20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w20, w21, w20", + "eor w21, w5, w21", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x48, 0x2B, 0xcb": { @@ -418,47 +1949,216 @@ "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov x20, x5", + "sub x5, x20, x7", + "eor x21, x20, x7", + "eor x21, x21, x5", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x5, #0x1", + "strb w21, [x28, #706]", + "tst x5, x5", + "mrs x21, nzcv", + "cmp x20, x7", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, x7", + "eor x20, x5, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "sub al, 1": { "ExpectedInstructionCount": "24", "Optimal": "No", - "Comment": "0x2C" + "Comment": "0x2C", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub ax, 1": { "ExpectedInstructionCount": "24", "Optimal": "No", - "Comment": "0x2D" + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #16", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub eax, 1": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x2D" + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w20, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "and w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub rax, 1": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x2D" + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x20, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xor bl, cl": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x30" + "Comment": "0x30", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "eor w20, w21, w20", + "bfxil x7, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "xor bx, cx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x31" + "Comment": "0x31", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "eor w20, w21, w20", + "bfxil x7, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "xor ebx, ecx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x31" + "Comment": "0x31", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "eor w7, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "xor rbx, rcx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x31" + "Comment": "0x31", + "ExpectedArm64ASM": [ + "eor x7, x7, x5", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "db 0x32, 0xcb": { "ExpectedInstructionCount": 14, @@ -466,6 +2166,22 @@ "Comment": [ "0x32", "xor bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "eor w20, w21, w20", + "bfxil x5, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x66, 0x33, 0xcb": { @@ -474,6 +2190,22 @@ "Comment": [ "0x33", "xor bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "eor w20, w21, w20", + "bfxil x5, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" ] }, "db 0x33, 0xcb": { @@ -482,6 +2214,18 @@ "Comment": [ "0x33", "xor ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "eor w5, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "db 0x48, 0x33, 0xcb": { @@ -490,47 +2234,202 @@ "Comment": [ "0x33", "xor rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "eor x5, x5, x7", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x5, #0x1", + "strb w20, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "xor al, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x34" + "Comment": "0x34", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "eor w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "xor ax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x35" + "Comment": "0x35", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "eor w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "xor eax, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x35" + "Comment": "0x35", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "eor w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "xor rax, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x35" + "Comment": "0x35", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "cmp bl, cl": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "0x38" + "Comment": "0x38", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w7", + "sub w22, w21, w20", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp bx, cx": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "0x39" + "Comment": "0x39", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w7", + "sub w22, w21, w20", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp ebx, ecx": { "ExpectedInstructionCount": "20", "Optimal": "No", - "Comment": "0x39" + "Comment": "0x39", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x7, #0, #32", + "sub w22, w21, w20", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst w22, w22", + "mrs x23, nzcv", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp rbx, rcx": { "ExpectedInstructionCount": 18, "Optimal": "Yes", - "Comment": "0x39" + "Comment": "0x39", + "ExpectedArm64ASM": [ + "sub x20, x7, x5", + "eor x21, x7, x5", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x21, nzcv", + "cmp x7, x5", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x7, x5", + "eor x20, x20, x7", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "db 0x3A, 0xcb": { "ExpectedInstructionCount": 24, @@ -538,6 +2437,32 @@ "Comment": [ "0x3A", "cmp bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "sub w22, w21, w20", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x66, 0x3B, 0xcb": { @@ -546,6 +2471,32 @@ "Comment": [ "0x3B", "cmp bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "sub w22, w21, w20", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x3B, 0xcb": { @@ -554,6 +2505,28 @@ "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "sub w22, w21, w20", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst w22, w22", + "mrs x23, nzcv", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "db 0x48, 0x3B, 0xcb": { @@ -562,357 +2535,846 @@ "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "sub x20, x5, x7", + "eor x21, x5, x7", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x21, nzcv", + "cmp x5, x7", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x5, x7", + "eor x20, x20, x5", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" ] }, "cmp al, 1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x3C" + "Comment": "0x3C", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sub w21, w20, #0x1 (1)", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp ax, 1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x3D" + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sub w21, w20, #0x1 (1)", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #16", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp eax, 1": { "ExpectedInstructionCount": "19", "Optimal": "No", - "Comment": "0x3D" + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w21, w20, #0x1 (1)", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst w21, w21", + "mrs x22, nzcv", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp rax, 1": { "ExpectedInstructionCount": 18, "Optimal": "Yes", - "Comment": "0x3D" + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x1 (1)", + "eor x21, x4, #0x1", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x21, nzcv", + "cmp x4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x4, #0x1", + "eor x20, x20, x4", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "push ax": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x50" + "Comment": "0x50", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sub x8, x8, #0x2 (2)", + "strh w20, [x8]" + ] }, "push rax": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x50" + "Comment": "0x50", + "ExpectedArm64ASM": [ + "sub x8, x8, #0x8 (8)", + "str x4, [x8]" + ] }, "pop ax": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8f" + "Comment": "0x8f", + "ExpectedArm64ASM": [ + "ldrh w20, [x8]", + "add x8, x8, #0x2 (2)", + "bfxil x4, x20, #0, #16" + ] }, "pop rax": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x8f" + "Comment": "0x8f", + "ExpectedArm64ASM": [ + "ldr x4, [x8]", + "add x8, x8, #0x8 (8)" + ] }, "movsxd rax, ebx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x63" + "Comment": "0x63", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "sxtw x4, w20" + ] }, "push word 1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x68" + "Comment": "0x68", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "sub x8, x8, #0x2 (2)", + "strh w20, [x8]" + ] }, "push qword 1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x68" + "Comment": "0x68", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "sub x8, x8, #0x8 (8)", + "str x20, [x8]" + ] }, "imul ax, bx, 257": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x69" + "Comment": "0x69", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "sxth x20, w20", + "mov w21, #0x101", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #15, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul eax, ebx, 257": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x69" + "Comment": "0x69", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "sxtw x20, w20", + "mov w21, #0x101", + "mul x20, x20, x21", + "asr x21, x20, #32", + "ubfx x4, x20, #0, #32", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #31, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul rax, rbx, 257": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x69" + "Comment": "0x69", + "ExpectedArm64ASM": [ + "mov w20, #0x101", + "mul x4, x7, x20", + "smulh x20, x7, x20", + "mov w21, #0x0", + "strb w21, [x28, #706]", + "strb w21, [x28, #708]", + "asr x22, x4, #63", + "orr w23, wzr, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] }, "push word -1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x6a" + "Comment": "0x6a", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffff", + "sub x8, x8, #0x2 (2)", + "strh w20, [x8]" + ] }, "push dword -1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x6a" + "Comment": "0x6a", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "sub x8, x8, #0x8 (8)", + "str x20, [x8]" + ] }, "push qword -1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x6a" + "Comment": "0x6a", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "sub x8, x8, #0x8 (8)", + "str x20, [x8]" + ] }, "imul ax, bx, 3": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x6b" + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "sxth x20, w20", + "orr w21, wzr, #0x3", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #15, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul eax, ebx, 3": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x6b" + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "sxtw x20, w20", + "orr w21, wzr, #0x3", + "mul x20, x20, x21", + "asr x21, x20, #32", + "ubfx x4, x20, #0, #32", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #31, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul rax, rbx, 3": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x6b" + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x3", + "mul x4, x7, x20", + "smulh x20, x7, x20", + "mov w21, #0x0", + "strb w21, [x28, #706]", + "strb w21, [x28, #708]", + "asr x22, x4, #63", + "orr w23, wzr, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] }, "test al, bl": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x84" + "Comment": "0x84", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w4", + "and w20, w21, w20", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "test ax, bx": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x84" + "Comment": "0x84", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "and w20, w21, w20", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "test eax, ebx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x84" + "Comment": "0x84", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "and w20, w21, w20", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "test rax, rbx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x84" + "Comment": "0x84", + "ExpectedArm64ASM": [ + "and x20, x4, x7", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "xchg bl, cl": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x86" + "Comment": "0x86", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w5", + "bfxil x5, x20, #0, #8", + "bfxil x7, x21, #0, #8" + ] }, "xchg [rax], cl": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x86" + "Comment": "0x86", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "mov w1, w20", + "swpalb w1, w20, [x4]", + "bfxil x5, x20, #0, #8" + ] }, "xchg bx, cx": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w5", + "bfxil x5, x20, #0, #16", + "bfxil x7, x21, #0, #16" + ] }, "xchg [rax], cx": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "mov w1, w20", + "swpalh w1, w20, [x4]", + "bfxil x5, x20, #0, #16" + ] }, "xchg ebx, ecx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x7, x5, #0, #32", + "mov x5, x20" + ] }, "xchg [rax], ecx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "mov w1, w20", + "swpal w1, w5, [x4]" + ] }, "xchg rbx, rcx": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "mov x20, x7", + "mov x7, x5", + "mov x5, x20" + ] }, "xchg [rax], rcx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x87" + "Comment": "0x87", + "ExpectedArm64ASM": [ + "mov x1, x5", + "swpal x1, x5, [x4]" + ] }, "mov [rax], bl": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x88" + "Comment": "0x88", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "strb w20, [x4]" + ] }, "mov [rax], bx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x89" + "Comment": "0x89", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "strh w20, [x4]" + ] }, "mov [rax], ebx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x89" + "Comment": "0x89", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "str w20, [x4]" + ] }, "mov [rax], rbx": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x89" + "Comment": "0x89", + "ExpectedArm64ASM": [ + "str x7, [x4]" + ] }, "mov bl, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8a" + "Comment": "0x8a", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "bfxil x7, x20, #0, #8" + ] }, "mov bx, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8b" + "Comment": "0x8b", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "bfxil x7, x20, #0, #16" + ] }, "mov ebx, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8b" + "Comment": "0x8b", + "ExpectedArm64ASM": [ + "ldr w7, [x4]" + ] }, "mov rbx, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8b" + "Comment": "0x8b", + "ExpectedArm64ASM": [ + "ldr x7, [x4]" + ] }, "mov ax, cs": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #138]", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, cs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #138]" + ] }, "mov rax, cs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #138]" + ] }, "mov ax, es": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #136]", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, es": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #136]" + ] }, "mov rax, es": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #136]" + ] }, "mov ax, ss": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #140]", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, ss": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #140]" + ] }, "mov rax, ss": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #140]" + ] }, "mov ax, ds": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #142]", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, ds": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #142]" + ] }, "mov rax, ds": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "ldrh w4, [x28, #142]" + ] }, "mov ax, gs": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, gs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w4, #0x0" + ] }, "mov rax, gs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w4, #0x0" + ] }, "mov ax, fs": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, fs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w4, #0x0" + ] }, "mov rax, fs": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8c" + "Comment": "0x8c", + "ExpectedArm64ASM": [ + "mov w4, #0x0" + ] }, "lea ax, [rbx+rcx*1 + 0]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "add x20, x5, x7", + "bfxil x4, x20, #0, #16" + ] }, "lea eax, [rbx+rcx*1 + 0]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "add x20, x5, x7", + "lsr x20, x20, #0", + "ubfx x4, x20, #0, #32" + ] }, "lea rax, [rbx+rcx*1 + 0]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "add x4, x5, x7" + ] }, "lea ax, [rbx+rcx*2 + 0]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #1", + "add x20, x20, x7", + "bfxil x4, x20, #0, #16" + ] }, "lea eax, [rbx+rcx*2 + 0]": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #1", + "add x20, x20, x7", + "lsr x20, x20, #0", + "ubfx x4, x20, #0, #32" + ] }, "lea rax, [rbx+rcx*2 + 0]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #1", + "add x4, x20, x7" + ] }, "lea ax, [rbx+rcx*4 + 0]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #2", + "add x20, x20, x7", + "bfxil x4, x20, #0, #16" + ] }, "lea eax, [rbx+rcx*4 + 0]": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #2", + "add x20, x20, x7", + "lsr x20, x20, #0", + "ubfx x4, x20, #0, #32" + ] }, "lea rax, [rbx+rcx*4 + 0]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #2", + "add x4, x20, x7" + ] }, "lea ax, [rbx+rcx*8 + 0]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #3", + "add x20, x20, x7", + "bfxil x4, x20, #0, #16" + ] }, "lea eax, [rbx+rcx*8 + 0]": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #3", + "add x20, x20, x7", + "lsr x20, x20, #0", + "ubfx x4, x20, #0, #32" + ] }, "lea rax, [rbx+rcx*8 + 0]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x8d" + "Comment": "0x8d", + "ExpectedArm64ASM": [ + "lsl x20, x5, #3", + "add x4, x20, x7" + ] }, "mov cs, ax": { "ExpectedInstructionCount": 4, @@ -923,17 +3385,41 @@ "mov es, ax": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x8e" + "Comment": "0x8e", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "strh w20, [x28, #136]", + "ubfx x20, x20, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #152]" + ] }, "mov ss, ax": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x8e" + "Comment": "0x8e", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "strh w20, [x28, #140]", + "ubfx x20, x20, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #160]" + ] }, "mov ds, ax": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x8e" + "Comment": "0x8e", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "strh w20, [x28, #142]", + "ubfx x20, x20, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #164]" + ] }, "mov gs, ax": { "ExpectedInstructionCount": 0, @@ -950,92 +3436,316 @@ "pop word [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8f" + "Comment": "0x8f", + "ExpectedArm64ASM": [ + "ldrh w20, [x8]", + "add x8, x8, #0x2 (2)", + "strh w20, [x4]" + ] }, "pop qword [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x8f" + "Comment": "0x8f", + "ExpectedArm64ASM": [ + "ldr x20, [x8]", + "add x8, x8, #0x8 (8)", + "str x20, [x4]" + ] }, "xchg ax, bx": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x90" + "Comment": "0x90", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w7", + "bfxil x7, x20, #0, #16", + "bfxil x4, x21, #0, #16" + ] }, "xchg eax, ebx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x90" + "Comment": "0x90", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x4, x7, #0, #32", + "mov x7, x20" + ] }, "xchg rax, rbx": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x90" + "Comment": "0x90", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x4, x7", + "mov x7, x20" + ] }, "nop": { "ExpectedInstructionCount": 0, "Optimal": "Yes", - "Comment": "0x90" + "Comment": "0x90", + "ExpectedArm64ASM": [] }, "cbw": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sxtb x20, w20", + "bfxil x4, x20, #0, #16" + ] }, "cwde": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sxth x20, w20", + "ubfx x4, x20, #0, #32" + ] }, "cdqe": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "sxtw x4, w4" + ] }, "cwd": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sbfx x20, x20, #15, #1", + "bfxil x6, x20, #0, #16" + ] }, "cdq": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sbfx x20, x20, #31, #1", + "ubfx x6, x20, #0, #32" + ] }, "cqo": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x98" + "Comment": "0x98", + "ExpectedArm64ASM": [ + "asr x6, x4, #63" + ] }, "fwait": { "ExpectedInstructionCount": 0, "Optimal": "Yes", - "Comment": "0x9b" + "Comment": "0x9b", + "ExpectedArm64ASM": [] }, "pushf": { "ExpectedInstructionCount": 41, "Optimal": "No", - "Comment": "0x9c" + "Comment": "0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "orr x21, x21, x22, lsl #2", + "ldrb w22, [x28, #708]", + "orr x21, x21, x22, lsl #4", + "ldrb w22, [x28, #712]", + "orr x21, x21, x22, lsl #8", + "ldrb w22, [x28, #713]", + "orr x21, x21, x22, lsl #9", + "ldrb w22, [x28, #714]", + "orr x21, x21, x22, lsl #10", + "ubfx x22, x20, #28, #1", + "orr x21, x21, x22, lsl #11", + "ldrb w22, [x28, #716]", + "orr x21, x21, x22, lsl #12", + "ldrb w22, [x28, #718]", + "orr x21, x21, x22, lsl #14", + "ldrb w22, [x28, #720]", + "orr x21, x21, x22, lsl #16", + "ldrb w22, [x28, #721]", + "orr x21, x21, x22, lsl #17", + "ldrb w22, [x28, #722]", + "orr x21, x21, x22, lsl #18", + "ldrb w22, [x28, #723]", + "orr x21, x21, x22, lsl #19", + "ldrb w22, [x28, #724]", + "orr x21, x21, x22, lsl #20", + "ldrb w22, [x28, #725]", + "orr x21, x21, x22, lsl #21", + "and x22, x20, #0xc0000000", + "orr x21, x21, x22, lsr #24", + "orr x21, x21, #0x2", + "sub x8, x8, #0x8 (8)", + "str x21, [x8]", + "str w20, [x28, #728]" + ] }, "pushfq": { "ExpectedInstructionCount": 41, "Optimal": "No", - "Comment": "0x9c" + "Comment": "0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "orr x21, x21, x22, lsl #2", + "ldrb w22, [x28, #708]", + "orr x21, x21, x22, lsl #4", + "ldrb w22, [x28, #712]", + "orr x21, x21, x22, lsl #8", + "ldrb w22, [x28, #713]", + "orr x21, x21, x22, lsl #9", + "ldrb w22, [x28, #714]", + "orr x21, x21, x22, lsl #10", + "ubfx x22, x20, #28, #1", + "orr x21, x21, x22, lsl #11", + "ldrb w22, [x28, #716]", + "orr x21, x21, x22, lsl #12", + "ldrb w22, [x28, #718]", + "orr x21, x21, x22, lsl #14", + "ldrb w22, [x28, #720]", + "orr x21, x21, x22, lsl #16", + "ldrb w22, [x28, #721]", + "orr x21, x21, x22, lsl #17", + "ldrb w22, [x28, #722]", + "orr x21, x21, x22, lsl #18", + "ldrb w22, [x28, #723]", + "orr x21, x21, x22, lsl #19", + "ldrb w22, [x28, #724]", + "orr x21, x21, x22, lsl #20", + "ldrb w22, [x28, #725]", + "orr x21, x21, x22, lsl #21", + "and x22, x20, #0xc0000000", + "orr x21, x21, x22, lsr #24", + "orr x21, x21, #0x2", + "sub x8, x8, #0x8 (8)", + "str x21, [x8]", + "str w20, [x28, #728]" + ] }, "popf": { "ExpectedInstructionCount": 42, "Optimal": "No", - "Comment": "0x9d" + "Comment": "0x9d", + "ExpectedArm64ASM": [ + "ldr x20, [x8]", + "add x8, x8, #0x8 (8)", + "mov w21, #0x202", + "orr x20, x20, x21", + "ubfx x21, x20, #0, #1", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "ubfx x22, x20, #2, #1", + "strb w22, [x28, #706]", + "ubfx x22, x20, #4, #1", + "strb w22, [x28, #708]", + "ubfx x22, x20, #6, #1", + "bfi w21, w22, #30, #1", + "ubfx x22, x20, #7, #1", + "bfi w21, w22, #31, #1", + "ubfx x22, x20, #8, #1", + "strb w22, [x28, #712]", + "ubfx x22, x20, #9, #1", + "strb w22, [x28, #713]", + "ubfx x22, x20, #10, #1", + "strb w22, [x28, #714]", + "ubfx x22, x20, #11, #1", + "bfi w21, w22, #28, #1", + "ubfx x22, x20, #12, #1", + "strb w22, [x28, #716]", + "ubfx x22, x20, #14, #1", + "strb w22, [x28, #718]", + "ubfx x22, x20, #16, #1", + "strb w22, [x28, #720]", + "ubfx x22, x20, #17, #1", + "strb w22, [x28, #721]", + "ubfx x22, x20, #18, #1", + "strb w22, [x28, #722]", + "ubfx x22, x20, #19, #1", + "strb w22, [x28, #723]", + "ubfx x22, x20, #20, #1", + "strb w22, [x28, #724]", + "ubfx x20, x20, #21, #1", + "strb w20, [x28, #725]", + "str w21, [x28, #728]" + ] }, "sahf": { "ExpectedInstructionCount": 20, "Optimal": "No", - "Comment": "0x9e" + "Comment": "0x9e", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #8, #8", + "mov w21, #0x28", + "bic w20, w20, w21", + "orr x20, x20, #0x2", + "ubfx x21, x20, #0, #1", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "ubfx x22, x20, #2, #1", + "strb w22, [x28, #706]", + "ubfx x22, x20, #4, #1", + "strb w22, [x28, #708]", + "ubfx x22, x20, #6, #1", + "bfi w21, w22, #30, #1", + "ubfx x20, x20, #7, #1", + "mov w0, w21", + "bfi w0, w20, #31, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "lahf": { "ExpectedInstructionCount": 16, "Optimal": "Yes", - "Comment": "0x9f" + "Comment": "0x9f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "orr x21, x21, x22, lsl #2", + "ldrb w22, [x28, #708]", + "orr x21, x21, x22, lsl #4", + "and x22, x20, #0xc0000000", + "orr x21, x21, x22, lsr #24", + "orr x21, x21, #0x2", + "bfi x4, x21, #8, #8", + "str w20, [x28, #728]" + ] }, "db 0x48, 0xa1; dq 0x00000000e0000008": { "ExpectedInstructionCount": 5, @@ -1043,6 +3753,13 @@ "Comment": [ "mov rax, [0xe0000008]", "0xa1" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x6264", + "movk x20, #0x3020, lsl #16", + "movk x20, #0x3678, lsl #32", + "movk x20, #0x2c37, lsl #48", + "ldr x4, [x20]" ] }, "db 0x67, 0xa1; dd 0xe0000000": { @@ -1051,6 +3768,11 @@ "Comment": [ "mov eax, [0xe0000000]", "0xa1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x6264", + "movk w20, #0x3020, lsl #16", + "ldr w4, [x20]" ] }, "db 0x48, 0xa3; dq 0x00000000e0000008": { @@ -1059,6 +3781,13 @@ "Comment": [ "mov [0xe0000008], rax", "0xa3" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x6264", + "movk x20, #0x3020, lsl #16", + "movk x20, #0x3678, lsl #32", + "movk x20, #0x2c37, lsl #48", + "str x4, [x20]" ] }, "db 0x67, 0xa3; dd 0xe0000000": { @@ -1067,6 +3796,12 @@ "Comment": [ "mov [0xe0000000], eax", "0xa3" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov w21, #0x6f6d", + "movk w21, #0x7376, lsl #16", + "str w20, [x21]" ] }, "movsb": { @@ -1075,6 +3810,17 @@ "Comment": [ "Direction flag increment/decrement location can be made with a single sbfx", "0xa4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x1", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "ldrb w21, [x10]", + "strb w21, [x11]", + "add x10, x10, x20", + "add x11, x11, x20" ] }, "movsw": { @@ -1083,6 +3829,17 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x2", + "mov x22, #0xfffffffffffffffe", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "ldrh w21, [x10]", + "strh w21, [x11]", + "add x10, x10, x20", + "add x11, x11, x20" ] }, "movsd": { @@ -1091,6 +3848,17 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x4", + "mov x22, #0xfffffffffffffffc", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "ldr w21, [x10]", + "str w21, [x11]", + "add x10, x10, x20", + "add x11, x11, x20" ] }, "movsq": { @@ -1099,27 +3867,162 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x8", + "mov x22, #0xfffffffffffffff8", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "ldr x21, [x10]", + "str x21, [x11]", + "add x10, x10, x20", + "add x11, x11, x20" ] }, "rep movsb": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xa4" + "Comment": "0xa4", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "mov x2, x10", + "cbnz x20, #+0x30", + "cbz x0, #+0x14", + "ldrb w3, [x2], #1", + "strb w3, [x1], #1", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "add x20, x0, x2", + "add x21, x1, x2", + "b #+0x2c", + "cbz x0, #+0x14", + "ldrb w3, [x2], #-1", + "strb w3, [x1], #-1", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "sub x20, x0, x2", + "sub x21, x1, x2", + "mov x11, x20", + "mov x10, x21", + "mov w5, #0x0" + ] }, "rep movsw": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xa5" + "Comment": "0xa5", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "mov x2, x10", + "cbnz x20, #+0x30", + "cbz x0, #+0x14", + "ldrh w3, [x2], #2", + "strh w3, [x1], #2", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "add x20, x0, x2, lsl #1", + "add x21, x1, x2, lsl #1", + "b #+0x2c", + "cbz x0, #+0x14", + "ldrh w3, [x2], #-2", + "strh w3, [x1], #-2", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "sub x20, x0, x2, lsl #1", + "sub x21, x1, x2, lsl #1", + "mov x11, x20", + "mov x10, x21", + "mov w5, #0x0" + ] }, "rep movsd": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xa5" + "Comment": "0xa5", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "mov x2, x10", + "cbnz x20, #+0x30", + "cbz x0, #+0x14", + "ldr w3, [x2], #4", + "str w3, [x1], #4", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "add x20, x0, x2, lsl #2", + "add x21, x1, x2, lsl #2", + "b #+0x2c", + "cbz x0, #+0x14", + "ldr w3, [x2], #-4", + "str w3, [x1], #-4", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "sub x20, x0, x2, lsl #2", + "sub x21, x1, x2, lsl #2", + "mov x11, x20", + "mov x10, x21", + "mov w5, #0x0" + ] }, "rep movsq": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xa5" + "Comment": "0xa5", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "mov x2, x10", + "cbnz x20, #+0x30", + "cbz x0, #+0x14", + "ldr x3, [x2], #8", + "str x3, [x1], #8", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "add x20, x0, x2, lsl #3", + "add x21, x1, x2, lsl #3", + "b #+0x2c", + "cbz x0, #+0x14", + "ldr x3, [x2], #-8", + "str x3, [x1], #-8", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0xc", + "mov x0, x11", + "mov x1, x10", + "mov x2, x5", + "sub x20, x0, x2, lsl #3", + "sub x21, x1, x2, lsl #3", + "mov x11, x20", + "mov x10, x21", + "mov w5, #0x0" + ] }, "cmpsb": { "ExpectedInstructionCount": 31, @@ -1127,6 +4030,39 @@ "Comment": [ "Direction flag increment/decrement location can be made with a single sbfx", "0xa6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x11]", + "ldrb w21, [x10]", + "sub w22, w21, w20", + "uxtb x22, w22", + "ldrb w23, [x28, #714]", + "orr w24, wzr, #0x1", + "mov x25, #0xffffffffffffffff", + "cmp x23, #0x0 (0)", + "csel x23, x24, x25, eq", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "cmpsw": { @@ -1135,6 +4071,39 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa7" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x11]", + "ldrh w21, [x10]", + "sub w22, w21, w20", + "uxth x22, w22", + "ldrb w23, [x28, #714]", + "orr w24, wzr, #0x2", + "mov x25, #0xfffffffffffffffe", + "cmp x23, #0x0 (0)", + "csel x23, x24, x25, eq", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "cmpsd": { @@ -1143,6 +4112,35 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa7" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x11]", + "ldr w21, [x10]", + "sub w22, w21, w20", + "ldrb w23, [x28, #714]", + "orr w24, wzr, #0x4", + "mov x25, #0xfffffffffffffffc", + "cmp x23, #0x0 (0)", + "csel x23, x24, x25, eq", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst w22, w22", + "mrs x23, nzcv", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "cmpsq": { @@ -1151,102 +4149,556 @@ "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", "0xa7" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x11]", + "ldr x21, [x10]", + "sub x22, x21, x20", + "ldrb w23, [x28, #714]", + "orr w24, wzr, #0x8", + "mov x25, #0xfffffffffffffff8", + "cmp x23, #0x0 (0)", + "csel x23, x24, x25, eq", + "add x11, x11, x23", + "add x10, x10, x23", + "eor x23, x21, x20", + "eor x23, x23, x22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst x22, x22", + "mrs x23, nzcv", + "cmp x21, x20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x20, x21, x20", + "eor x21, x22, x21", + "and x20, x20, x21", + "lsr x20, x20, #63", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" ] }, "repz cmpsb": { "ExpectedInstructionCount": 35, "Optimal": "No", - "Comment": "0xa6" + "Comment": "0xa6", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x1", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x78", + "ldrb w21, [x11]", + "ldrb w22, [x10]", + "sub w23, w22, w21", + "uxtb x23, w23", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #24", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #7, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x74" + ] }, "repz cmpsw": { "ExpectedInstructionCount": 35, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x2", + "mov x22, #0xfffffffffffffffe", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x78", + "ldrh w21, [x11]", + "ldrh w22, [x10]", + "sub w23, w22, w21", + "uxth x23, w23", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #16", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #15, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x74" + ] }, "repz cmpsd": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x4", + "mov x22, #0xfffffffffffffffc", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x68", + "ldr w21, [x11]", + "ldr w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst w23, w23", + "mrs x24, nzcv", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #31, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x64" + ] }, "repz cmpsq": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x8", + "mov x22, #0xfffffffffffffff8", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x68", + "ldr x21, [x11]", + "ldr x22, [x10]", + "sub x23, x22, x21", + "eor x24, x22, x21", + "eor x24, x24, x23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst x23, x23", + "mrs x24, nzcv", + "cmp x22, x21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor x21, x22, x21", + "eor x22, x23, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x64" + ] }, "repnz cmpsb": { "ExpectedInstructionCount": 35, "Optimal": "No", - "Comment": "0xa6" + "Comment": "0xa6", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x1", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x78", + "ldrb w21, [x11]", + "ldrb w22, [x10]", + "sub w23, w22, w21", + "uxtb x23, w23", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #24", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #7, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x74" + ] }, "repnz cmpsw": { "ExpectedInstructionCount": 35, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x2", + "mov x22, #0xfffffffffffffffe", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x78", + "ldrh w21, [x11]", + "ldrh w22, [x10]", + "sub w23, w22, w21", + "uxth x23, w23", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #16", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #15, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x74" + ] }, "repnz cmpsd": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x4", + "mov x22, #0xfffffffffffffffc", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x68", + "ldr w21, [x11]", + "ldr w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst w23, w23", + "mrs x24, nzcv", + "cmp w22, w21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w21, w22", + "ubfx x21, x21, #31, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x64" + ] }, "repnz cmpsq": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0xa7" + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "orr w21, wzr, #0x8", + "mov x22, #0xfffffffffffffff8", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "cbz x5, #+0x68", + "ldr x21, [x11]", + "ldr x22, [x10]", + "sub x23, x22, x21", + "eor x24, x22, x21", + "eor x24, x24, x23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst x23, x23", + "mrs x24, nzcv", + "cmp x22, x21", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor x21, x22, x21", + "eor x22, x23, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x64" + ] }, "test al, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0xa8" + "Comment": "0xa8", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "test ax, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0xa9" + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "test eax, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0xa9" + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "test rax, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xa9" + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "and x20, x4, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "stosb": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xaa" + "Comment": "0xaa", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "strb w20, [x11]", + "orr w20, wzr, #0x1", + "mov x21, #0xffffffffffffffff", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x11, x11, x20" + ] }, "stosw": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xab" + "Comment": "0xab", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "strh w20, [x11]", + "orr w20, wzr, #0x2", + "mov x21, #0xfffffffffffffffe", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x11, x11, x20" + ] }, "stosd": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xab" + "Comment": "0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "str w20, [x11]", + "orr w20, wzr, #0x4", + "mov x21, #0xfffffffffffffffc", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x11, x11, x20" + ] }, "stosq": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xab" + "Comment": "0xab", + "ExpectedArm64ASM": [ + "str x4, [x11]", + "orr w20, wzr, #0x8", + "mov x21, #0xfffffffffffffff8", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x11, x11, x20" + ] }, "rep stosb": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0xaa" + "Comment": "0xaa", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldrb w21, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "cbnz x21, #+0x1c", + "cbz x0, #+0x10", + "strb w20, [x1], #1", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "add x11, x11, x5", + "b #+0x18", + "cbz x0, #+0x10", + "strb w20, [x1], #-1", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "sub x11, x11, x5", + "mov w5, #0x0" + ] }, "rep stosw": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0xab" + "Comment": "0xab", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldrb w21, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "cbnz x21, #+0x1c", + "cbz x0, #+0x10", + "strh w20, [x1], #2", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "add x11, x11, x5, lsl #1", + "b #+0x18", + "cbz x0, #+0x10", + "strh w20, [x1], #-2", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "sub x11, x11, x5, lsl #1", + "mov w5, #0x0" + ] }, "rep stosd": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0xab" + "Comment": "0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ldrb w21, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "cbnz x21, #+0x1c", + "cbz x0, #+0x10", + "str w20, [x1], #4", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "add x11, x11, x5, lsl #2", + "b #+0x18", + "cbz x0, #+0x10", + "str w20, [x1], #-4", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "sub x11, x11, x5, lsl #2", + "mov w5, #0x0" + ] }, "rep stosq": { "ExpectedInstructionCount": 16, @@ -1255,127 +4707,638 @@ "Unrolling the loop for faster memset can be done.", "Taking advantage of ARM MOPs instructions can be done", "0xab" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov x0, x5", + "mov x1, x11", + "cbnz x20, #+0x1c", + "cbz x0, #+0x10", + "str x4, [x1], #8", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "add x11, x11, x5, lsl #3", + "b #+0x18", + "cbz x0, #+0x10", + "str x4, [x1], #-8", + "sub x0, x0, #0x1 (1)", + "cbnz x0, #-0x8", + "sub x11, x11, x5, lsl #3", + "mov w5, #0x0" ] }, "lodsb": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xac" + "Comment": "0xac", + "ExpectedArm64ASM": [ + "ldrb w20, [x10]", + "bfxil x4, x20, #0, #8", + "orr w20, wzr, #0x1", + "mov x21, #0xffffffffffffffff", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x10, x10, x20" + ] }, "lodsw": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "ldrh w20, [x10]", + "bfxil x4, x20, #0, #16", + "orr w20, wzr, #0x2", + "mov x21, #0xfffffffffffffffe", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x10, x10, x20" + ] }, "lodsd": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "ldr w4, [x10]", + "orr w20, wzr, #0x4", + "mov x21, #0xfffffffffffffffc", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x10, x10, x20" + ] }, "lodsq": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "ldr x4, [x10]", + "orr w20, wzr, #0x8", + "mov x21, #0xfffffffffffffff8", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "add x10, x10, x20" + ] }, "rep lodsb": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0xac" + "Comment": "0xac", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "mov x21, #0xffffffffffffffff", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x18", + "ldrb w21, [x10]", + "bfxil x4, x21, #0, #8", + "sub x5, x5, #0x1 (1)", + "add x10, x10, x20", + "b #-0x14" + ] }, "rep lodsw": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "mov x21, #0xfffffffffffffffe", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x18", + "ldrh w21, [x10]", + "bfxil x4, x21, #0, #16", + "sub x5, x5, #0x1 (1)", + "add x10, x10, x20", + "b #-0x14" + ] }, "rep lodsd": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x4", + "mov x21, #0xfffffffffffffffc", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x14", + "ldr w4, [x10]", + "sub x5, x5, #0x1 (1)", + "add x10, x10, x20", + "b #-0x10" + ] }, "rep lodsq": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0xad" + "Comment": "0xad", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x8", + "mov x21, #0xfffffffffffffff8", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x14", + "ldr x4, [x10]", + "sub x5, x5, #0x1 (1)", + "add x10, x10, x20", + "b #-0x10" + ] }, "scasb": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0xae" + "Comment": "0xae", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldrb w21, [x11]", + "sub w22, w20, w21", + "uxtb x22, w22", + "orr w23, wzr, #0x1", + "mov x24, #0xffffffffffffffff", + "ldrb w25, [x28, #714]", + "cmp x25, #0x0 (0)", + "csel x23, x23, x24, eq", + "add x11, x11, x23", + "eor w23, w20, w21", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, w21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "scasw": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldrh w21, [x11]", + "sub w22, w20, w21", + "uxth x22, w22", + "orr w23, wzr, #0x2", + "mov x24, #0xfffffffffffffffe", + "ldrb w25, [x28, #714]", + "cmp x25, #0x0 (0)", + "csel x23, x23, x24, eq", + "add x11, x11, x23", + "eor w23, w20, w21", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, w21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "scasd": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ldr w21, [x11]", + "sub w22, w20, w21", + "orr w23, wzr, #0x4", + "mov x24, #0xfffffffffffffffc", + "ldrb w25, [x28, #714]", + "cmp x25, #0x0 (0)", + "csel x23, x23, x24, eq", + "add x11, x11, x23", + "eor w23, w20, w21", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst w22, w22", + "mrs x23, nzcv", + "cmp w20, w21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "and w20, w21, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "scasq": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldr x20, [x11]", + "sub x21, x4, x20", + "orr w22, wzr, #0x8", + "mov x23, #0xfffffffffffffff8", + "ldrb w24, [x28, #714]", + "cmp x24, #0x0 (0)", + "csel x22, x22, x23, eq", + "add x11, x11, x22", + "eor x22, x4, x20", + "eor x22, x22, x21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst x21, x21", + "mrs x22, nzcv", + "cmp x4, x20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x20, x4, x20", + "eor x21, x21, x4", + "and x20, x20, x21", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "repz scasb": { "ExpectedInstructionCount": 34, "Optimal": "No", - "Comment": "0xae" + "Comment": "0xae", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "mov x21, #0xffffffffffffffff", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x74", + "uxtb x21, w4", + "ldrb w22, [x11]", + "sub w23, w21, w22", + "uxtb x23, w23", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #24", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #7, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x70" + ] }, "repz scasw": { "ExpectedInstructionCount": 34, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "mov x21, #0xfffffffffffffffe", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x74", + "uxth x21, w4", + "ldrh w22, [x11]", + "sub w23, w21, w22", + "uxth x23, w23", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #16", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #15, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x70" + ] }, "repz scasd": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x4", + "mov x21, #0xfffffffffffffffc", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x64", + "ubfx x21, x4, #0, #32", + "ldr w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst w23, w23", + "mrs x24, nzcv", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #31, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x60" + ] }, "repz scasq": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x8", + "mov x21, #0xfffffffffffffff8", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x60", + "ldr x21, [x11]", + "sub x22, x4, x21", + "eor x23, x4, x21", + "eor x23, x23, x22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst x22, x22", + "mrs x23, nzcv", + "cmp x4, x21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x21, x4, x21", + "eor x22, x22, x4", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x21, x23, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbnz x22, #-0x5c" + ] }, "repnz scasb": { "ExpectedInstructionCount": 34, "Optimal": "No", - "Comment": "0xae" + "Comment": "0xae", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "mov x21, #0xffffffffffffffff", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x74", + "uxtb x21, w4", + "ldrb w22, [x11]", + "sub w23, w21, w22", + "uxtb x23, w23", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #24", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #7, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x70" + ] }, "repnz scasw": { "ExpectedInstructionCount": 34, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "mov x21, #0xfffffffffffffffe", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x74", + "uxth x21, w4", + "ldrh w22, [x11]", + "sub w23, w21, w22", + "uxth x23, w23", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "lsl w24, w23, #16", + "and x24, x24, #0x80000000", + "cmp x23, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #15, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x70" + ] }, "repnz scasd": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x4", + "mov x21, #0xfffffffffffffffc", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x64", + "ubfx x21, x4, #0, #32", + "ldr w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "eor w24, w24, w23", + "ubfx x24, x24, #4, #1", + "strb w24, [x28, #708]", + "eor x24, x23, #0x1", + "strb w24, [x28, #706]", + "tst w23, w23", + "mrs x24, nzcv", + "cmp w21, w22", + "cset x25, lo", + "orr x24, x24, x25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w22, w21", + "ubfx x21, x21, #31, #1", + "orr x21, x24, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x60" + ] }, "repnz scasq": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xaf" + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x8", + "mov x21, #0xfffffffffffffff8", + "ldrb w22, [x28, #714]", + "cmp x22, #0x0 (0)", + "csel x20, x20, x21, eq", + "cbz x5, #+0x60", + "ldr x21, [x11]", + "sub x22, x4, x21", + "eor x23, x4, x21", + "eor x23, x23, x22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "tst x22, x22", + "mrs x23, nzcv", + "cmp x4, x21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x21, x4, x21", + "eor x22, x22, x4", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x21, x23, x21, lsl #28", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx x22, x21, #30, #1", + "str w21, [x28, #728]", + "cbz x22, #-0x5c" + ] }, "mov al, 0xff": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xb0" + "Comment": "0xb0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xff", + "bfxil x4, x20, #0, #8" + ] }, "mov al, 0x82": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xb0" + "Comment": "0xb0", + "ExpectedArm64ASM": [ + "mov w20, #0x82", + "bfxil x4, x20, #0, #8" + ] }, "mov ax, 0xffff": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xb8" + "Comment": "0xb8", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffff", + "bfxil x4, x20, #0, #16" + ] }, "mov ax, 0x4243": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xb8" + "Comment": "0xb8", + "ExpectedArm64ASM": [ + "mov w20, #0x4243", + "bfxil x4, x20, #0, #16" + ] }, "mov eax, 0xffffffff": { "ExpectedInstructionCount": 2, @@ -1383,42 +5346,87 @@ "Comment": [ "movz+movk doesn't turn in to bitfield move", "0xb8" + ], + "ExpectedArm64ASM": [ + "mov w4, #0xffff", + "movk w4, #0xffff, lsl #16" ] }, "mov eax, 0x44454647": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xb8" + "Comment": "0xb8", + "ExpectedArm64ASM": [ + "mov w4, #0x4647", + "movk w4, #0x4445, lsl #16" + ] }, "mov rax, 0xffffffffffffffff": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xb8" + "Comment": "0xb8", + "ExpectedArm64ASM": [ + "mov x4, #0xffffffffffffffff" + ] }, "mov rax, 0x5152535455565758": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0xb8" + "Comment": "0xb8", + "ExpectedArm64ASM": [ + "mov x4, #0x5758", + "movk x4, #0x5556, lsl #16", + "movk x4, #0x5354, lsl #32", + "movk x4, #0x5152, lsl #48" + ] }, "xlat": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xd7" + "Comment": "0xd7", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldrb w20, [x7, x20, sxtx]", + "bfxil x4, x20, #0, #8" + ] }, "cmc": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0xf5" + "Comment": "0xf5", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "eor x21, x21, #0x1", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] }, "clc": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0xf8" + "Comment": "0xf8", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "stc": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0xf9" + "Comment": "0xf9", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "cli": { "ExpectedInstructionCount": 7, @@ -1435,12 +5443,20 @@ "cld": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xfc" + "Comment": "0xfc", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "strb w20, [x28, #714]" + ] }, "std": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xfd" + "Comment": "0xfd", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "strb w20, [x28, #714]" + ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 03c31892c..27527f6b1 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -15,862 +15,4010 @@ "add al, 1": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP1 0x80 /0" + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w21, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "or al, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP1 0x80 /1" + "Comment": "GROUP1 0x80 /1", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "orr w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "adc al, 1": { "ExpectedInstructionCount": 32, "Optimal": "No", - "Comment": "GROUP1 0x80 /2" + "Comment": "GROUP1 0x80 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxtb x22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #24", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "bic w20, w20, w23", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb al, 1": { "ExpectedInstructionCount": 32, "Optimal": "No", - "Comment": "GROUP1 0x80 /3" + "Comment": "GROUP1 0x80 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "uxtb x22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb x20, w20", + "eor w23, w22, #0x1", + "eor w23, w23, w20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w20, #24", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr x21, x23, x21, lsl #29", + "eor w23, w22, #0x1", + "eor w20, w20, w22", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "and al, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP1 0x80 /4" + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "and w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "sub al, 1": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP1 0x80 /5" + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xor al, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP1 0x80 /6" + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "eor w20, w20, #0x1", + "bfxil x4, x20, #0, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "cmp al, 1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "GROUP1 0x80 /7" + "Comment": "GROUP1 0x80 /7", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sub w21, w20, #0x1 (1)", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #24", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add ax, 256": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP1 0x81 /0" + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "add w21, w20, #0x100 (256)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x100", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #16", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w21, #0x100 (256)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x100", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add eax, 256": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x81 /0" + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "add w4, w20, #0x100 (256)", + "eor w21, w20, #0x100", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w4, #0x100 (256)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x100", + "eor w20, w4, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add rax, 256": { "ExpectedInstructionCount": 19, "Optimal": "Yes", - "Comment": "GROUP1 0x81 /0" + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x100 (256)", + "eor x21, x20, #0x100", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x4, #0x100 (256)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x100", + "eor x20, x4, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "or eax, 256": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x81 /1" + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "orr w4, w20, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "or rax, 256": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x81 /1" + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "adc eax, 256": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x81 /2" + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x100", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "add w4, w22, w20", + "eor w20, w22, #0x100", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, #0x100 (256)", + "cset x23, lo", + "cmp w4, #0x100 (256)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x100", + "eor w22, w4, w22", + "bic w21, w22, w21", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "adc rax, 256": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x81 /2" + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x100", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "add x4, x22, x20", + "eor x20, x22, #0x100", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, #0x100 (256)", + "cset x23, lo", + "cmp x4, #0x100 (256)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x100", + "eor x22, x4, x22", + "bic x21, x22, x21", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb eax, 256": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x81 /3" + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x100", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "sub w4, w22, w20", + "eor w20, w22, #0x100", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, w22", + "cset x23, hi", + "cmp w4, w22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x100", + "eor w22, w4, w22", + "and w21, w21, w22", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb rax, 256": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x81 /3" + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x100", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "sub x4, x22, x20", + "eor x20, x22, #0x100", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, x22", + "cset x23, hi", + "cmp x4, x22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x100", + "eor x22, x4, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "and eax, 256": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x81 /4" + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "and w4, w20, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "and rax, 256": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x81 /4" + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "and x4, x4, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "sub eax, 256": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x81 /5" + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w4, w20, #0x100 (256)", + "eor w21, w20, #0x100", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w20, #0x100 (256)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x100", + "eor w20, w4, w20", + "and w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub rax, 256": { "ExpectedInstructionCount": 19, "Optimal": "Yes", - "Comment": "GROUP1 0x81 /5" + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x100 (256)", + "eor x21, x20, #0x100", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x20, #0x100 (256)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x100", + "eor x20, x4, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xor eax, 256": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x81 /6" + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "eor w4, w20, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "xor rax, 256": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x81 /6" + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x100", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "cmp eax, 256": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x81 /7" + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w21, w20, #0x100 (256)", + "eor w22, w20, #0x100", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst w21, w21", + "mrs x22, nzcv", + "cmp w20, #0x100 (256)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x100", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp rax, 256": { "ExpectedInstructionCount": 18, "Optimal": "Yes", - "Comment": "GROUP1 0x81 /7" + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x100 (256)", + "eor x21, x4, #0x100", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x21, nzcv", + "cmp x4, #0x100 (256)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x4, #0x100", + "eor x20, x20, x4", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add ax, 1": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP1 0x83 /0" + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "lsl w22, w21, #16", + "and x22, x22, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x23, eq", + "orr x22, x22, x23, lsl #30", + "cmp w21, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add eax, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x83 /0" + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "add w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "add rax, 1": { "ExpectedInstructionCount": 19, "Optimal": "Yes", - "Comment": "GROUP1 0x83 /0" + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "or eax, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x83 /1" + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "orr w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "or rax, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x83 /1" + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "adc eax, 1": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x83 /2" + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "add w4, w22, w20", + "eor w20, w22, #0x1", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, #0x1 (1)", + "cset x23, lo", + "cmp w4, #0x1 (1)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x1", + "eor w22, w4, w22", + "bic w21, w22, w21", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "adc rax, 1": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x83 /2" + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "add x4, x22, x20", + "eor x20, x22, #0x1", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, #0x1 (1)", + "cset x23, lo", + "cmp x4, #0x1 (1)", + "cset x24, ls", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x1", + "eor x22, x4, x22", + "bic x21, x22, x21", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb eax, 1": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x83 /3" + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add w20, w20, w21", + "ubfx x22, x4, #0, #32", + "sub w4, w22, w20", + "eor w20, w22, #0x1", + "eor w20, w20, w4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "cmp w4, w22", + "cset x23, hi", + "cmp w4, w22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor w21, w22, #0x1", + "eor w22, w4, w22", + "and w21, w21, w22", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "sbb rax, 1": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP1 0x83 /3" + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "add x20, x20, x21", + "mov x22, x4", + "sub x4, x22, x20", + "eor x20, x22, #0x1", + "eor x20, x20, x4", + "ubfx x20, x20, #4, #1", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, x22", + "cset x23, hi", + "cmp x4, x22", + "cset x24, hs", + "cmp x21, #0x1 (1)", + "csel x21, x24, x23, eq", + "orr x20, x20, x21, lsl #29", + "eor x21, x22, #0x1", + "eor x22, x4, x22", + "and x21, x21, x22", + "lsr x21, x21, #63", + "orr x20, x20, x21, lsl #28", + "str w20, [x28, #728]" + ] }, "and eax, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x83 /4" + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "and w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "and rax, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x83 /4" + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "and x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "sub eax, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x83 /5" + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst w4, w4", + "mrs x21, nzcv", + "cmp w20, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "and w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sub rax, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x83 /5" + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "tst x4, x4", + "mrs x21, nzcv", + "cmp x20, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xor eax, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP1 0x83 /6" + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "eor w4, w20, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "xor rax, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP1 0x83 /6" + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x1", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "cmp eax, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP1 0x83 /7" + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w21, w20, #0x1 (1)", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst w21, w21", + "mrs x22, nzcv", + "cmp w20, #0x1 (1)", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmp rax, 1": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "GROUP1 0x83 /7" + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x1 (1)", + "eor x21, x4, #0x1", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x21, nzcv", + "cmp x4, #0x1 (1)", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x4, #0x1", + "eor x20, x20, x4", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "rol al, 2": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP2 0xC0 /0" + "Comment": "GROUP2 0xC0 /0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, #30", + "bfxil x4, x20, #0, #8", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "ror al, 2": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP2 0xC0 /1" + "Comment": "GROUP2 0xC0 /1", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "bfi w20, w20, #8, #8", + "ror w20, w20, #2", + "bfxil x4, x20, #0, #8", + "ubfx x20, x20, #7, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "rcl al, 2": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "GROUP2 0xC0 /2" + "Comment": "GROUP2 0xC0 /2", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "orr w23, wzr, #0x2", + "mov w24, #0x0", + "bfi x24, x20, #55, #8", + "bfi x24, x22, #63, #1", + "bfi x24, x20, #46, #8", + "bfi x24, x22, #54, #1", + "bfi x24, x20, #37, #8", + "bfi x24, x22, #45, #1", + "bfi x24, x20, #28, #8", + "bfi x24, x22, #36, #1", + "bfi x24, x20, #19, #8", + "bfi x24, x22, #27, #1", + "mov x0, x24", + "bfxil x0, x20, #0, #8", + "mov x20, x0", + "ror x24, x20, #62", + "bfxil x4, x24, #0, #8", + "ror x20, x20, #61", + "ubfx x20, x20, #0, #1", + "cmp x23, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx x22, x24, #7, #1", + "eor x20, x22, x20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr al, 2": { "ExpectedInstructionCount": 22, "Optimal": "No", - "Comment": "GROUP2 0xC0 /3" + "Comment": "GROUP2 0xC0 /3", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "orr w23, wzr, #0x2", + "bfi x20, x22, #8, #1", + "bfi x20, x20, #9, #9", + "bfi x20, x20, #18, #18", + "bfi x20, x20, #36, #9", + "lsr x24, x20, #2", + "bfxil x4, x24, #0, #8", + "lsr x20, x20, #1", + "ubfx x20, x20, #0, #1", + "cmp w23, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x24, #7, #1", + "ubfx x22, x24, #6, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl al, 2": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xC0 /4" + "Comment": "GROUP2 0xC0 /4", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "lsl w21, w20, #2", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "mov w22, #0x0", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #6, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shr al, 2": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "GROUP2 0xC0 /5" + "Comment": "GROUP2 0xC0 /5", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "lsr w21, w20, #2", + "bfxil x4, x21, #0, #8", + "mov w22, #0x0", + "ldr w23, [x28, #728]", + "ubfx x23, x23, #28, #1", + "lsl w24, w21, #24", + "and x24, x24, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "ubfx x20, x20, #1, #1", + "orr x20, x24, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "orr x20, x20, x23, lsl #28", + "str w20, [x28, #728]" + ] }, "sar al, 2": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xC0 /7" + "Comment": "GROUP2 0xC0 /7", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sxtb x20, w20", + "asr x21, x20, #2", + "bfxil x4, x21, #0, #8", + "mov w22, #0x0", + "lsl x23, x21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #1, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "rol ax, 2": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP2 0xC1 /0" + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #30", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "rol eax, 2": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "GROUP2 0xC1 /0" + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ror w4, w20, #30", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "rol rax, 2": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "GROUP2 0xC1 /0" + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "ror x4, x4, #62", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "ror ax, 2": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP2 0xC1 /1" + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #2", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #15, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "ror eax, 2": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "GROUP2 0xC1 /1" + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ror w4, w20, #2", + "ubfx x20, x4, #31, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "ror rax, 2": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "GROUP2 0xC1 /1" + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "ror x4, x4, #2", + "lsr x20, x4, #63", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x20, x21, x20, lsl #29", + "str w20, [x28, #728]" + ] }, "rcl ax, 2": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP2 0xC1 /2" + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "orr w23, wzr, #0x2", + "mov w24, #0x0", + "bfi x24, x20, #47, #16", + "bfi x24, x22, #63, #1", + "bfi x24, x20, #30, #16", + "bfi x24, x22, #46, #1", + "bfi x24, x20, #13, #16", + "bfi x24, x22, #29, #1", + "mov x0, x24", + "bfxil x0, x20, #0, #16", + "mov x20, x0", + "ror x24, x20, #62", + "bfxil x4, x24, #0, #16", + "ror x20, x20, #61", + "ubfx x20, x20, #0, #1", + "cmp x23, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx x22, x24, #15, #1", + "eor x20, x22, x20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcl eax, 2": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "GROUP2 0xC1 /2" + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsl w24, w21, #2", + "lsr w25, w21, #31", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "lsl x25, x23, #1", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x24, x24, x25", + "ubfx x4, x24, #0, #32", + "lsr w21, w21, #30", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w20, w21, w23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x22, x24, #31, #1", + "eor x21, x22, x21", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcl rax, 2": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP2 0xC1 /2" + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "mov x21, x4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsl x24, x21, #2", + "lsr x25, x21, #63", + "mov w26, #0x0", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hi", + "orr x24, x24, x25", + "lsl x25, x23, #1", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x4, x24, x25", + "lsr x21, x21, #62", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "lsr x22, x4, #63", + "eor x21, x22, x21", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr ax, 2": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "GROUP2 0xC1 /3" + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "orr w23, wzr, #0x2", + "bfi x20, x22, #16, #1", + "bfi x20, x20, #17, #17", + "bfi x20, x20, #34, #17", + "lsr x24, x20, #2", + "bfxil x4, x24, #0, #16", + "lsr x20, x20, #1", + "ubfx x20, x20, #0, #1", + "cmp w23, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x24, #15, #1", + "ubfx x22, x24, #14, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr eax, 2": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP2 0xC1 /3" + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsr w24, w21, #2", + "lsl w25, w21, #31", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "lsl x25, x23, #30", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x24, x24, x25", + "ubfx x4, x24, #0, #32", + "lsr w21, w21, #1", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w20, w21, w23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x24, #31, #1", + "ubfx x22, x24, #30, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr rax, 2": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "GROUP2 0xC1 /3" + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x2", + "mov x21, x4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsr x24, x21, #2", + "lsl x25, x21, #63", + "mov w26, #0x0", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hi", + "orr x24, x24, x25", + "lsl x25, x23, #62", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x4, x24, x25", + "lsr x21, x21, #1", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "lsr x21, x4, #63", + "ubfx x22, x4, #62, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl ax, 2": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xC1 /4" + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsl w21, w20, #2", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "mov w22, #0x0", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #14, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shl eax, 2": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP2 0xC1 /4" + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsl w4, w20, #2", + "mov w21, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x20, x20, #30, #1", + "orr w20, w22, w20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shl rax, 2": { "ExpectedInstructionCount": 11, "Optimal": "Yes", - "Comment": "GROUP2 0xC1 /4" + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, #2", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #62, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shr ax, 2": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "GROUP2 0xC1 /5" + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w21, w20, #2", + "bfxil x4, x21, #0, #16", + "mov w22, #0x0", + "ldr w23, [x28, #728]", + "ubfx x23, x23, #28, #1", + "lsl w24, w21, #16", + "and x24, x24, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "ubfx x20, x20, #1, #1", + "orr x20, x24, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "orr x20, x20, x23, lsl #28", + "str w20, [x28, #728]" + ] }, "shr eax, 2": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xC1 /5" + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w4, w20, #2", + "mov w21, #0x0", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #28, #1", + "tst w4, w4", + "mrs x23, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w23, w20, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "orr w20, w20, w22, lsl #28", + "str w20, [x28, #728]" + ] }, "shr rax, 2": { "ExpectedInstructionCount": 14, "Optimal": "Yes", - "Comment": "GROUP2 0xC1 /5" + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, #2", + "mov w21, #0x0", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #28, #1", + "tst x4, x4", + "mrs x23, nzcv", + "ubfx x20, x20, #1, #1", + "orr x20, x23, x20, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "orr x20, x20, x22, lsl #28", + "str w20, [x28, #728]" + ] }, "sar ax, 2": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xC1 /7" + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sxth x20, w20", + "asr x21, x20, #2", + "bfxil x4, x21, #0, #16", + "mov w22, #0x0", + "lsl x23, x21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #1, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "sar eax, 2": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP2 0xC1 /7" + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "asr w4, w20, #2", + "mov w21, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w22, w20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "sar rax, 2": { "ExpectedInstructionCount": 11, "Optimal": "Yes", - "Comment": "GROUP2 0xC1 /7" + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, #2", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "rol al, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd0 /0" + "Comment": "GROUP2 0xd0 /0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, #31", + "bfxil x4, x20, #0, #8", + "ubfx x21, x20, #0, #1", + "ldr w22, [x28, #728]", + "and x22, x22, #0xc0000000", + "orr x22, x22, x21, lsl #29", + "ubfx x20, x20, #7, #1", + "eor w20, w20, w21", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "ror al, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xd0 /1" + "Comment": "GROUP2 0xd0 /1", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "bfi w20, w20, #8, #8", + "ror w20, w20, #1", + "bfxil x4, x20, #0, #8", + "ubfx x21, x20, #7, #1", + "ldr w22, [x28, #728]", + "and x22, x22, #0xc0000000", + "orr x22, x22, x21, lsl #29", + "ubfx x20, x20, #6, #1", + "eor w20, w20, w21", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "rcl al, 1": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xd0 /2" + "Comment": "GROUP2 0xd0 /2", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsl w23, w20, #1", + "orr w22, w23, w22", + "ubfx x20, x20, #7, #1", + "bfxil x4, x22, #0, #8", + "bfi w21, w20, #29, #1", + "ubfx x22, x22, #7, #1", + "eor w20, w22, w20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr al, 1": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP2 0xd0 /3" + "Comment": "GROUP2 0xd0 /3", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "ubfx x23, x20, #1, #7", + "mov w0, w23", + "bfi w0, w22, #7, #1", + "uxtb w22, w0", + "ubfx x20, x20, #0, #1", + "bfxil x4, x22, #0, #8", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x22, #7, #1", + "ubfx x22, x22, #6, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl al, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP2 0xd0 /4" + "Comment": "GROUP2 0xd0 /4", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "lsl w21, w20, #1", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "mov w22, #0x0", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x24, x20, #7, #1", + "orr x23, x23, x24, lsl #29", + "eor x24, x21, #0x1", + "strb w24, [x28, #706]", + "strb w22, [x28, #708]", + "eor w20, w21, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shr al, 1": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP2 0xd0 /5" + "Comment": "GROUP2 0xd0 /5", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "lsr w21, w20, #1", + "bfxil x4, x21, #0, #8", + "mov w22, #0x0", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x24, x20, #0, #1", + "orr x23, x23, x24, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sar al, 1": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xd0 /7" + "Comment": "GROUP2 0xd0 /7", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sxtb x20, w20", + "asr w21, w20, #1", + "bfxil x4, x21, #0, #8", + "mov w22, #0x0", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #0, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "rol ax, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xd1 /0" + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #31", + "bfxil x4, x20, #0, #16", + "ubfx x21, x20, #0, #1", + "ldr w22, [x28, #728]", + "and x22, x22, #0xc0000000", + "orr x22, x22, x21, lsl #29", + "ubfx x20, x20, #15, #1", + "eor w20, w20, w21", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "rol eax, 1": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP2 0xd1 /0" + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ror w4, w20, #31", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x21, x21, x20, lsl #29", + "ubfx x22, x4, #31, #1", + "eor w20, w22, w20", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "rol rax, 1": { "ExpectedInstructionCount": 9, "Optimal": "Yes", - "Comment": "GROUP2 0xd1 /0" + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "ror x4, x4, #63", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x21, x21, x20, lsl #29", + "lsr x22, x4, #63", + "eor x20, x22, x20", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "ror ax, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xd1 /1" + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #1", + "bfxil x4, x20, #0, #16", + "ubfx x21, x20, #15, #1", + "ldr w22, [x28, #728]", + "and x22, x22, #0xc0000000", + "orr x22, x22, x21, lsl #29", + "ubfx x20, x20, #14, #1", + "eor w20, w20, w21", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "ror eax, 1": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP2 0xd1 /1" + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ror w4, w20, #1", + "ubfx x20, x4, #31, #1", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x21, x21, x20, lsl #29", + "ubfx x22, x4, #30, #1", + "eor w20, w22, w20", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "ror rax, 1": { "ExpectedInstructionCount": 9, "Optimal": "Yes", - "Comment": "GROUP2 0xd1 /1" + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "ror x4, x4, #1", + "lsr x20, x4, #63", + "ldr w21, [x28, #728]", + "and x21, x21, #0xc0000000", + "orr x21, x21, x20, lsl #29", + "ubfx x22, x4, #62, #1", + "eor x20, x22, x20", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "rcl ax, 1": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xd1 /2" + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsl w23, w20, #1", + "orr w22, w23, w22", + "ubfx x20, x20, #15, #1", + "bfxil x4, x22, #0, #16", + "bfi w21, w20, #29, #1", + "ubfx x22, x22, #15, #1", + "eor w20, w22, w20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcl eax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd1 /2" + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsl w23, w20, #1", + "orr w4, w23, w22", + "ubfx x20, x20, #31, #1", + "bfi w21, w20, #29, #1", + "ubfx x22, x4, #31, #1", + "eor w20, w22, w20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcl rax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd1 /2" + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsl x23, x20, #1", + "orr x4, x23, x22", + "lsr x20, x20, #63", + "bfi w21, w20, #29, #1", + "lsr x22, x4, #63", + "eor x20, x22, x20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr ax, 1": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xd1 /3" + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "ubfx x23, x20, #1, #15", + "lsl w22, w22, #15", + "orr w22, w23, w22", + "bfxil x4, x22, #0, #16", + "ubfx x20, x20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x22, #15, #1", + "ubfx x22, x22, #14, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr eax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd1 /3" + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "extr w4, w22, w20, #1", + "ubfx x20, x20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x4, #31, #1", + "ubfx x22, x4, #30, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr rax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd1 /3" + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "extr x4, x22, x20, #1", + "ubfx x20, x20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "lsr x21, x4, #63", + "ubfx x22, x4, #62, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl ax, 1": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP2 0xd1 /4" + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsl w21, w20, #1", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "mov w22, #0x0", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x24, x20, #15, #1", + "orr x23, x23, x24, lsl #29", + "eor x24, x21, #0x1", + "strb w24, [x28, #706]", + "strb w22, [x28, #708]", + "eor w20, w21, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shl eax, 1": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xd1 /4" + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsl w4, w20, #1", + "mov w21, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x23, x20, #31, #1", + "orr w22, w22, w23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "eor w20, w4, w20", + "ubfx x20, x20, #31, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "shl rax, 1": { "ExpectedInstructionCount": 14, "Optimal": "Yes", - "Comment": "GROUP2 0xd1 /4" + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, #1", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "lsr x23, x20, #63", + "orr x22, x22, x23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "eor x20, x4, x20", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shr ax, 1": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP2 0xd1 /5" + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w21, w20, #1", + "bfxil x4, x21, #0, #16", + "mov w22, #0x0", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x24, x20, #0, #1", + "orr x23, x23, x24, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shr eax, 1": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xd1 /5" + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w4, w20, #1", + "mov w21, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x23, x20, #0, #1", + "orr w22, w22, w23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "ubfx x20, x20, #31, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "shr rax, 1": { "ExpectedInstructionCount": 13, "Optimal": "Yes", - "Comment": "GROUP2 0xd1 /5" + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, #1", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x23, x20, #0, #1", + "orr x22, x22, x23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "sar ax, 1": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xd1 /7" + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sxth x20, w20", + "asr w21, w20, #1", + "bfxil x4, x21, #0, #16", + "mov w22, #0x0", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x20, x20, #0, #1", + "orr x20, x23, x20, lsl #29", + "eor x21, x21, #0x1", + "strb w21, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] }, "sar eax, 1": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP2 0xd1 /7" + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "asr w4, w20, #1", + "mov w21, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x20, x20, #0, #1", + "orr w20, w22, w20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "sar rax, 1": { "ExpectedInstructionCount": 11, "Optimal": "Yes", - "Comment": "GROUP2 0xd1 /7" + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, #1", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #0, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "rol al, cl": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP2 0xd2 /0" + "Comment": "GROUP2 0xd2 /0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "orr w22, wzr, #0x20", + "sub w22, w22, w21", + "ror w20, w20, w22", + "bfxil x4, x20, #0, #8", + "ldr w22, [x28, #728]", + "and x23, x22, #0xc0000000", + "ubfx x24, x20, #0, #1", + "orr x23, x23, x24, lsl #29", + "ubfx x20, x20, #7, #1", + "eor w20, w20, w24", + "orr x20, x23, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x22, x20, eq", + "str w20, [x28, #728]" + ] }, "ror al, cl": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP2 0xd2 /1" + "Comment": "GROUP2 0xd2 /1", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, w21", + "bfxil x4, x20, #0, #8", + "ldr w22, [x28, #728]", + "and x23, x22, #0xc0000000", + "ubfx x24, x20, #7, #1", + "orr x23, x23, x24, lsl #29", + "ubfx x20, x20, #6, #1", + "eor w20, w20, w24", + "orr x20, x23, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x22, x20, eq", + "str w20, [x28, #728]" + ] }, "rcl al, cl": { "ExpectedInstructionCount": 39, "Optimal": "No", - "Comment": "GROUP2 0xd2 /2" + "Comment": "GROUP2 0xd2 /2", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "and w20, w20, #0x1f", + "mov w24, #0x0", + "bfi x24, x21, #55, #8", + "bfi x24, x23, #63, #1", + "bfi x24, x21, #46, #8", + "bfi x24, x23, #54, #1", + "bfi x24, x21, #37, #8", + "bfi x24, x23, #45, #1", + "bfi x24, x21, #28, #8", + "bfi x24, x23, #36, #1", + "bfi x24, x21, #19, #8", + "bfi x24, x23, #27, #1", + "mov x0, x24", + "bfxil x0, x21, #0, #8", + "mov x21, x0", + "orr w24, wzr, #0x40", + "sub w24, w24, w20", + "ror x24, x21, x24", + "bfxil x4, x24, #0, #8", + "orr w25, wzr, #0x3f", + "sub x25, x25, x20", + "ror x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x23, x21, x23, hs", + "bfi w22, w23, #29, #1", + "ubfx x23, x22, #28, #1", + "ubfx x24, x24, #7, #1", + "eor x21, x24, x21", + "cmp x20, #0x0 (0)", + "csel x20, x23, x21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr al, cl": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP2 0xd2 /3" + "Comment": "GROUP2 0xd2 /3", + "ExpectedArm64ASM": [ + "uxtb x20, w5", + "uxtb x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "and w20, w20, #0x1f", + "bfi x21, x23, #8, #1", + "bfi x21, x21, #9, #9", + "bfi x21, x21, #18, #18", + "bfi x21, x21, #36, #9", + "lsr x24, x21, x20", + "bfxil x4, x24, #0, #8", + "sub w25, w20, #0x1 (1)", + "lsr x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x24, #7, #1", + "ubfx x22, x24, #6, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl al, cl": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP2 0xd2 /4" + "Comment": "GROUP2 0xd2 /4", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w5", + "lsl w22, w20, w21", + "bfxil x4, x22, #0, #8", + "uxtb x22, w22", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "orr w25, wzr, #0x8", + "sub x25, x25, x21", + "lsr w25, w20, w25", + "ubfx x25, x25, #0, #1", + "orr x24, x24, x25, lsl #29", + "eor x25, x22, #0x1", + "ldrb w26, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr x20, x24, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "shr al, cl": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP2 0xd2 /5" + "Comment": "GROUP2 0xd2 /5", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w5", + "lsr w22, w20, w21", + "bfxil x4, x22, #0, #8", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "sub x25, x21, #0x1 (1)", + "lsr w25, w20, w25", + "ubfx x25, x25, #0, #1", + "orr x24, x24, x25, lsl #29", + "eor x25, x22, #0x1", + "ldrb w26, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx x20, x20, #7, #1", + "orr x20, x24, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "sar al, cl": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "GROUP2 0xd2 /7" + "Comment": "GROUP2 0xd2 /7", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w5", + "sxtb x20, w20", + "asr w22, w20, w21", + "bfxil x4, x22, #0, #8", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "sub x25, x21, #0x1 (1)", + "lsr x20, x20, x25", + "ubfx x20, x20, #0, #1", + "orr x20, x24, x20, lsl #29", + "eor x22, x22, #0x1", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x22, x24, x22, eq", + "strb w22, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "rol ax, cl": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "GROUP2 0xd3 /0" + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #16, #16", + "orr w22, wzr, #0x20", + "sub w22, w22, w21", + "ror w20, w20, w22", + "bfxil x4, x20, #0, #16", + "ldr w22, [x28, #728]", + "and x23, x22, #0xc0000000", + "ubfx x24, x20, #0, #1", + "orr x23, x23, x24, lsl #29", + "ubfx x20, x20, #15, #1", + "eor w20, w20, w24", + "orr x20, x23, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x22, x20, eq", + "str w20, [x28, #728]" + ] }, "rol eax, cl": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xd3 /0" + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x5, #0, #32", + "and w21, w21, #0x1f", + "orr w22, wzr, #0x20", + "sub w22, w22, w21", + "ror w4, w20, w22", + "ldr w20, [x28, #728]", + "and x22, x20, #0xc0000000", + "ubfx x23, x4, #0, #1", + "orr x22, x22, x23, lsl #29", + "ubfx x24, x4, #31, #1", + "eor w23, w24, w23", + "orr x22, x22, x23, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x20, x22, eq", + "str w20, [x28, #728]" + ] }, "rol rax, cl": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xd3 /0" + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "and x20, x5, #0x3f", + "orr w21, wzr, #0x40", + "sub x21, x21, x20", + "ror x4, x4, x21", + "ldr w21, [x28, #728]", + "and x22, x21, #0xc0000000", + "ubfx x23, x4, #0, #1", + "orr x22, x22, x23, lsl #29", + "lsr x24, x4, #63", + "eor x23, x24, x23", + "orr x22, x22, x23, lsl #28", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] }, "ror ax, cl": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xd3 /1" + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #16, #16", + "ror w20, w20, w21", + "bfxil x4, x20, #0, #16", + "ldr w22, [x28, #728]", + "and x23, x22, #0xc0000000", + "ubfx x24, x20, #15, #1", + "orr x23, x23, x24, lsl #29", + "ubfx x20, x20, #14, #1", + "eor w20, w20, w24", + "orr x20, x23, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x22, x20, eq", + "str w20, [x28, #728]" + ] }, "ror eax, cl": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xd3 /1" + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x5, #0, #32", + "and w21, w21, #0x1f", + "ror w4, w20, w21", + "ldr w20, [x28, #728]", + "and x22, x20, #0xc0000000", + "ubfx x23, x4, #31, #1", + "orr x22, x22, x23, lsl #29", + "ubfx x24, x4, #30, #1", + "eor w23, w24, w23", + "orr x22, x22, x23, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x20, x22, eq", + "str w20, [x28, #728]" + ] }, "ror rax, cl": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xd3 /1" + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "and x20, x5, #0x3f", + "ror x4, x4, x20", + "ldr w21, [x28, #728]", + "and x22, x21, #0xc0000000", + "lsr x23, x4, #63", + "orr x22, x22, x23, lsl #29", + "ubfx x24, x4, #62, #1", + "eor x23, x24, x23", + "orr x22, x22, x23, lsl #28", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] }, "rcl ax, cl": { "ExpectedInstructionCount": 35, "Optimal": "No", - "Comment": "GROUP2 0xd3 /2" + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "and w20, w20, #0x1f", + "mov w24, #0x0", + "bfi x24, x21, #47, #16", + "bfi x24, x23, #63, #1", + "bfi x24, x21, #30, #16", + "bfi x24, x23, #46, #1", + "bfi x24, x21, #13, #16", + "bfi x24, x23, #29, #1", + "mov x0, x24", + "bfxil x0, x21, #0, #16", + "mov x21, x0", + "orr w24, wzr, #0x40", + "sub w24, w24, w20", + "ror x24, x21, x24", + "bfxil x4, x24, #0, #16", + "orr w25, wzr, #0x3f", + "sub x25, x25, x20", + "ror x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x23, x21, x23, hs", + "bfi w22, w23, #29, #1", + "ubfx x23, x22, #28, #1", + "ubfx x24, x24, #15, #1", + "eor x21, x24, x21", + "cmp x20, #0x0 (0)", + "csel x20, x23, x21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcl eax, cl": { "ExpectedInstructionCount": 34, "Optimal": "No", - "Comment": "GROUP2 0xd3 /2" + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsl w24, w21, w20", + "mov w25, #0x21", + "sub w25, w25, w20", + "lsr w25, w21, w25", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "sub w25, w20, #0x1 (1)", + "lsl x25, x23, x25", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x24, x24, x25", + "ubfx x4, x24, #0, #32", + "orr w25, wzr, #0x20", + "sub w25, w25, w20", + "lsr w21, w21, w25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w23, w21, w23, hs", + "bfi w22, w23, #29, #1", + "ubfx x23, x22, #28, #1", + "ubfx x24, x24, #31, #1", + "eor x21, x24, x21", + "cmp x20, #0x0 (0)", + "csel x20, x23, x21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcl rax, cl": { "ExpectedInstructionCount": 32, "Optimal": "No", - "Comment": "GROUP2 0xd3 /2" + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsl x23, x20, x5", + "mov w24, #0x41", + "sub x24, x24, x5", + "lsr x24, x20, x24", + "mov w25, #0x0", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hi", + "orr x23, x23, x24", + "sub x24, x5, #0x1 (1)", + "lsl x24, x22, x24", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hs", + "orr x4, x23, x24", + "orr w23, wzr, #0x40", + "sub x23, x23, x5", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "cmp x5, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx x22, x21, #28, #1", + "lsr x23, x4, #63", + "eor x20, x23, x20", + "cmp x5, #0x0 (0)", + "csel x20, x22, x20, eq", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr ax, cl": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "GROUP2 0xd3 /3" + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "uxth x20, w5", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "and w20, w20, #0x1f", + "bfi x21, x23, #16, #1", + "bfi x21, x21, #17, #17", + "bfi x21, x21, #34, #17", + "lsr x24, x21, x20", + "bfxil x4, x24, #0, #16", + "sub w25, w20, #0x1 (1)", + "lsr x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x24, #15, #1", + "ubfx x22, x24, #14, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "rcr eax, cl": { "ExpectedInstructionCount": 37, "Optimal": "No", - "Comment": "GROUP2 0xd3 /3" + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "lsr w24, w21, w20", + "mov w25, #0x21", + "sub w25, w25, w20", + "lsl w25, w21, w25", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "orr w25, wzr, #0x20", + "sub w25, w25, w20", + "lsl x25, x23, x25", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x24, x24, x25", + "ubfx x4, x24, #0, #32", + "sub w25, w20, #0x1 (1)", + "lsr w21, w21, w25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w21, w21, w23, hs", + "mov w0, w22", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "ubfx x22, x21, #28, #1", + "ubfx x23, x24, #31, #1", + "ubfx x24, x24, #30, #1", + "eor x23, x23, x24", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rcr rax, cl": { "ExpectedInstructionCount": 33, "Optimal": "No", - "Comment": "GROUP2 0xd3 /3" + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "lsr x23, x20, x5", + "mov w24, #0x41", + "sub x24, x24, x5", + "lsl x24, x20, x24", + "mov w25, #0x0", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hi", + "orr x23, x23, x24", + "orr w24, wzr, #0x40", + "sub x24, x24, x5", + "lsl x24, x22, x24", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hs", + "orr x4, x23, x24", + "sub x23, x5, #0x1 (1)", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "cmp x5, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "ubfx x21, x20, #28, #1", + "lsr x22, x4, #63", + "ubfx x23, x4, #62, #1", + "eor x22, x22, x23", + "cmp x5, #0x0 (0)", + "csel x21, x21, x22, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] }, "shl ax, cl": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "GROUP2 0xd3 /4" + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w5", + "lsl w22, w20, w21", + "bfxil x4, x22, #0, #16", + "uxth x22, w22", + "ldr w23, [x28, #728]", + "orr w24, wzr, #0x10", + "lsl w25, w22, #16", + "and x25, x25, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x26, eq", + "orr x25, x25, x26, lsl #30", + "sub x24, x24, x21", + "lsr w24, w20, w24", + "ubfx x24, x24, #0, #1", + "orr x24, x25, x24, lsl #29", + "eor x25, x22, #0x1", + "ldrb w26, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr x20, x24, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "shl eax, cl": { "ExpectedInstructionCount": 22, "Optimal": "No", - "Comment": "GROUP2 0xd3 /4" + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x5, #0, #32", + "lsl w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "orr w24, wzr, #0x20", + "sub x24, x24, x21", + "lsr w24, w20, w24", + "ubfx x24, x24, #0, #1", + "orr w23, w23, w24, lsl #29", + "eor x24, x4, #0x1", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x24, x25, x24, eq", + "strb w24, [x28, #706]", + "eor w20, w20, w4", + "ubfx x20, x20, #31, #1", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] }, "shl rax, cl": { "ExpectedInstructionCount": 21, "Optimal": "Yes", - "Comment": "GROUP2 0xd3 /4" + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "orr w23, wzr, #0x40", + "sub x23, x23, x5", + "lsr x23, x20, x23", + "ubfx x23, x23, #0, #1", + "orr x22, x22, x23, lsl #29", + "eor x23, x4, #0x1", + "ldrb w24, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x23, x24, x23, eq", + "strb w23, [x28, #706]", + "eor x20, x20, x4", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "cmp x5, #0x0 (0)", + "csel x20, x21, x20, eq", + "str w20, [x28, #728]" + ] }, "shr ax, cl": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP2 0xd3 /5" + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w5", + "lsr w22, w20, w21", + "bfxil x4, x22, #0, #16", + "ldr w23, [x28, #728]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "sub x25, x21, #0x1 (1)", + "lsr w25, w20, w25", + "ubfx x25, x25, #0, #1", + "orr x24, x24, x25, lsl #29", + "eor x25, x22, #0x1", + "ldrb w26, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx x20, x20, #15, #1", + "orr x20, x24, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "shr eax, cl": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "GROUP2 0xd3 /5" + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x5, #0, #32", + "lsr w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "sub x24, x21, #0x1 (1)", + "lsr w24, w20, w24", + "ubfx x24, x24, #0, #1", + "orr w23, w23, w24, lsl #29", + "eor x24, x4, #0x1", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x24, x25, x24, eq", + "strb w24, [x28, #706]", + "eor w20, w20, w4", + "ubfx x20, x20, #31, #1", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] }, "shr rax, cl": { "ExpectedInstructionCount": 20, "Optimal": "Yes", - "Comment": "GROUP2 0xd3 /5" + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "sub x23, x5, #0x1 (1)", + "lsr x23, x20, x23", + "ubfx x23, x23, #0, #1", + "orr x22, x22, x23, lsl #29", + "eor x23, x4, #0x1", + "ldrb w24, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x23, x24, x23, eq", + "strb w23, [x28, #706]", + "eor x20, x20, x4", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "cmp x5, #0x0 (0)", + "csel x20, x21, x20, eq", + "str w20, [x28, #728]" + ] }, "sar ax, cl": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "GROUP2 0xd3 /7" + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w5", + "sxth x20, w20", + "asr w22, w20, w21", + "bfxil x4, x22, #0, #16", + "ldr w23, [x28, #728]", + "lsl w24, w22, #16", + "and x24, x24, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x25, eq", + "orr x24, x24, x25, lsl #30", + "sub x25, x21, #0x1 (1)", + "lsr x20, x20, x25", + "ubfx x20, x20, #0, #1", + "orr x20, x24, x20, lsl #29", + "eor x22, x22, #0x1", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x22, x24, x22, eq", + "strb w22, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "sar eax, cl": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "GROUP2 0xd3 /7" + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x5, #0, #32", + "asr w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "sub x24, x21, #0x1 (1)", + "lsr w20, w20, w24", + "ubfx x20, x20, #0, #1", + "orr w20, w23, w20, lsl #29", + "eor x23, x4, #0x1", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x23, x24, x23, eq", + "strb w23, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] }, "sar rax, cl": { "ExpectedInstructionCount": 17, "Optimal": "Yes", - "Comment": "GROUP2 0xd3 /7" + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "sub x23, x5, #0x1 (1)", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "ldrb w23, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x22, x23, x22, eq", + "strb w22, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x20, x21, x20, eq", + "str w20, [x28, #728]" + ] }, "test bl, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf6 /0" + "Comment": "GROUP2 0xf6 /0", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "not bl": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP2 0xf6 /2" + "Comment": "GROUP2 0xf6 /2", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "eor x20, x20, #0xff", + "bfxil x7, x20, #0, #8" + ] }, "neg bl": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP2 0xf6 /3" + "Comment": "GROUP2 0xf6 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "uxtb x21, w7", + "neg w22, w21", + "bfxil x7, x22, #0, #8", + "uxtb x22, w22", + "eor x23, x20, x21", + "eor x23, x23, x22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp x20, x21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x21, x20, x21", + "eor x20, x22, x20", + "and x20, x21, x20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "mul bl": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf6 /4" + "Comment": "GROUP2 0xf6 /4", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #8, #8", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "orr w22, wzr, #0x30000000", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] }, "imul bl": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xf6 /5" + "Comment": "GROUP2 0xf6 /5", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "sxtb x20, w20", + "sxtb x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "sbfx x21, x20, #8, #8", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #7, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "div bl": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xf6 /6" + "Comment": "GROUP2 0xf6 /6", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxth x21, w4", + "uxth w0, w21", + "uxth w1, w20", + "udiv w22, w0, w1", + "uxth w0, w21", + "uxth w1, w20", + "udiv w2, w0, w1", + "msub w20, w2, w1, w0", + "mov x0, x22", + "bfi x0, x20, #8, #8", + "mov x20, x0", + "bfxil x4, x20, #0, #16" + ] }, "idiv bl": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP2 0xf6 /7" + "Comment": "GROUP2 0xf6 /7", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxth x21, w4", + "sxth x21, w21", + "sxtb x20, w20", + "sdiv x22, x21, x20", + "sdiv x0, x21, x20", + "msub x20, x0, x20, x21", + "mov x0, x22", + "bfi x0, x20, #8, #8", + "mov x20, x0", + "bfxil x4, x20, #0, #16" + ] }, "test bx, 1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf7 /0" + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl w21, w20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "test ebx, 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP2 0xf7 /0" + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "and w20, w20, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "test rbx, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP2 0xf7 /0" + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "and x20, x7, #0x1", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] }, "not bx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP2 0xf7 /1" + "Comment": "GROUP2 0xf7 /1", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "eor x20, x20, #0xffff", + "bfxil x7, x20, #0, #16" + ] }, "not ebx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP2 0xf7 /1" + "Comment": "GROUP2 0xf7 /1", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "eor x20, x20, #0xffffffff", + "ubfx x7, x20, #0, #32" + ] }, "not rbx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP2 0xf7 /1" + "Comment": "GROUP2 0xf7 /1", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "eor x7, x7, x20" + ] }, "neg bx": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP2 0xf7 /2" + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "uxth x21, w7", + "neg w22, w21", + "bfxil x7, x22, #0, #16", + "uxth x22, w22", + "eor x23, x20, x21", + "eor x23, x23, x22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp x20, x21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x21, x20, x21", + "eor x20, x22, x20", + "and x20, x21, x20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "neg ebx": { "ExpectedInstructionCount": 20, "Optimal": "No", - "Comment": "GROUP2 0xf7 /2" + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ubfx x21, x7, #0, #32", + "neg w7, w21", + "eor x22, x20, x21", + "eor x22, x22, x7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst w7, w7", + "mrs x22, nzcv", + "cmp x20, x21", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x21, x20, x21", + "eor x20, x7, x20", + "and x20, x21, x20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "neg rbx": { "ExpectedInstructionCount": 20, "Optimal": "No", - "Comment": "GROUP2 0xf7 /2" + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov x21, x7", + "neg x7, x21", + "eor x22, x20, x21", + "eor x22, x22, x7", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x7, #0x1", + "strb w22, [x28, #706]", + "tst x7, x7", + "mrs x22, nzcv", + "cmp x20, x21", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x21, x20, x21", + "eor x20, x7, x20", + "and x20, x21, x20", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "mul bx": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "GROUP2 0xf7 /3" + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #16, #16", + "bfxil x6, x20, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "orr w22, wzr, #0x30000000", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] }, "mul ebx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf7 /3" + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "mul x20, x20, x21", + "ubfx x4, x20, #0, #32", + "lsr x6, x20, #32", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "strb w20, [x28, #706]", + "orr w21, wzr, #0x30000000", + "cmp x6, #0x0 (0)", + "csel x20, x20, x21, eq", + "str w20, [x28, #728]" + ] }, "mul rbx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP2 0xf7 /3" + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x7, x20", + "umulh x6, x7, x20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "strb w20, [x28, #706]", + "orr w21, wzr, #0x30000000", + "cmp x6, #0x0 (0)", + "csel x20, x20, x21, eq", + "str w20, [x28, #728]" + ] }, "imul bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "GROUP2 0xf7 /5" + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "sxth x20, w20", + "sxth x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "sbfx x21, x20, #16, #16", + "bfxil x6, x21, #0, #16", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #15, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul ebx": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "GROUP2 0xf7 /5" + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "sxtw x20, w20", + "sxtw x21, w4", + "mul x20, x20, x21", + "ubfx x4, x20, #0, #32", + "lsr x6, x20, #32", + "asr x21, x20, #32", + "sxtw x20, w20", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #31, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP2 0xf7 /5" + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x7, x20", + "smulh x6, x7, x20", + "mov w20, #0x0", + "strb w20, [x28, #706]", + "strb w20, [x28, #708]", + "asr x21, x4, #63", + "orr w22, wzr, #0x30000000", + "cmp x6, x21", + "csel x20, x20, x22, eq", + "str w20, [x28, #728]" + ] }, "div bx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf7 /6" + "Comment": "GROUP2 0xf7 /6", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "uxth x22, w6", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "udiv w23, w0, w20", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "udiv w1, w0, w20", + "msub w20, w1, w20, w0", + "bfxil x4, x23, #0, #16", + "bfxil x6, x20, #0, #16" + ] }, "div ebx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "GROUP2 0xf7 /6" + "Comment": "GROUP2 0xf7 /6", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ubfx x22, x6, #0, #32", + "mov x0, x21", + "bfi x0, x22, #32, #32", + "udiv x23, x0, x20", + "ubfx x4, x23, #0, #32", + "mov x0, x21", + "bfi x0, x22, #32, #32", + "udiv x1, x0, x20", + "msub x20, x1, x20, x0", + "ubfx x6, x20, #0, #32" + ] }, "div rbx": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP2 0xf7 /6" + "Comment": "GROUP2 0xf7 /6", + "ExpectedArm64ASM": [ + "mov x20, x4", + "cbz x6, #+0x28", + "mov x0, x6", + "mov x1, x20", + "mov x2, x7", + "ldr x3, [x28, #1688]", + "str x30, [sp, #-16]!", + "blr x3", + "ldr x30, [sp], #16", + "mov x4, x0", + "b #+0x8", + "udiv x4, x20, x7", + "cbz x6, #+0x28", + "mov x0, x6", + "mov x1, x20", + "mov x2, x7", + "ldr x3, [x28, #1704]", + "str x30, [sp, #-16]!", + "blr x3", + "ldr x30, [sp], #16", + "mov x6, x0", + "b #+0xc", + "udiv x0, x20, x7", + "msub x6, x0, x7, x20" + ] }, "idiv bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xf7 /7" + "Comment": "GROUP2 0xf7 /7", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "uxth x22, w6", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "sxth w1, w20", + "sdiv w23, w0, w1", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "sxth w1, w20", + "sdiv w2, w0, w1", + "msub w20, w2, w1, w0", + "bfxil x4, x23, #0, #16", + "bfxil x6, x20, #0, #16" + ] }, "idiv ebx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "GROUP2 0xf7 /7" + "Comment": "GROUP2 0xf7 /7", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ubfx x22, x6, #0, #32", + "mov x0, x21", + "bfi x0, x22, #32, #32", + "sxtw x1, w20", + "sdiv x23, x0, x1", + "ubfx x4, x23, #0, #32", + "mov x0, x21", + "bfi x0, x22, #32, #32", + "sxtw x2, w20", + "sdiv x1, x0, x2", + "msub x20, x1, x2, x0", + "ubfx x6, x20, #0, #32" + ] }, "idiv rbx": { "ExpectedInstructionCount": 28, "Optimal": "No", - "Comment": "GROUP2 0xf7 /7" + "Comment": "GROUP2 0xf7 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x0, x20, #63", + "eor x0, x0, x6", + "cbz x0, #+0x28", + "mov x0, x6", + "mov x1, x20", + "mov x2, x7", + "ldr x3, [x28, #1696]", + "str x30, [sp, #-16]!", + "blr x3", + "ldr x30, [sp], #16", + "mov x4, x0", + "b #+0x8", + "sdiv x4, x20, x7", + "asr x0, x20, #63", + "eor x0, x0, x6", + "cbz x0, #+0x28", + "mov x0, x6", + "mov x1, x20", + "mov x2, x7", + "ldr x3, [x28, #1712]", + "str x30, [sp, #-16]!", + "blr x3", + "ldr x30, [sp], #16", + "mov x6, x0", + "b #+0xc", + "sdiv x0, x20, x7", + "msub x6, x0, x7, x20" + ] }, "inc al": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP3 0xfe /0" + "Comment": "GROUP3 0xfe /0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec al": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP3 0xfe /1" + "Comment": "GROUP3 0xfe /1", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "uxtb x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #24", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "inc ax": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP4 0xfe /0" + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "inc eax": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP4 0xfe /0" + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "add w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "tst w4, w4", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "bic w20, w20, w22", + "ubfx x20, x20, #31, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "inc rax": { "ExpectedInstructionCount": 19, "Optimal": "Yes", - "Comment": "GROUP4 0xfe /0" + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "tst x4, x4", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "bic x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec ax": { "ExpectedInstructionCount": 24, "Optimal": "No", - "Comment": "GROUP4 0xfe /1" + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec eax": { "ExpectedInstructionCount": 19, "Optimal": "No", - "Comment": "GROUP4 0xfe /1" + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "sub w4, w20, #0x1 (1)", + "eor w21, w20, #0x1", + "eor w21, w21, w4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "tst w4, w4", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor w22, w20, #0x1", + "eor w20, w4, w20", + "and w20, w22, w20", + "ubfx x20, x20, #31, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec rax": { "ExpectedInstructionCount": 19, "Optimal": "Yes", - "Comment": "GROUP4 0xfe /1" + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "eor x21, x20, #0x1", + "eor x21, x21, x4", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x4, #0x1", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx x21, x21, #29, #1", + "tst x4, x4", + "mrs x22, nzcv", + "orr w21, w22, w21, lsl #29", + "eor x22, x20, #0x1", + "eor x20, x4, x20", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "push ax": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP4 0xff /6" + "Comment": "GROUP4 0xff /6", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "sub x8, x8, #0x2 (2)", + "strh w20, [x8]" + ] }, "push rax": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP4 0xff /6" + "Comment": "GROUP4 0xff /6", + "ExpectedArm64ASM": [ + "sub x8, x8, #0x8 (8)", + "str x4, [x8]" + ] }, "mov byte [rax], 0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP11 0xc6 /0" + "Comment": "GROUP11 0xc6 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "strb w20, [x4]" + ] }, "mov word [rax], 0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "strh w20, [x4]" + ] }, "mov dword [rax], 0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "str w20, [x4]" + ] }, "mov qword [rax], 0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "str x20, [x4]" + ] }, "mov byte [rax], 1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP11 0xc6 /0" + "Comment": "GROUP11 0xc6 /0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "strb w20, [x4]" + ] }, "mov word [rax], 1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "strh w20, [x4]" + ] }, "mov dword [rax], 1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "str w20, [x4]" + ] }, "mov qword [rax], 1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP11 0xc7 /0" + "Comment": "GROUP11 0xc7 /0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "str x20, [x4]" + ] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 2b177f736..903f93e7a 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -11,107 +11,658 @@ "push es": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x06" + "Comment": "0x06", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #136]", + "str w21, [x20]" + ] }, "pop es": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x07" + "Comment": "0x07", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "strh w21, [x28, #136]", + "ubfx x20, x21, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #152]" + ] }, "push cs": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0e" + "Comment": "0x0e", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #138]", + "str w21, [x20]" + ] }, "push ss": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x16" + "Comment": "0x16", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #140]", + "str w21, [x20]" + ] }, "pop ss": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x17" + "Comment": "0x17", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "strh w21, [x28, #140]", + "ubfx x20, x21, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #160]" + ] }, "push ds": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x1e" + "Comment": "0x1e", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #142]", + "str w21, [x20]" + ] }, "pop ds": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x1f" + "Comment": "0x1f", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "strh w21, [x28, #142]", + "ubfx x20, x21, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #164]" + ] }, "daa": { "ExpectedInstructionCount": 70, "Optimal": "No", - "Comment": "0x27" + "Comment": "0x27", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ldrb w22, [x28, #708]", + "mov w23, w4", + "uxtb x23, w23", + "mov w24, #0x0", + "bfi w20, w24, #29, #1", + "str w20, [x28, #728]", + "and x20, x23, #0xf", + "cmp x20, #0x9 (9)", + "cset x20, hi", + "orr x20, x22, x20", + "cbnz x20, #+0x10", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "b #+0x38", + "add x20, x23, #0x6 (6)", + "mov w22, w4", + "mov w0, w22", + "bfxil w0, w20, #0, #8", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "ldr w20, [x28, #728]", + "ubfx x22, x20, #29, #1", + "orr w22, w21, w22", + "bfi w20, w22, #29, #1", + "orr w22, wzr, #0x1", + "strb w22, [x28, #708]", + "str w20, [x28, #728]", + "cmp x23, #0x99 (153)", + "cset x20, hi", + "orr x20, x21, x20", + "cbnz x20, #+0x20", + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]", + "b #+0x3c", + "mov w20, w4", + "uxtb x20, w20", + "add x20, x20, #0x60 (96)", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #8", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] }, "das": { "ExpectedInstructionCount": 70, "Optimal": "No", - "Comment": "0x2f" + "Comment": "0x2f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ldrb w22, [x28, #708]", + "mov w23, w4", + "uxtb x23, w23", + "mov w24, #0x0", + "bfi w20, w24, #29, #1", + "str w20, [x28, #728]", + "and x20, x23, #0xf", + "cmp x20, #0x9 (9)", + "cset x20, hi", + "orr x20, x22, x20", + "cbnz x20, #+0x10", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "b #+0x38", + "sub x20, x23, #0x6 (6)", + "mov w22, w4", + "mov w0, w22", + "bfxil w0, w20, #0, #8", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "ldr w20, [x28, #728]", + "ubfx x22, x20, #29, #1", + "orr w22, w21, w22", + "bfi w20, w22, #29, #1", + "orr w22, wzr, #0x1", + "strb w22, [x28, #708]", + "str w20, [x28, #728]", + "cmp x23, #0x99 (153)", + "cset x20, hi", + "orr x20, x21, x20", + "cbnz x20, #+0x20", + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]", + "b #+0x3c", + "mov w20, w4", + "uxtb x20, w20", + "sub x20, x20, #0x60 (96)", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #8", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] }, "aaa": { "ExpectedInstructionCount": 36, "Optimal": "No", - "Comment": "0x37" + "Comment": "0x37", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #708]", + "mov w21, w4", + "uxtb x21, w21", + "mov w22, w4", + "uxth x22, w22", + "and x21, x21, #0xf", + "cmp x21, #0x9 (9)", + "cset x21, hi", + "orr x20, x20, x21", + "cbnz x20, #+0x38", + "mov w20, #0xff0f", + "and x20, x22, x20", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "bfi w21, w20, #29, #1", + "strb w20, [x28, #708]", + "str w21, [x28, #728]", + "b #+0x38", + "add x20, x22, #0x106 (262)", + "mov w21, #0xff0f", + "and x20, x20, x21", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "bfi w21, w20, #29, #1", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "aas": { "ExpectedInstructionCount": 37, "Optimal": "No", - "Comment": "0x3f" + "Comment": "0x3f", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #708]", + "mov w21, w4", + "uxtb x21, w21", + "mov w22, w4", + "uxth x22, w22", + "and x21, x21, #0xf", + "cmp x21, #0x9 (9)", + "cset x21, hi", + "orr x20, x20, x21", + "cbnz x20, #+0x38", + "mov w20, #0xff0f", + "and x20, x22, x20", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "bfi w21, w20, #29, #1", + "strb w20, [x28, #708]", + "str w21, [x28, #728]", + "b #+0x3c", + "sub x20, x22, #0x6 (6)", + "sub x20, x20, #0x100 (256)", + "mov w21, #0xff0f", + "and x20, x20, x21", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "orr w20, wzr, #0x1", + "ldr w21, [x28, #728]", + "bfi w21, w20, #29, #1", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "inc ax": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "0x40" + "Comment": "0x40", + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxth x20, w20", + "add w21, w20, #0x1 (1)", + "mov w22, w4", + "bfxil w22, w21, #0, #16", + "bfxil x4, x22, #0, #32", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "inc eax": { "ExpectedInstructionCount": 20, "Optimal": "No", - "Comment": "0x40" + "Comment": "0x40", + "ExpectedArm64ASM": [ + "mov w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #32", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "tst w21, w21", + "mrs x23, nzcv", + "orr w22, w23, w22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "bic w20, w20, w23", + "ubfx x20, x20, #31, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec ax": { "ExpectedInstructionCount": 27, "Optimal": "No", - "Comment": "0x48" + "Comment": "0x48", + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxth x20, w20", + "sub w21, w20, #0x1 (1)", + "mov w22, w4", + "bfxil w22, w21, #0, #16", + "bfxil x4, x22, #0, #32", + "uxth x21, w21", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "lsl w23, w21, #16", + "and x23, x23, #0x80000000", + "cmp x21, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "orr x22, x23, x22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "dec eax": { "ExpectedInstructionCount": 20, "Optimal": "No", - "Comment": "0x48" + "Comment": "0x48", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #32", + "eor w22, w20, #0x1", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx x22, x22, #29, #1", + "tst w21, w21", + "mrs x23, nzcv", + "orr w22, w23, w22, lsl #29", + "eor w23, w20, #0x1", + "eor w20, w21, w20", + "and w20, w23, w20", + "ubfx x20, x20, #31, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "pusha": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x60" + "Comment": "0x60", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x21, x20, #0x4 (4)", + "mov w22, w4", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w5", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w6", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w7", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "str w20, [x21]", + "sub x20, x21, #0x4 (4)", + "mov w21, w9", + "str w21, [x20]", + "sub x20, x20, #0x4 (4)", + "mov w21, w10", + "str w21, [x20]", + "sub x20, x20, #0x4 (4)", + "mov w21, w11", + "str w21, [x20]", + "bfxil x8, x20, #0, #32" + ] }, "pushad": { "ExpectedInstructionCount": "25", "Optimal": "No", - "Comment": "0x60" + "Comment": "0x60", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x21, x20, #0x4 (4)", + "mov w22, w4", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w5", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w6", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "mov w22, w7", + "str w22, [x21]", + "sub x21, x21, #0x4 (4)", + "str w20, [x21]", + "sub x20, x21, #0x4 (4)", + "mov w21, w9", + "str w21, [x20]", + "sub x20, x20, #0x4 (4)", + "mov w21, w10", + "str w21, [x20]", + "sub x20, x20, #0x4 (4)", + "mov w21, w11", + "str w21, [x20]", + "bfxil x8, x20, #0, #32" + ] }, "popa": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x61" + "Comment": "0x61", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "bfxil x11, x21, #0, #32", + "add x21, x20, #0x4 (4)", + "ldr w20, [x20, #4]", + "bfxil x10, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x9, x21, #0, #32", + "add x21, x20, #0x8 (8)", + "ldr w20, [x20, #8]", + "bfxil x7, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x6, x21, #0, #32", + "add x21, x20, #0x4 (4)", + "ldr w20, [x20, #4]", + "bfxil x5, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x4, x21, #0, #32", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32" + ] }, "popad": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x61" + "Comment": "0x61", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "bfxil x11, x21, #0, #32", + "add x21, x20, #0x4 (4)", + "ldr w20, [x20, #4]", + "bfxil x10, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x9, x21, #0, #32", + "add x21, x20, #0x8 (8)", + "ldr w20, [x20, #8]", + "bfxil x7, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x6, x21, #0, #32", + "add x21, x20, #0x4 (4)", + "ldr w20, [x20, #4]", + "bfxil x5, x20, #0, #32", + "add x20, x21, #0x4 (4)", + "ldr w21, [x21, #4]", + "bfxil x4, x21, #0, #32", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32" + ] }, "aam": { "ExpectedInstructionCount": 29, "Optimal": "No", - "Comment": "0xd4" + "Comment": "0xd4", + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxtb x20, w20", + "mov w21, #0xa", + "udiv x22, x20, x21", + "udiv x2, x20, x21", + "msub x20, x2, x21, x20", + "lsl x21, x22, #8", + "add x20, x21, x20", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] }, "aad": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0xd5" + "Comment": "0xd5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxtb x20, w20", + "mov w21, w4", + "uxth x21, w21", + "lsr w21, w21, #8", + "mov w22, #0xa", + "mul x21, x21, x22", + "add x20, x20, x21", + "and x20, x20, #0xff", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] }, "db 0xd4, 0x40": { "ExpectedInstructionCount": 29, @@ -119,6 +670,37 @@ "Comment": [ "aam with a different immediate byte base", "0xd4" + ], + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxtb x20, w20", + "orr w21, wzr, #0x40", + "udiv x22, x20, x21", + "udiv x2, x20, x21", + "msub x20, x2, x21, x20", + "lsl x21, x22, #8", + "add x20, x21, x20", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "db 0xd5, 0x40": { @@ -127,12 +709,59 @@ "Comment": [ "aad with a different immediate byte base", "0xd5" + ], + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxtb x20, w20", + "mov w21, w4", + "uxth x21, w21", + "lsr w21, w21, #8", + "lsl x21, x21, #6", + "add x20, x20, x21", + "and x20, x20, #0xff", + "mov w21, w4", + "mov w0, w21", + "bfxil w0, w20, #0, #16", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "mov w20, w4", + "uxtb x20, w20", + "and x21, x20, #0x80", + "cmp x21, #0x0 (0)", + "cset x21, hs", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #31, #1", + "lsr w21, w0, #0", + "and x22, x20, #0xff", + "cmp x22, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "salc": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0xd6" + "Comment": "0xd6", + "ExpectedArm64ASM": [ + "mov w20, w4", + "uxtb x20, w20", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #29, #1", + "add w20, w20, w22", + "mov w22, w4", + "uxtb x22, w22", + "sub w20, w22, w20", + "mov w22, w4", + "mov w0, w22", + "bfxil w0, w20, #0, #8", + "lsr w20, w0, #0", + "bfxil x4, x20, #0, #32", + "str w21, [x28, #728]" + ] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index d3ce40325..4a5a037d6 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -17,67 +17,108 @@ "femms": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x0b" + "Comment": "0x0f 0x0b", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffff", + "strh w20, [x28, #1010]" + ] }, "movups xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x10" + "Comment": "0x0f 0x10", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "movups [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x11" + "Comment": "0x0f 0x11", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "movlps xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x12" + "Comment": "0x0f 0x12", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v16.d[0], v4.d[0]" + ] }, "movlps [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x13" + "Comment": "0x0f 0x13", + "ExpectedArm64ASM": [ + "str d16, [x4]" + ] }, "unpcklps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x14" + "Comment": "0x0f 0x14", + "ExpectedArm64ASM": [ + "zip1 v16.4s, v16.4s, v17.4s" + ] }, "unpckhps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x15" + "Comment": "0x0f 0x15", + "ExpectedArm64ASM": [ + "zip2 v16.4s, v16.4s, v17.4s" + ] }, "movhps xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x16" + "Comment": "0x0f 0x16", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v16.d[1], v4.d[0]" + ] }, "movlhps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x16" + "Comment": "0x0f 0x16", + "ExpectedArm64ASM": [ + "mov v16.d[1], v17.d[0]" + ] }, "movhps [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x17" + "Comment": "0x0f 0x17", + "ExpectedArm64ASM": [ + "mov x20, v16.d[1]", + "str x20, [x4]" + ] }, "nop": { "ExpectedInstructionCount": 0, "Optimal": "Yes", - "Comment": "0x0f 0x19" + "Comment": "0x0f 0x19", + "ExpectedArm64ASM": [] }, "movaps xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x28" + "Comment": "0x0f 0x28", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "movaps [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x29" + "Comment": "0x0f 0x29", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "cvtpi2ps xmm0, [rax]": { "ExpectedInstructionCount": 3, @@ -85,6 +126,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "scvtf v4.4s, v4.4s", + "mov v16.d[0], v4.d[0]" ] }, "cvtpi2ps xmm0, mm0": { @@ -93,302 +139,921 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "scvtf v4.4s, v4.4s", + "mov v16.d[0], v4.d[0]" ] }, "movntps [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x2b" + "Comment": "0x0f 0x2b", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "cvttps2pi mm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x0f 0x2c" + "Comment": "0x0f 0x2c", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "cvttps2pi mm0, xmm0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0x2c" + "Comment": "0x0f 0x2c", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "cvtps2pi mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x2d" + "Comment": "0x0f 0x2d", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "frinti v4.4s, v4.4s", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "cvtps2pi mm0, xmm0": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x0f 0x2d" + "Comment": "0x0f 0x2d", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "frinti v4.4s, v4.4s", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "ucomiss xmm0, xmm1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x0f 0x2e" + "Comment": "0x0f 0x2e", + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "comiss xmm0, xmm1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x0f 0x2f" + "Comment": "0x0f 0x2f", + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "rdtsc": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x0f 0x31" + "Comment": "0x0f 0x31", + "ExpectedArm64ASM": [ + "mrs x20, S3_3_c14_c0_2", + "ubfx x4, x20, #0, #32", + "lsr x6, x20, #32" + ] }, "cmovo ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x40" + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #28, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovo eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x40" + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #28, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, ne", + "str w22, [x28, #728]" + ] }, "cmovo rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x40" + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, ne", + "str w20, [x28, #728]" + ] }, "cmovno ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x41" + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #28, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovno eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x41" + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #28, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovno rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x41" + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovb ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x42" + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovb eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x42" + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, ne", + "str w22, [x28, #728]" + ] }, "cmovb rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0x42" + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, ne", + "str w20, [x28, #728]" + ] }, "cmovnb ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x43" + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovnb eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x43" + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #29, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovnb rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x43" + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovz ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x44" + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovz eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x44" + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, ne", + "str w22, [x28, #728]" + ] }, "cmovz rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x44" + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, ne", + "str w20, [x28, #728]" + ] }, "cmovnz ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x45" + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovnz eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x45" + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovnz rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x45" + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovbe ax, bx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x46" + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #29, #1", + "orr w23, w23, w24", + "cmp x23, #0x1 (1)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovbe eax, ebx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0x46" + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #29, #1", + "orr w23, w23, w24", + "cmp x23, #0x1 (1)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovbe rax, rbx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x46" + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #29, #1", + "orr w21, w21, w22", + "cmp x21, #0x1 (1)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovnbe ax, bx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x47" + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #29, #1", + "orr w23, w23, w24", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovnbe eax, ebx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0x47" + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #29, #1", + "orr w23, w23, w24", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovnbe rax, rbx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x47" + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #29, #1", + "orr w21, w21, w22", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovs ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x48" + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovs eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x48" + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, ne", + "str w22, [x28, #728]" + ] }, "cmovs rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x48" + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, ne", + "str w20, [x28, #728]" + ] }, "cmovns ax, bx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x49" + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "cmp x23, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovns eax, ebx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x49" + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "cmp x23, #0x0 (0)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovns rax, rbx": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0x49" + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "cmp x21, #0x0 (0)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovpe ax, bx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0x4a" + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "cmp x22, #0x0 (0)", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16" + ] }, "cmovpe eax, ebx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x4a" + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "cmp x22, #0x0 (0)", + "csel w4, w20, w21, ne" + ] }, "cmovpe rax, rbx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x4a" + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s4, w20", + "cnt v4.16b, v4.16b", + "umov w20, v4.b[0]", + "orr w21, wzr, #0x1", + "and x20, x21, x20", + "cmp x20, #0x0 (0)", + "csel x4, x7, x4, ne" + ] }, "cmovnp ax, bx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0x4b" + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "cmp x22, #0x0 (0)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16" + ] }, "cmovnp eax, ebx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x4b" + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "orr w23, wzr, #0x1", + "and x22, x23, x22", + "cmp x22, #0x0 (0)", + "csel w4, w20, w21, eq" + ] }, "cmovnp rax, rbx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x4b" + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s4, w20", + "cnt v4.16b, v4.16b", + "umov w20, v4.b[0]", + "orr w21, wzr, #0x1", + "and x20, x21, x20", + "cmp x20, #0x0 (0)", + "csel x4, x7, x4, eq" + ] }, "cmovl ax, bx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0x4c" + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "ubfx x24, x22, #28, #1", + "cmp w23, w24", + "csel w20, w20, w21, ne", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovl eax, ebx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x4c" + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "ubfx x24, x22, #28, #1", + "cmp w23, w24", + "csel w4, w20, w21, ne", + "str w22, [x28, #728]" + ] }, "cmovl rax, rbx": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x4c" + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "ubfx x22, x20, #28, #1", + "cmp w21, w22", + "csel x4, x7, x4, ne", + "str w20, [x28, #728]" + ] }, "cmovnl ax, bx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0x4d" + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "ubfx x24, x22, #28, #1", + "cmp w23, w24", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovnl eax, ebx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x4d" + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #31, #1", + "ubfx x24, x22, #28, #1", + "cmp w23, w24", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovnl rax, rbx": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x4d" + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "ubfx x22, x20, #28, #1", + "cmp w21, w22", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovle ax, bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0x4e" + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #31, #1", + "ubfx x25, x22, #28, #1", + "cmp x23, #0x1 (1)", + "cset x23, eq", + "cmp w24, w25", + "cset x24, ne", + "orr x23, x23, x24", + "cmp x23, #0x1 (1)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovle eax, ebx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0x4e" + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #31, #1", + "ubfx x25, x22, #28, #1", + "cmp x23, #0x1 (1)", + "cset x23, eq", + "cmp w24, w25", + "cset x24, ne", + "orr x23, x23, x24", + "cmp x23, #0x1 (1)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovle rax, rbx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0x4e" + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #31, #1", + "ubfx x23, x20, #28, #1", + "cmp x21, #0x1 (1)", + "cset x21, eq", + "cmp w22, w23", + "cset x22, ne", + "orr x21, x21, x22", + "cmp x21, #0x1 (1)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "cmovnle ax, bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0x4f" + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #31, #1", + "ubfx x25, x22, #28, #1", + "cmp x23, #0x0 (0)", + "cset x23, eq", + "cmp w24, w25", + "cset x24, eq", + "and x23, x23, x24", + "cmp x23, #0x1 (1)", + "csel w20, w20, w21, eq", + "bfxil x4, x20, #0, #16", + "str w22, [x28, #728]" + ] }, "cmovnle eax, ebx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0x4f" + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "ldr w22, [x28, #728]", + "ubfx x23, x22, #30, #1", + "ubfx x24, x22, #31, #1", + "ubfx x25, x22, #28, #1", + "cmp x23, #0x0 (0)", + "cset x23, eq", + "cmp w24, w25", + "cset x24, eq", + "and x23, x23, x24", + "cmp x23, #0x1 (1)", + "csel w4, w20, w21, eq", + "str w22, [x28, #728]" + ] }, "cmovnle rax, rbx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0x4f" + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #31, #1", + "ubfx x23, x20, #28, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "cmp w22, w23", + "cset x22, eq", + "and x21, x21, x22", + "cmp x21, #0x1 (1)", + "csel x4, x7, x4, eq", + "str w20, [x28, #728]" + ] }, "movmskps eax, xmm0": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0x0f 0x50" + "Comment": "0x0f 0x50", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, v16.s[0]", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21", + "mov w21, v16.s[1]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #1", + "orr x20, x20, x21", + "mov w21, v16.s[2]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #2", + "orr x20, x20, x21", + "mov w21, v16.s[3]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #3", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" + ] }, "movmskps rax, xmm0": { "ExpectedInstructionCount": 16, "Optimal": "No", - "Comment": "0x0f 0x50" + "Comment": "0x0f 0x50", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, v16.s[0]", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21", + "mov w21, v16.s[1]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #1", + "orr x20, x20, x21", + "mov w21, v16.s[2]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #2", + "orr x20, x20, x21", + "mov w21, v16.s[3]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #3", + "orr x4, x20, x21" + ] }, "sqrtps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x51" + "Comment": "0x0f 0x51", + "ExpectedArm64ASM": [ + "fsqrt v16.4s, v17.4s" + ] }, "rsqrtps xmm0, xmm1": { "ExpectedInstructionCount": 3, @@ -396,6 +1061,11 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x52" + ], + "ExpectedArm64ASM": [ + "fmov v0.4s, #0x70 (1.0000)", + "fsqrt v1.4s, v17.4s", + "fdiv v16.4s, v0.4s, v1.4s" ] }, "rcpps xmm0, xmm1": { @@ -404,242 +1074,531 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0x0f 0x53" + ], + "ExpectedArm64ASM": [ + "fmov v0.4s, #0x70 (1.0000)", + "fdiv v16.4s, v0.4s, v17.4s" ] }, "andps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x54" + "Comment": "0x0f 0x54", + "ExpectedArm64ASM": [ + "and v16.16b, v16.16b, v17.16b" + ] }, "andnps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x55" + "Comment": "0x0f 0x55", + "ExpectedArm64ASM": [ + "bic v16.16b, v17.16b, v16.16b" + ] }, "orps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x56" + "Comment": "0x0f 0x56", + "ExpectedArm64ASM": [ + "orr v16.16b, v16.16b, v17.16b" + ] }, "xorps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x57" + "Comment": "0x0f 0x57", + "ExpectedArm64ASM": [ + "eor v16.16b, v16.16b, v17.16b" + ] }, "addps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x58" + "Comment": "0x0f 0x58", + "ExpectedArm64ASM": [ + "fadd v16.4s, v16.4s, v17.4s" + ] }, "mulps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x59" + "Comment": "0x0f 0x59", + "ExpectedArm64ASM": [ + "fmul v16.4s, v16.4s, v17.4s" + ] }, "cvtps2pd xmm0, xmm1": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x5a" + "Comment": "0x0f 0x5a", + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcvtl v16.2d, v4.2s" + ] }, "cvtdq2ps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x5b" + "Comment": "0x0f 0x5b", + "ExpectedArm64ASM": [ + "scvtf v16.4s, v17.4s" + ] }, "subps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x5c" + "Comment": "0x0f 0x5c", + "ExpectedArm64ASM": [ + "fsub v16.4s, v16.4s, v17.4s" + ] }, "minps xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x0f 0x5d" + "Comment": "0x0f 0x5d", + "ExpectedArm64ASM": [ + "fcmgt v0.4s, v17.4s, v16.4s", + "mov v1.16b, v16.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v16.16b, v1.16b" + ] }, "divps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0x5e" + "Comment": "0x0f 0x5e", + "ExpectedArm64ASM": [ + "fdiv v16.4s, v16.4s, v17.4s" + ] }, "maxps xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x0f 0x5f" + "Comment": "0x0f 0x5f", + "ExpectedArm64ASM": [ + "fcmgt v0.4s, v17.4s, v16.4s", + "mov v1.16b, v16.16b", + "bit v1.16b, v17.16b, v0.16b", + "mov v16.16b, v1.16b" + ] }, "punpcklbw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x60" + "Comment": "0x0f 0x60", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip1 v4.8b, v4.8b, v5.8b", + "str d4, [x28, #752]" + ] }, "punpcklbw mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x60" + "Comment": "0x0f 0x60", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip1 v4.8b, v4.8b, v5.8b", + "str d4, [x28, #752]" + ] }, "punpcklwd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x61" + "Comment": "0x0f 0x61", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip1 v4.4h, v4.4h, v5.4h", + "str d4, [x28, #752]" + ] }, "punpcklwd mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x61" + "Comment": "0x0f 0x61", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip1 v4.4h, v4.4h, v5.4h", + "str d4, [x28, #752]" + ] }, "punpckldq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x62" + "Comment": "0x0f 0x62", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip1 v4.2s, v4.2s, v5.2s", + "str d4, [x28, #752]" + ] }, "punpckldq mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x62" + "Comment": "0x0f 0x62", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip1 v4.2s, v4.2s, v5.2s", + "str d4, [x28, #752]" + ] }, "packsswb mm0, mm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x63" + "Comment": "0x0f 0x63", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "sqxtn v4.8b, v4.8h", + "sqxtn v1.8b, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.s[1], v1.s[0]", + "str d4, [x28, #752]" + ] }, "packsswb mm0, [rax]": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x63" + "Comment": "0x0f 0x63", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "sqxtn v4.8b, v4.8h", + "sqxtn v1.8b, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.s[1], v1.s[0]", + "str d4, [x28, #752]" + ] }, "pcmpgtb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x64" + "Comment": "0x0f 0x64", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmgt v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "pcmpgtw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x65" + "Comment": "0x0f 0x65", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmgt v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pcmpgtd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x66" + "Comment": "0x0f 0x66", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmgt v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "punpckhbw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x68" + "Comment": "0x0f 0x68", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip2 v4.8b, v4.8b, v5.8b", + "str d4, [x28, #752]" + ] }, "punpckhbw mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x68" + "Comment": "0x0f 0x68", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip2 v4.8b, v4.8b, v5.8b", + "str d4, [x28, #752]" + ] }, "punpckhwd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x69" + "Comment": "0x0f 0x69", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip2 v4.4h, v4.4h, v5.4h", + "str d4, [x28, #752]" + ] }, "punpckhwd mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x69" + "Comment": "0x0f 0x69", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip2 v4.4h, v4.4h, v5.4h", + "str d4, [x28, #752]" + ] }, "punpckhdq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x6a" + "Comment": "0x0f 0x6a", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "zip2 v4.2s, v4.2s, v5.2s", + "str d4, [x28, #752]" + ] }, "punpckhdq mm0, [rax]": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x6a" + "Comment": "0x0f 0x6a", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x4]", + "zip2 v4.2s, v4.2s, v5.2s", + "str d4, [x28, #752]" + ] }, "packssdw mm0, mm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x6b" + "Comment": "0x0f 0x6b", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "sqxtn v4.4h, v4.4s", + "sqxtn v1.4h, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.s[1], v1.s[0]", + "str d4, [x28, #752]" + ] }, "movd mm0, eax": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0x6e" + "Comment": "0x0f 0x6e", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "fmov s4, w20", + "str d4, [x28, #752]" + ] }, "movd mm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0x6e" + "Comment": "0x0f 0x6e", + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "fmov s4, w20", + "str d4, [x28, #752]" + ] }, "movq mm0, mm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x6f" + "Comment": "0x0f 0x6f", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "movq mm0, mm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x6f" + "Comment": "0x0f 0x6f", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "str d4, [x28, #752]" + ] }, "movq mm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x6f" + "Comment": "0x0f 0x6f", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "str d4, [x28, #752]" + ] }, "pshufw mm0, mm1, 0": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[0]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pshufw mm0, [rax], 0": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[0]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pshufw mm0, mm1, 1": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[1]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pshufw mm0, [rax], 1": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[1]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pshufw mm0, mm1, 0xff": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[3]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[3]", + "mov v5.h[2], v4.h[3]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[3]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pshufw mm0, [rax], 0xff": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0x70" + "Comment": "0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[3]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[3]", + "mov v5.h[2], v4.h[3]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[3]", + "mov v4.16b, v0.16b", + "str d4, [x28, #752]" + ] }, "pcmpeqb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x74" + "Comment": "0x0f 0x74", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmeq v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "pcmpeqw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x75" + "Comment": "0x0f 0x75", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmeq v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pcmpeqd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0x76" + "Comment": "0x0f 0x76", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "cmeq v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "emms": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x77" + "Comment": "0x0f 0x77", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffff", + "strh w20, [x28, #1010]" + ] }, "movd eax, mm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0x7e" + "Comment": "0x0f 0x7e", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "mov w4, v4.s[0]" + ] }, "movd [rax], mm0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0x7e" + "Comment": "0x0f 0x7e", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "mov w20, v4.s[0]", + "str w20, [x4]" + ] }, "db 0x0f, 0x7f, 0xc1": { "ExpectedInstructionCount": 2, @@ -648,927 +1607,2966 @@ "movq mm0, mm1", "Manual encoded since nasm would encode 0x6f version", "0x0f 0x7f" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #768]" ] }, "movq [rax], mm0": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0x7f" + "Comment": "0x0f 0x7f", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x4]" + ] }, "seto al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x90" + "Comment": "0x0f 0x90", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "cmp x21, #0x0 (0)", + "cset x21, ne", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setno al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x91" + "Comment": "0x0f 0x91", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #28, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setb al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x92" + "Comment": "0x0f 0x92", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "cmp x21, #0x0 (0)", + "cset x21, ne", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setnb al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x93" + "Comment": "0x0f 0x93", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setz al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x94" + "Comment": "0x0f 0x94", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "cmp x21, #0x0 (0)", + "cset x21, ne", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setnz al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x95" + "Comment": "0x0f 0x95", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setbe al": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x96" + "Comment": "0x0f 0x96", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #29, #1", + "orr w21, w21, w22", + "cmp x21, #0x1 (1)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setnbe al": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0x97" + "Comment": "0x0f 0x97", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #29, #1", + "orr w21, w21, w22", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "sets al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x98" + "Comment": "0x0f 0x98", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "cmp x21, #0x0 (0)", + "cset x21, ne", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setns al": { "ExpectedInstructionCount": 6, "Optimal": "Yes", - "Comment": "0x0f 0x99" + "Comment": "0x0f 0x99", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setpe al": { "ExpectedInstructionCount": 9, "Optimal": "Yes", - "Comment": "0x0f 0x9a" + "Comment": "0x0f 0x9a", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldrb w21, [x28, #706]", + "fmov s4, w21", + "cnt v4.16b, v4.16b", + "umov w21, v4.b[0]", + "and x20, x20, x21", + "cmp x20, #0x0 (0)", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] }, "setnp al": { "ExpectedInstructionCount": 9, "Optimal": "Yes", - "Comment": "0x0f 0x9b" + "Comment": "0x0f 0x9b", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ldrb w21, [x28, #706]", + "fmov s4, w21", + "cnt v4.16b, v4.16b", + "umov w21, v4.b[0]", + "and x20, x20, x21", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] }, "setl al": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x9c" + "Comment": "0x0f 0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "ubfx x22, x20, #28, #1", + "cmp w21, w22", + "cset x21, ne", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setnl al": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0x9d" + "Comment": "0x0f 0x9d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #31, #1", + "ubfx x22, x20, #28, #1", + "cmp w21, w22", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setle al": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x0f 0x9e" + "Comment": "0x0f 0x9e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #31, #1", + "ubfx x23, x20, #28, #1", + "cmp x21, #0x1 (1)", + "cset x21, eq", + "cmp w22, w23", + "cset x22, ne", + "orr x21, x21, x22", + "cmp x21, #0x1 (1)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "setnle al": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x0f 0x9f" + "Comment": "0x0f 0x9f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #30, #1", + "ubfx x22, x20, #31, #1", + "ubfx x23, x20, #28, #1", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "cmp w22, w23", + "cset x22, eq", + "and x21, x21, x22", + "cmp x21, #0x1 (1)", + "cset x21, eq", + "bfxil x4, x21, #0, #8", + "str w20, [x28, #728]" + ] }, "push fs": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xa0" + "Comment": "0x0f 0xa0", + "ExpectedArm64ASM": [ + "sub x8, x8, #0x8 (8)", + "ldr x20, [x28, #176]", + "str x20, [x8]" + ] }, "pop fs": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0xa1" + "Comment": "0x0f 0xa1", + "ExpectedArm64ASM": [ + "ldr x20, [x8]", + "add x8, x8, #0x8 (8)", + "strh w20, [x28, #146]", + "ubfx x20, x20, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #176]" + ] }, "bt ax, bx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "and x20, x20, #0xf", + "lsr w20, w21, w20", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt [rax], bx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #13", + "ldrb w20, [x4, x20, sxtx]", + "lsr w20, w20, w21", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt eax, ebx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "and x20, x20, #0x1f", + "lsr w20, w21, w20", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt [rax], ebx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #29", + "ldrb w20, [x4, x20, sxtx]", + "lsr w20, w20, w21", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt rax, rbx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x20, x4, x20", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt [rax], rbx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xa3" + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "ldrb w21, [x4, x21, sxtx]", + "lsr w20, w21, w20", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "shld ax, bx, 0": { "ExpectedInstructionCount": 0, "Optimal": "Yes", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [] }, "shld ax, bx, 1": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "lsl x22, x21, #1", + "lsr w20, w20, #15", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "lsl x23, x20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x24, x21, #15, #1", + "orr x23, x23, x24, lsl #29", + "eor x24, x20, #0x1", + "strb w24, [x28, #706]", + "strb w22, [x28, #708]", + "eor x20, x20, x21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shld ax, bx, 15": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "lsl x22, x21, #15", + "lsr w20, w20, #1", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "lsl x23, x20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x21, x21, #1, #1", + "orr x21, x23, x21, lsl #29", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "strb w22, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld ax, bx, 16": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "mov w22, #0x0", + "lsl x23, x21, #16", + "orr x20, x23, x20", + "bfxil x4, x20, #0, #16", + "lsl x23, x20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x21, x21, #0, #1", + "orr x21, x23, x21, lsl #29", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "strb w22, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld ax, bx, 31": { "ExpectedInstructionCount": 18, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "lsl x22, x21, #31", + "lsr w20, w20, #17", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "lsl x23, x20, #16", + "and x23, x23, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "ubfx x21, x21, #1, #1", + "orr x21, x23, x21, lsl #29", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "strb w22, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld eax, ebx, 0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "ubfx x4, x4, #0, #32" + ] }, "shld eax, ebx, 1": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "extr w4, w21, w20, #31", + "mov w20, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x23, x21, #31, #1", + "orr w22, w22, w23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w20, [x28, #708]", + "eor w20, w4, w21", + "ubfx x20, x20, #31, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] }, "shld eax, ebx, 15": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "extr w4, w21, w20, #17", + "mov w20, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x21, x21, #17, #1", + "orr w21, w22, w21, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld eax, ebx, 16": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "extr w4, w21, w20, #16", + "mov w20, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x21, x21, #16, #1", + "orr w21, w22, w21, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld eax, ebx, 31": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "extr w4, w21, w20, #1", + "mov w20, #0x0", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx x21, x21, #1, #1", + "orr w21, w22, w21, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "shld rax, rbx, 0": { "ExpectedInstructionCount": 0, "Optimal": "Yes", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [] }, "shld rax, rbx, 1": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #63", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "lsr x23, x20, #63", + "orr x22, x22, x23, lsl #29", + "eor x23, x4, #0x1", + "strb w23, [x28, #706]", + "strb w21, [x28, #708]", + "eor x20, x4, x20", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "shld rax, rbx, 15": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #49", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #49, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shld rax, rbx, 32": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #32", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #32, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shld rax, rbx, 63": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xac" + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #1", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr x20, x22, x20, lsl #29", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "shld ax, bx, cl": { "ExpectedInstructionCount": 36, "Optimal": "No", - "Comment": "0x0f 0xad" + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "uxtb x22, w5", + "and x22, x22, #0x1f", + "orr w23, wzr, #0x10", + "sub x23, x23, x22", + "lsl x24, x21, x22", + "lsr w20, w20, w23", + "orr x20, x24, x20", + "cmp x22, #0x0 (0)", + "csel x20, x21, x20, eq", + "bfxil x4, x20, #0, #16", + "cbz x22, #+0x60", + "uxth x20, w20", + "ldr w23, [x28, #728]", + "orr w24, wzr, #0x10", + "lsl x25, x20, #16", + "and x25, x25, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x26, eq", + "orr x25, x25, x26, lsl #30", + "sub x24, x24, x22", + "lsr w24, w21, w24", + "ubfx x24, x24, #0, #1", + "orr x24, x25, x24, lsl #29", + "eor x25, x20, #0x1", + "ldrb w26, [x28, #706]", + "cmp x22, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor x20, x21, x20", + "ubfx x20, x20, #15, #1", + "orr x20, x24, x20, lsl #28", + "cmp x22, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "shld eax, ebx, cl": { "ExpectedInstructionCount": 33, "Optimal": "No", - "Comment": "0x0f 0xad" + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "uxtb x22, w5", + "and x22, x22, #0x1f", + "orr w23, wzr, #0x20", + "sub x23, x23, x22", + "lsl x24, x21, x22", + "lsr w20, w20, w23", + "orr x20, x24, x20", + "cmp x22, #0x0 (0)", + "csel x20, x21, x20, eq", + "ubfx x4, x20, #0, #32", + "cbz x22, #+0x54", + "ubfx x20, x20, #0, #32", + "ldr w23, [x28, #728]", + "tst w20, w20", + "mrs x24, nzcv", + "orr w25, wzr, #0x20", + "sub x25, x25, x22", + "lsr w25, w21, w25", + "ubfx x25, x25, #0, #1", + "orr w24, w24, w25, lsl #29", + "eor x25, x20, #0x1", + "ldrb w26, [x28, #706]", + "cmp x22, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor x20, x21, x20", + "ubfx x20, x20, #31, #1", + "orr x20, x24, x20, lsl #28", + "cmp x22, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "shld rax, rbx, cl": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0x0f 0xad" + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "mov x20, x4", + "uxtb x21, w5", + "and x21, x21, #0x3f", + "orr w22, wzr, #0x40", + "sub x22, x22, x21", + "lsl x23, x20, x21", + "lsr x22, x7, x22", + "orr x22, x23, x22", + "cmp x21, #0x0 (0)", + "csel x22, x20, x22, eq", + "mov x4, x22", + "cbz x21, #+0x50", + "ldr w23, [x28, #728]", + "tst x22, x22", + "mrs x24, nzcv", + "orr w25, wzr, #0x40", + "sub x25, x25, x21", + "lsr x25, x20, x25", + "ubfx x25, x25, #0, #1", + "orr x24, x24, x25, lsl #29", + "eor x25, x22, #0x1", + "ldrb w26, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x25, x26, x25, eq", + "strb w25, [x28, #706]", + "eor x20, x20, x22", + "lsr x20, x20, #63", + "orr x20, x24, x20, lsl #28", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "str w20, [x28, #728]" + ] }, "push gs": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xa8" + "Comment": "0x0f 0xa8", + "ExpectedArm64ASM": [ + "sub x8, x8, #0x8 (8)", + "ldr x20, [x28, #168]", + "str x20, [x8]" + ] }, "pop gs": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x0f 0xa9" + "Comment": "0x0f 0xa9", + "ExpectedArm64ASM": [ + "ldr x20, [x8]", + "add x8, x8, #0x8 (8)", + "strh w20, [x28, #144]", + "ubfx x20, x20, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #168]" + ] }, "bts ax, bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "and x20, x20, #0xf", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "orr x20, x21, x20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts [rax], bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #13", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "orr x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts eax, ebx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "and x20, x20, #0x1f", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "orr x20, x21, x20", + "ubfx x4, x20, #0, #32", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts [rax], ebx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #29", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "orr x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts rax, rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "orr w22, wzr, #0x1", + "lsl x20, x22, x20", + "orr x4, x4, x20", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts [rax], rbx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xab" + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "orr w22, wzr, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "orr x22, x23, x22", + "strb w22, [x4, x21, sxtx]", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "imul ax, bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xaf" + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w7", + "sxth x20, w20", + "sxth x21, w21", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #15, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul eax, ebx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xaf" + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x7, #0, #32", + "sxtw x20, w20", + "sxtw x21, w21", + "mul x20, x20, x21", + "asr x21, x20, #32", + "ubfx x4, x20, #0, #32", + "mov w22, #0x0", + "strb w22, [x28, #706]", + "strb w22, [x28, #708]", + "sbfx x20, x20, #31, #1", + "orr w23, wzr, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] }, "imul rax, rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xaf" + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x20, x7", + "smulh x20, x20, x7", + "mov w21, #0x0", + "strb w21, [x28, #706]", + "strb w21, [x28, #708]", + "asr x22, x4, #63", + "orr w23, wzr, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] }, "cmpxchg al, bl": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0x0f 0xb0" + "Comment": "0x0f 0xb0", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w4", + "uxtb x22, w4", + "cmp x21, x22", + "csel x23, x22, x21, eq", + "cmp x21, x22", + "csel w20, w20, w21, eq", + "bfxil x4, x23, #0, #8", + "bfxil x4, x20, #0, #8", + "sub x20, x22, x23", + "uxtb x20, w20", + "eor x21, x22, x23", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl x21, x20, #24", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x21, x21, x24, lsl #30", + "cmp x22, x23", + "cset x24, lo", + "orr x21, x21, x24, lsl #29", + "eor x23, x22, x23", + "eor x20, x20, x22", + "and x20, x23, x20", + "ubfx x20, x20, #7, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg [rax], bl": { "ExpectedInstructionCount": 28, "Optimal": "No", - "Comment": "0x0f 0xb0" + "Comment": "0x0f 0xb0", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "uxtb x21, w4", + "mov w1, w21", + "casalb w1, w20, [x4]", + "mov w20, w1", + "bfxil x4, x20, #0, #8", + "sub w22, w21, w20", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg ax, bx": { "ExpectedInstructionCount": 31, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "uxth x22, w4", + "cmp x21, x22", + "csel x23, x22, x21, eq", + "cmp x21, x22", + "csel w20, w20, w21, eq", + "bfxil x4, x23, #0, #16", + "bfxil x4, x20, #0, #16", + "sub x20, x22, x23", + "uxth x20, w20", + "eor x21, x22, x23", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "lsl x21, x20, #16", + "and x21, x21, #0x80000000", + "cmp x20, #0x0 (0)", + "cset x24, eq", + "orr x21, x21, x24, lsl #30", + "cmp x22, x23", + "cset x24, lo", + "orr x21, x21, x24, lsl #29", + "eor x23, x22, x23", + "eor x20, x20, x22", + "and x20, x23, x20", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg [rax], bx": { "ExpectedInstructionCount": 28, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "mov w1, w21", + "casalh w1, w20, [x4]", + "mov w20, w1", + "bfxil x4, x20, #0, #16", + "sub w22, w21, w20", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w21, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg eax, ebx": { "ExpectedInstructionCount": 30, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "mov x21, x4", + "mov x22, x4", + "ubfx x23, x21, #0, #32", + "ubfx x24, x22, #0, #32", + "cmp x23, x24", + "csel x25, x24, x23, eq", + "cmp x23, x24", + "csel x20, x20, x21, eq", + "cmp x25, x24", + "csel x4, x22, x23, eq", + "mov x4, x20", + "sub x20, x24, x25", + "eor x21, x24, x25", + "eor x21, x21, x20", + "ubfx x21, x21, #4, #1", + "strb w21, [x28, #708]", + "eor x21, x20, #0x1", + "strb w21, [x28, #706]", + "tst w20, w20", + "mrs x21, nzcv", + "cmp x24, x25", + "cset x22, lo", + "orr x21, x21, x22, lsl #29", + "eor x22, x24, x25", + "eor x20, x20, x24", + "and x20, x22, x20", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg [rax], ebx": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "mov x21, x4", + "ubfx x22, x21, #0, #32", + "mov w1, w22", + "casal w1, w20, [x4]", + "mov w20, w1", + "cmp w20, w22", + "csel x4, x21, x20, eq", + "sub w21, w22, w20", + "eor w23, w22, w20", + "eor w23, w23, w21", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x21, #0x1", + "strb w23, [x28, #706]", + "tst w21, w21", + "mrs x23, nzcv", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w22, w20", + "eor w21, w21, w22", + "and w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg rax, rbx": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x21, x4", + "cmp x20, x21", + "csel x22, x21, x20, eq", + "cmp x20, x21", + "csel x20, x7, x20, eq", + "mov x4, x22", + "mov x4, x20", + "sub x20, x21, x22", + "eor x23, x21, x22", + "eor x23, x23, x20", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x20, #0x1", + "strb w23, [x28, #706]", + "tst x20, x20", + "mrs x23, nzcv", + "cmp x21, x22", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor x22, x21, x22", + "eor x20, x20, x21", + "and x20, x22, x20", + "lsr x20, x20, #63", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpxchg [rax], rbx": { "ExpectedInstructionCount": 22, "Optimal": "No", - "Comment": "0x0f 0xb1" + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x1, x20", + "casal x1, x7, [x4]", + "mov x4, x1", + "sub x21, x20, x4", + "eor x22, x20, x4", + "eor x22, x22, x21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst x21, x21", + "mrs x22, nzcv", + "cmp x20, x4", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x23, x20, x4", + "eor x20, x21, x20", + "and x20, x23, x20", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "btr ax, bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "and x20, x20, #0xf", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "bic w20, w21, w20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr [rax], bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #13", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "bic w22, w23, w22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr eax, ebx": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "and x20, x20, #0x1f", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "bic w4, w21, w20", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr [rax], ebx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #29", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "bic w22, w23, w22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr rax, rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "orr w22, wzr, #0x1", + "lsl x20, x22, x20", + "bic x4, x4, x20", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr [rax], rbx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xb3" + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "orr w22, wzr, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "bic w22, w23, w22", + "strb w22, [x4, x21, sxtx]", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "movzx ax, bl": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "bfxil x4, x20, #0, #16" + ] }, "movzx ax, byte [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "bfxil x4, x20, #0, #16" + ] }, "movzx eax, bl": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "uxtb x4, w7" + ] }, "movzx eax, byte [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "ldrb w4, [x4]" + ] }, "movzx rax, bl": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "uxtb x4, w7" + ] }, "movzx rax, byte [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb6" + "Comment": "0x0f 0xb6", + "ExpectedArm64ASM": [ + "ldrb w4, [x4]" + ] }, "movzx eax, bx": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb7" + "Comment": "0x0f 0xb7", + "ExpectedArm64ASM": [ + "uxth x4, w7" + ] }, "movzx eax, word [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb7" + "Comment": "0x0f 0xb7", + "ExpectedArm64ASM": [ + "ldrh w4, [x4]" + ] }, "movzx rax, bx": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb7" + "Comment": "0x0f 0xb7", + "ExpectedArm64ASM": [ + "uxth x4, w7" + ] }, "movzx rax, word [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xb7" + "Comment": "0x0f 0xb7", + "ExpectedArm64ASM": [ + "ldrh w4, [x4]" + ] }, "btc ax, bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "uxth x21, w4", + "and x20, x20, #0xf", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "eor x20, x21, x20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc [rax], bx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #13", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "eor x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc eax, ebx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x4, #0, #32", + "and x20, x20, #0x1f", + "lsr w22, w21, w20", + "orr w23, wzr, #0x1", + "lsl x20, x23, x20", + "eor x20, x21, x20", + "ubfx x4, x20, #0, #32", + "ubfx x20, x22, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc [rax], ebx": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x20, #0, #3", + "sbfx x20, x20, #3, #29", + "orr w22, wzr, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "eor x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc rax, rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "orr w22, wzr, #0x1", + "lsl x20, x22, x20", + "eor x4, x4, x20", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc [rax], rbx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xbb" + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "orr w22, wzr, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "eor x22, x23, x22", + "strb w22, [x4, x21, sxtx]", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bsf ax, bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xbc" + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w7", + "uxth w0, w21", + "cmp w0, #0x0 (0)", + "rbit w0, w0", + "clz w22, w0", + "csinv w22, w22, wzr, ne", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "bfxil x4, x20, #0, #16", + "cmp x21, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "bsf eax, ebx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xbc" + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "lsr w0, w20, #0", + "cmp w0, #0x0 (0)", + "rbit w0, w0", + "clz w21, w0", + "csinv w21, w21, wzr, ne", + "cmp x20, #0x0 (0)", + "csel x4, x4, x21, eq", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "bsf rax, rbx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xbc" + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "rbit x0, x7", + "cmp x7, #0x0 (0)", + "clz x20, x0", + "csinv x20, x20, xzr, ne", + "cmp x7, #0x0 (0)", + "csel x4, x4, x20, eq", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "bsr ax, bx": { "ExpectedInstructionCount": 14, "Optimal": "No", - "Comment": "0x0f 0xbd" + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w7", + "mov x0, #0xf", + "lsl w22, w21, #16", + "orr w22, w22, #0x8000", + "clz w22, w22", + "sub x22, x0, x22", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "bfxil x4, x20, #0, #16", + "cmp x21, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "bsr eax, ebx": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xbd" + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "mov x0, #0x1f", + "clz w21, w20", + "sub x21, x0, x21", + "cmp x20, #0x0 (0)", + "csel x4, x4, x21, eq", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "bsr rax, rbx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xbd" + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "mov x0, #0x3f", + "clz x20, x7", + "sub x20, x0, x20", + "cmp x7, #0x0 (0)", + "csel x4, x4, x20, eq", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] }, "movsx ax, bl": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "sxtb x20, w20", + "bfxil x4, x20, #0, #16" + ] }, "movsx ax, byte [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "sxtb x20, w20", + "bfxil x4, x20, #0, #16" + ] }, "movsx eax, bl": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "sxtb x20, w20", + "ubfx x4, x20, #0, #32" + ] }, "movsx eax, byte [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "sxtb x20, w20", + "ubfx x4, x20, #0, #32" + ] }, "movsx rax, bl": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "sxtb x4, w20" + ] }, "movsx rax, byte [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xbe" + "Comment": "0x0f 0xbe", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "sxtb x4, w20" + ] }, "movsx eax, bx": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbf" + "Comment": "0x0f 0xbf", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "sxth x20, w20", + "ubfx x4, x20, #0, #32" + ] }, "movsx eax, word [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xbf" + "Comment": "0x0f 0xbf", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x20, w20", + "ubfx x4, x20, #0, #32" + ] }, "movsx rax, bx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0xbf" + "Comment": "0x0f 0xbf", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "sxth x4, w20" + ] }, "movsx rax, word [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xbf" + "Comment": "0x0f 0xbf", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "sxth x4, w20" + ] }, "xadd al, bl": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "0x0f 0xc0" + "Comment": "0x0f 0xc0", + "ExpectedArm64ASM": [ + "uxtb x20, w4", + "uxtb x21, w7", + "add w22, w20, w21", + "bfxil x7, x20, #0, #8", + "bfxil x4, x22, #0, #8", + "uxtb x22, w22", + "eor w23, w20, w21", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "bic w20, w20, w21", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd [rax], bl": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "0x0f 0xc0" + "Comment": "0x0f 0xc0", + "ExpectedArm64ASM": [ + "uxtb x20, w7", + "ldaddalb w20, w21, [x4]", + "bfxil x7, x21, #0, #8", + "add w22, w21, w20", + "uxtb x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #24", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #7, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd ax, bx": { "ExpectedInstructionCount": 26, "Optimal": "No", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "uxth x21, w7", + "add w22, w20, w21", + "bfxil x7, x20, #0, #16", + "bfxil x4, x22, #0, #16", + "uxth x22, w22", + "eor w23, w20, w21", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w21", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "bic w20, w20, w21", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd [rax], bx": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "ldaddalh w20, w21, [x4]", + "bfxil x7, x21, #0, #16", + "add w22, w21, w20", + "uxth x22, w22", + "eor w23, w21, w20", + "eor w23, w23, w22", + "ubfx x23, x23, #4, #1", + "strb w23, [x28, #708]", + "eor x23, x22, #0x1", + "strb w23, [x28, #706]", + "lsl w23, w22, #16", + "and x23, x23, #0x80000000", + "cmp x22, #0x0 (0)", + "cset x24, eq", + "orr x23, x23, x24, lsl #30", + "cmp w22, w20", + "cset x24, lo", + "orr x23, x23, x24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx x20, x20, #15, #1", + "orr x20, x23, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd eax, ebx": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x21, x7, #0, #32", + "add w4, w20, w21", + "mov x7, x20", + "eor w22, w20, w21", + "eor w22, w22, w4", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "tst w4, w4", + "mrs x22, nzcv", + "cmp w4, w21", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w21, w20, w21", + "eor w20, w4, w20", + "bic w20, w20, w21", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd [rax], ebx": { "ExpectedInstructionCount": 20, "Optimal": "Yes", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ldaddal w20, w7, [x4]", + "add w21, w7, w20", + "eor w22, w7, w20", + "eor w22, w22, w21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst w21, w21", + "mrs x22, nzcv", + "cmp w21, w20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor w20, w7, w20", + "eor w21, w21, w7", + "bic w20, w21, w20", + "ubfx x20, x20, #31, #1", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd rax, rbx": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x21, x7", + "add x4, x20, x21", + "mov x7, x20", + "eor x22, x20, x21", + "eor x22, x22, x4", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x4, #0x1", + "strb w22, [x28, #706]", + "tst x4, x4", + "mrs x22, nzcv", + "cmp x4, x21", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x21, x20, x21", + "eor x20, x4, x20", + "bic x20, x20, x21", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "xadd [rax], rbx": { "ExpectedInstructionCount": 20, "Optimal": "Yes", - "Comment": "0x0f 0xc1" + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov x20, x7", + "ldaddal x20, x7, [x4]", + "add x21, x7, x20", + "eor x22, x7, x20", + "eor x22, x22, x21", + "ubfx x22, x22, #4, #1", + "strb w22, [x28, #708]", + "eor x22, x21, #0x1", + "strb w22, [x28, #706]", + "tst x21, x21", + "mrs x22, nzcv", + "cmp x21, x20", + "cset x23, lo", + "orr x22, x22, x23, lsl #29", + "eor x20, x7, x20", + "eor x21, x21, x7", + "bic x20, x21, x20", + "lsr x20, x20, #63", + "orr x20, x22, x20, lsl #28", + "str w20, [x28, #728]" + ] }, "cmpps xmm0, xmm1, 0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmeq v16.4s, v16.4s, v17.4s" + ] }, "cmpps xmm0, xmm1, 1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmgt v16.4s, v17.4s, v16.4s" + ] }, "cmpps xmm0, xmm1, 2": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmge v16.4s, v17.4s, v16.4s" + ] }, "cmpps xmm0, xmm1, 3": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmge v0.4s, v16.4s, v17.4s", + "fcmgt v1.4s, v17.4s, v16.4s", + "orr v16.16b, v0.16b, v1.16b", + "mvn v16.16b, v16.16b" + ] }, "cmpps xmm0, xmm1, 4": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmeq v16.4s, v16.4s, v17.4s", + "mvn v16.16b, v16.16b" + ] }, "cmpps xmm0, xmm1, 5": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmgt v4.4s, v17.4s, v16.4s", + "mvn v16.16b, v4.16b" + ] }, "cmpps xmm0, xmm1, 6": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmge v4.4s, v17.4s, v16.4s", + "mvn v16.16b, v4.16b" + ] }, "cmpps xmm0, xmm1, 7": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x0f 0xc2" + "Comment": "0x0f 0xc2", + "ExpectedArm64ASM": [ + "fcmge v0.4s, v16.4s, v17.4s", + "fcmgt v1.4s, v17.4s, v16.4s", + "orr v16.16b, v0.16b, v1.16b" + ] }, "movnti [rax], ebx": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0xc3" + "Comment": "0x0f 0xc3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "str w20, [x4]" + ] }, "movnti [rax], rbx": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xc3" + "Comment": "0x0f 0xc3", + "ExpectedArm64ASM": [ + "str x7, [x4]" + ] }, "pinsrw mm0, eax, 0": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[0], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, eax, 1": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[1], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, eax, 2": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[2], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, eax, 3": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[3], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, eax, 4": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[0], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, [rax], 0": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[0], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, [rax], 1": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[1], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, [rax], 2": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[2], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, [rax], 3": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[3], w20", + "str d4, [x28, #752]" + ] }, "pinsrw mm0, [rax], 4": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xc4" + "Comment": "0x0f 0xc4", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ldr d4, [x28, #752]", + "mov v4.16b, v4.16b", + "mov v4.h[0], w20", + "str d4, [x28, #752]" + ] }, "pextrw eax, mm0, 0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xc5" + "Comment": "0x0f 0xc5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "umov w20, v4.h[0]", + "uxth x4, w20" + ] }, "pextrw eax, mm0, 1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xc5" + "Comment": "0x0f 0xc5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "umov w20, v4.h[1]", + "uxth x4, w20" + ] }, "pextrw eax, mm0, 2": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xc5" + "Comment": "0x0f 0xc5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "umov w20, v4.h[2]", + "uxth x4, w20" + ] }, "pextrw eax, mm0, 3": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xc5" + "Comment": "0x0f 0xc5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "umov w20, v4.h[3]", + "uxth x4, w20" + ] }, "pextrw eax, mm0, 4": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0x0f 0xc5" + "Comment": "0x0f 0xc5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "umov w20, v4.h[0]", + "uxth x4, w20" + ] }, "shufps xmm0, xmm1, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v16.s[0]", + "mov v4.s[2], v17.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[0]", + "mov v16.16b, v0.16b" + ] }, "shufps xmm0, [rax], 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v16.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v16.16b, v0.16b" + ] }, "shufps xmm0, xmm1, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v16.s[0]", + "mov v4.s[2], v17.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[0]", + "mov v16.16b, v0.16b" + ] }, "shufps xmm0, [rax], 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[1]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v16.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v16.16b, v0.16b" + ] }, "shufps xmm0, xmm1, 0xFF": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[3]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v16.s[3]", + "mov v4.s[2], v17.s[3]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" + ] }, "shufps xmm0, [rax], 0xFF": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xc6" + "Comment": "0x0f 0xc6", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v16.16b", + "mov v0.s[0], v16.s[3]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v16.s[3]", + "mov v5.s[2], v4.s[3]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v16.16b, v0.16b" + ] }, "bswap eax": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x0f 0xc8" + "Comment": "0x0f 0xc8", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "rev w4, w20" + ] }, "bswap rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x0f 0xc8" + "Comment": "0x0f 0xc8", + "ExpectedArm64ASM": [ + "rev x4, x4" + ] }, "psrlw mm0, mm1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xd1" + "Comment": "0x0f 0xd1", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "neg v0.8h, v0.8h", + "ushl v4.8h, v5.8h, v0.8h", + "str d4, [x28, #752]" + ] }, "psrld mm0, mm1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xd2" + "Comment": "0x0f 0xd2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "neg v0.4s, v0.4s", + "ushl v4.4s, v5.4s, v0.4s", + "str d4, [x28, #752]" + ] }, "psrlq mm0, mm1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xd3" + "Comment": "0x0f 0xd3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.2d, v4.d[0]", + "neg v0.2d, v0.2d", + "ushl v4.2d, v5.2d, v0.2d", + "str d4, [x28, #752]" + ] }, "paddq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xd4" + "Comment": "0x0f 0xd4", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "add v4.2d, v5.2d, v4.2d", + "str d4, [x28, #752]" + ] }, "pmullw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xd5" + "Comment": "0x0f 0xd5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "mul v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pmovmskb eax, mm0": { "ExpectedInstructionCount": 12, "Optimal": "Yes", - "Comment": "0x0f 0xd7" + "Comment": "0x0f 0xd7", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v5.2d, x20", + "cmlt v4.16b, v4.16b, #0", + "and v4.16b, v4.16b, v5.16b", + "addp v4.16b, v4.16b, v4.16b", + "addp v4.8b, v4.8b, v4.8b", + "addp v4.8b, v4.8b, v4.8b", + "umov w4, v4.h[0]" + ] }, "psubusb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xd8" + "Comment": "0x0f 0xd8", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "uqsub v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "psubusw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xd9" + "Comment": "0x0f 0xd9", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "uqsub v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pminub mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xda" + "Comment": "0x0f 0xda", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "umin v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "pand mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xdb" + "Comment": "0x0f 0xdb", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "and v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "paddusb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xdc" + "Comment": "0x0f 0xdc", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "uqadd v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "paddusw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xdd" + "Comment": "0x0f 0xdd", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "uqadd v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pmaxub mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xde" + "Comment": "0x0f 0xde", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "umax v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "pandn mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xdf" + "Comment": "0x0f 0xdf", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "bic v4.16b, v4.16b, v5.16b", + "str d4, [x28, #752]" + ] }, "pavgb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xe0" + "Comment": "0x0f 0xe0", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "urhadd v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "psraw mm0, mm1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xe1" + "Comment": "0x0f 0xe1", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "neg v0.8h, v0.8h", + "sshl v4.8h, v5.8h, v0.8h", + "str d4, [x28, #752]" + ] }, "psrad mm0, mm1": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0x0f 0xe2" + "Comment": "0x0f 0xe2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "neg v0.4s, v0.4s", + "sshl v4.4s, v5.4s, v0.4s", + "str d4, [x28, #752]" + ] }, "pavgw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xe3" + "Comment": "0x0f 0xe3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "urhadd v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pmulhuw mm0, mm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0xe4" + "Comment": "0x0f 0xe4", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "umull v4.4s, v4.4h, v5.4h", + "shrn v4.4h, v4.4s, #16", + "str d4, [x28, #752]" + ] }, "pmulhw mm0, mm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0xe5" + "Comment": "0x0f 0xe5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "smull v4.4s, v4.4h, v5.4h", + "shrn v4.4h, v4.4s, #16", + "str d4, [x28, #752]" + ] }, "movntq [rax], mm0": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x0f 0xe7" + "Comment": "0x0f 0xe7", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x4]" + ] }, "psubsb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xe8" + "Comment": "0x0f 0xe8", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sqsub v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "psubsw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xe9" + "Comment": "0x0f 0xe9", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sqsub v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pminsw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xea" + "Comment": "0x0f 0xea", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "smin v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "por mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xeb" + "Comment": "0x0f 0xeb", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "paddsb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xec" + "Comment": "0x0f 0xec", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sqadd v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "paddsw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xed" + "Comment": "0x0f 0xed", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sqadd v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pmaxsw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xee" + "Comment": "0x0f 0xee", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "smax v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "pxor mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xef" + "Comment": "0x0f 0xef", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "eor v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "psllw mm0, mm1": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xf1" + "Comment": "0x0f 0xf1", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "ushl v4.8h, v5.8h, v0.8h", + "str d4, [x28, #752]" + ] }, "pslld mm0, mm1": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xf2" + "Comment": "0x0f 0xf2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "ushl v4.4s, v5.4s, v0.4s", + "str d4, [x28, #752]" + ] }, "psllq mm0, mm1": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0x0f 0xf3" + "Comment": "0x0f 0xf3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v4.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v4.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.2d, v4.d[0]", + "ushl v4.2d, v5.2d, v0.2d", + "str d4, [x28, #752]" + ] }, "pmuludq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xf4" + "Comment": "0x0f 0xf4", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "umull v4.2d, v4.2s, v5.2s", + "str d4, [x28, #752]" + ] }, "pmaddwd mm0, mm1": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "0x0f 0xf5" + "Comment": "0x0f 0xf5", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "sxtl v6.4s, v4.4h", + "sxtl2 v4.4s, v4.8h", + "sxtl v7.4s, v5.4h", + "sxtl2 v5.4s, v5.8h", + "mul v6.4s, v6.4s, v7.4s", + "mul v4.4s, v4.4s, v5.4s", + "addp v4.4s, v6.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "psadbw mm0, mm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x0f 0xf6" + "Comment": "0x0f 0xf6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ldr d5, [x28, #768]", + "uabdl v4.8h, v4.8b, v5.8b", + "addv h4, v4.8h", + "str d4, [x28, #752]" + ] }, "maskmovq mm0, mm1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x0f 0xf7" + "Comment": "0x0f 0xf7", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "cmlt v4.16b, v4.16b, #0", + "ldr d5, [x28, #752]", + "ldr d6, [x11]", + "mov v0.8b, v4.8b", + "bsl v0.8b, v5.8b, v6.8b", + "mov v4.8b, v0.8b", + "str d4, [x11]" + ] }, "psubb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xf8" + "Comment": "0x0f 0xf8", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sub v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "psubw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xf9" + "Comment": "0x0f 0xf9", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sub v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "psubd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xfa" + "Comment": "0x0f 0xfa", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sub v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "psubq mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xfb" + "Comment": "0x0f 0xfb", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "sub v4.2d, v5.2d, v4.2d", + "str d4, [x28, #752]" + ] }, "paddb mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xfc" + "Comment": "0x0f 0xfc", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "add v4.16b, v5.16b, v4.16b", + "str d4, [x28, #752]" + ] }, "paddw mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xfd" + "Comment": "0x0f 0xfd", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "add v4.8h, v5.8h, v4.8h", + "str d4, [x28, #752]" + ] }, "paddd mm0, mm1": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x0f 0xfe" + "Comment": "0x0f 0xfe", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #768]", + "ldr d5, [x28, #752]", + "add v4.4s, v5.4s, v4.4s", + "str d4, [x28, #752]" + ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 87bb2ae25..93996124c 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -13,573 +13,1709 @@ "sgdt [rax]": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "GROUP7 0x0F 0x1 /0" + "Comment": "GROUP7 0x0F 0x1 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "strh w20, [x4]", + "mov x20, #0xfffffffffffe0000", + "stur x20, [x4, #2]" + ] }, "bt ax, 0": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt eax, 0": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt rax, 0": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt ax, 15": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w20, w20, #15", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt eax, 31": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w20, w20, #31", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bt rax, 63": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /4" + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts ax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "orr x21, x20, #0x1", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts eax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "orr x21, x20, #0x1", + "ubfx x4, x21, #0, #32", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts rax, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "orr x4, x20, #0x1", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts ax, 15": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w21, w20, #15", + "orr x20, x20, #0x8000", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts eax, 31": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w21, w20, #31", + "orr x20, x20, #0x80000000", + "ubfx x4, x20, #0, #32", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "bts rax, 63": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /5" + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "orr x4, x4, #0x8000000000000000", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr ax, 0": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "orr w21, wzr, #0x1", + "bic w21, w20, w21", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr eax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "orr w21, wzr, #0x1", + "bic w4, w20, w21", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr rax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "mov x20, x4", + "orr w21, wzr, #0x1", + "bic x4, x20, x21", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr ax, 15": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w21, w20, #15", + "orr w22, wzr, #0x8000", + "bic w20, w20, w22", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr eax, 31": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w21, w20, #31", + "orr w22, wzr, #0x80000000", + "bic w4, w20, w22", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btr rax, 63": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /6" + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "orr x21, xzr, #0x8000000000000000", + "bic x4, x4, x21", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc ax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "eor x21, x20, #0x1", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc eax, 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "eor x21, x20, #0x1", + "ubfx x4, x21, #0, #32", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc rax, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "eor x4, x20, #0x1", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc ax, 15": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "uxth x20, w4", + "lsr w21, w20, #15", + "eor x20, x20, #0x8000", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc eax, 31": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "lsr w21, w20, #31", + "eor x20, x20, #0x80000000", + "ubfx x4, x20, #0, #32", + "ubfx x20, x21, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "btc rax, 63": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "GROUP8 0x0F 0xBA /7" + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "eor x4, x4, #0x8000000000000000", + "ubfx x20, x20, #0, #1", + "ldr w21, [x28, #728]", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "cmpxchg8b [rbp]": { "ExpectedInstructionCount": 25, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /1" + "Comment": "GROUP9 0x0F 0xC7 /1", + "ExpectedArm64ASM": [ + "add x20, x9, #0x0 (0)", + "ubfx x21, x4, #0, #32", + "ubfx x22, x6, #0, #32", + "mov w23, w22", + "mov w22, w21", + "ubfx x21, x7, #0, #32", + "ubfx x24, x5, #0, #32", + "mov w25, w24", + "mov w24, w21", + "mov w2, w22", + "mov w3, w23", + "caspal w2, w3, w24, w25, [x20]", + "mov w20, w2", + "mov w21, w3", + "mov w24, w20", + "mov w25, w21", + "cmp x20, x22", + "ccmp x21, x23, #nzcv, eq", + "cset x20, eq", + "ldr w21, [x28, #728]", + "bfi w21, w20, #30, #1", + "str w21, [x28, #728]", + "cbnz x20, #+0xc", + "mov x4, x24", + "mov x6, x25" + ] }, "cmpxchg16b [rbp]": { "ExpectedInstructionCount": 21, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /1" + "Comment": "GROUP9 0x0F 0xC7 /1", + "ExpectedArm64ASM": [ + "add x20, x9, #0x0 (0)", + "mov x22, x4", + "mov x23, x6", + "mov x24, x7", + "mov x25, x5", + "mov x2, x22", + "mov x3, x23", + "caspal x2, x3, x24, x25, [x20]", + "mov x20, x2", + "mov x21, x3", + "mov x24, x20", + "mov x25, x21", + "cmp x20, x22", + "ccmp x21, x23, #nzcv, eq", + "cset x20, eq", + "ldr w21, [x28, #728]", + "bfi w21, w20, #30, #1", + "str w21, [x28, #728]", + "cbnz x20, #+0xc", + "mov x4, x24", + "mov x6, x25" + ] }, "rdrand ax": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /6" + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "bfxil x4, x22, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "rdrand eax": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /6" + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "ubfx x4, x22, #0, #32", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "rdrand rax": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /6" + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x4, x20", + "mov x20, x21", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "rdseed ax": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /7" + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "bfxil x4, x22, #0, #16", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "rdseed eax": { "ExpectedInstructionCount": 10, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /7" + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "ubfx x4, x22, #0, #32", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "rdseed rax": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "GROUP9 0x0F 0xC7 /7" + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x4, x20", + "mov x20, x21", + "mov w21, #0x0", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] }, "psrlw mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psrlw mm0, 15": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ushr v4.8h, v4.8h, #15", + "str d4, [x28, #752]" + ] }, "psrlw mm0, 16": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "psrlw xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psrlw xmm0, 15": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.8h, v16.8h, #15" + ] }, "psrlw xmm0, 16": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /2" + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psraw mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psraw mm0, 15": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "sshr v4.8h, v4.8h, #15", + "str d4, [x28, #752]" + ] }, "psraw mm0, 16": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "sshr v4.8h, v4.8h, #15", + "str d4, [x28, #752]" + ] }, "psraw xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psraw xmm0, 15": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.8h, v16.8h, #15" + ] }, "psraw xmm0, 16": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /3" + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.8h, v16.8h, #15" + ] }, "psllw mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psllw mm0, 15": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "shl v4.8h, v4.8h, #15", + "str d4, [x28, #752]" + ] }, "psllw mm0, 16": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "psllw xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psllw xmm0, 15": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.8h, v16.8h, #15" + ] }, "psllw xmm0, 16": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP12 0x0F 0xC7 /6" + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psrld mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psrld mm0, 31": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ushr v4.4s, v4.4s, #31", + "str d4, [x28, #752]" + ] }, "psrld mm0, 32": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "psrld xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psrld xmm0, 31": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.4s, v16.4s, #31" + ] }, "psrld xmm0, 32": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /2" + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psrad mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psrad mm0, 31": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "sshr v4.4s, v4.4s, #31", + "str d4, [x28, #752]" + ] }, "psrad mm0, 32": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "sshr v4.4s, v4.4s, #31", + "str d4, [x28, #752]" + ] }, "psrad xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psrad xmm0, 31": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.4s, v16.4s, #31" + ] }, "psrad xmm0, 32": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /3" + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.4s, v16.4s, #31" + ] }, "pslld mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "pslld mm0, 31": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "shl v4.4s, v4.4s, #31", + "str d4, [x28, #752]" + ] }, "pslld mm0, 32": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "pslld xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "pslld xmm0, 31": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.4s, v16.4s, #31" + ] }, "pslld xmm0, 32": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP13 0x0F 0xC7 /6" + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psrlq mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psrlq mm0, 63": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "ushr v4.2d, v4.2d, #63", + "str d4, [x28, #752]" + ] }, "psrlq mm0, 64": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "psrlq xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psrlq xmm0, 63": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.2d, v16.2d, #63" + ] }, "psrlq xmm0, 64": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /2" + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psrldq xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /3" + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "ext v16.16b, v16.16b, v4.16b, #0" + ] }, "psrldq xmm0, 15": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /3" + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "ext v16.16b, v16.16b, v4.16b, #15" + ] }, "psrldq xmm0, 16": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /3" + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "psllq mm0, 0": { "ExpectedInstructionCount": 2, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "str d4, [x28, #752]" + ] }, "psllq mm0, 63": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "Yes", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "shl v4.2d, v4.2d, #63", + "str d4, [x28, #752]" + ] }, "psllq mm0, 64": { "ExpectedInstructionCount": 3, "Type": "MMX", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "movi v4.2d, #0x0", + "str d4, [x28, #752]" + ] }, "psllq xmm0, 0": { "ExpectedInstructionCount": 2, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mov v4.16b, v16.16b", + "mov v16.16b, v4.16b" + ] }, "psllq xmm0, 63": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "Yes", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.2d, v16.2d, #63" + ] }, "psllq xmm0, 64": { "ExpectedInstructionCount": 1, "Type": "SSE", "Optimal": "No", - "Comment": "GROUP14 0x0F 0xC7 /6" + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] }, "fxsave [rax]": { "ExpectedInstructionCount": 73, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /0" + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "strh w20, [x4]", + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "lsl w21, w21, #11", + "orr x20, x20, x21", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "lsl w21, w21, #8", + "orr x20, x20, x21", + "lsl w21, w22, #9", + "orr x20, x20, x21", + "lsl w21, w23, #10", + "orr x20, x20, x21", + "lsl w21, w24, #14", + "orr x20, x20, x21", + "strh w20, [x4, #2]", + "ldrh w20, [x28, #1010]", + "strh w20, [x4, #4]", + "ldr q4, [x28, #752]", + "str q4, [x4, #32]", + "ldr q4, [x28, #768]", + "str q4, [x4, #48]", + "ldr q4, [x28, #784]", + "str q4, [x4, #64]", + "ldr q4, [x28, #800]", + "str q4, [x4, #80]", + "ldr q4, [x28, #816]", + "str q4, [x4, #96]", + "ldr q4, [x28, #832]", + "str q4, [x4, #112]", + "ldr q4, [x28, #848]", + "str q4, [x4, #128]", + "ldr q4, [x28, #864]", + "str q4, [x4, #144]", + "str q16, [x4, #160]", + "str q17, [x4, #176]", + "str q18, [x4, #192]", + "str q19, [x4, #208]", + "str q20, [x4, #224]", + "str q21, [x4, #240]", + "str q22, [x4, #256]", + "str q23, [x4, #272]", + "str q24, [x4, #288]", + "str q25, [x4, #304]", + "str q26, [x4, #320]", + "str q27, [x4, #336]", + "str q28, [x4, #352]", + "str q29, [x4, #368]", + "str q30, [x4, #384]", + "str q31, [x4, #400]", + "orr w20, wzr, #0x1f80", + "mrs x21, fpcr", + "lsr x21, x21, #22", + "and x0, x21, #0x3", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, xzr, eq", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "orr x21, x21, x1", + "bfxil x21, x1, #0, #2", + "bfi w20, w21, #13, #3", + "add x21, x4, #0x18 (24)", + "str w20, [x4, #24]", + "orr w20, wzr, #0xffff", + "str w20, [x21, #4]" + ] }, "rdfsbase eax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /0" + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldr w4, [x28, #176]" + ] }, "rdfsbase rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /0" + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldr x4, [x28, #176]" + ] }, "fxrstor [rax]": { "ExpectedInstructionCount": 103, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /1" + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w20", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w20, [x28, #1008]", + "ldrh w20, [x4, #2]", + "ubfx x21, x20, #11, #3", + "strb w21, [x28, #747]", + "ubfx x21, x20, #8, #1", + "ubfx x22, x20, #9, #1", + "ubfx x23, x20, #10, #1", + "ubfx x20, x20, #14, #1", + "strb w21, [x28, #744]", + "strb w22, [x28, #745]", + "strb w23, [x28, #746]", + "strb w20, [x28, #750]", + "ldrh w20, [x4, #4]", + "strh w20, [x28, #1010]", + "ldr q4, [x4, #32]", + "str q4, [x28, #752]", + "ldr q4, [x4, #48]", + "str q4, [x28, #768]", + "ldr q4, [x4, #64]", + "str q4, [x28, #784]", + "ldr q4, [x4, #80]", + "str q4, [x28, #800]", + "ldr q4, [x4, #96]", + "str q4, [x28, #816]", + "ldr q4, [x4, #112]", + "str q4, [x28, #832]", + "ldr q4, [x4, #128]", + "str q4, [x28, #848]", + "ldr q4, [x4, #144]", + "str q4, [x28, #864]", + "ldr q16, [x4, #160]", + "ldr q17, [x4, #176]", + "ldr q18, [x4, #192]", + "ldr q19, [x4, #208]", + "ldr q20, [x4, #224]", + "ldr q21, [x4, #240]", + "ldr q22, [x4, #256]", + "ldr q23, [x4, #272]", + "ldr q24, [x4, #288]", + "ldr q25, [x4, #304]", + "ldr q26, [x4, #320]", + "ldr q27, [x4, #336]", + "ldr q28, [x4, #352]", + "ldr q29, [x4, #368]", + "ldr q30, [x4, #384]", + "ldr q31, [x4, #400]", + "ldr w20, [x4, #24]", + "ubfx x20, x20, #13, #3", + "and x0, x20, #0x3", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, xzr, eq", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" + ] }, "rdgsbase eax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /1" + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldr w4, [x28, #168]" + ] }, "rdgsbase rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /1" + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldr x4, [x28, #168]" + ] }, "ldmxcsr [rax]": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /2" + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "ubfx x20, x20, #13, #3", + "and x0, x20, #0x3", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, xzr, eq", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" + ] }, "wrfsbase eax": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /2" + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "str x20, [x28, #176]" + ] }, "wrfsbase rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /2" + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "str x4, [x28, #176]" + ] }, "stmxcsr [rax]": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /3" + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1f80", + "mrs x21, fpcr", + "lsr x21, x21, #22", + "and x0, x21, #0x3", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, xzr, eq", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "orr x21, x21, x1", + "bfxil x21, x1, #0, #2", + "bfi w20, w21, #13, #3", + "str w20, [x4]" + ] }, "wrgsbase eax": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /3" + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "str x20, [x28, #168]" + ] }, "wrgsbase rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /3" + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "str x4, [x28, #168]" + ] }, "xsave [rax]": { "ExpectedInstructionCount": 86, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /4" + "Comment": "GROUP15 0x0F 0xAE /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x21, x4", + "ubfx x22, x20, #0, #1", + "cbnz x22, #+0x8", + "b #+0x98", + "ldrh w22, [x28, #1008]", + "strh w22, [x21]", + "mov w22, #0x0", + "ldrb w23, [x28, #747]", + "lsl w23, w23, #11", + "orr x22, x22, x23", + "ldrb w23, [x28, #744]", + "ldrb w24, [x28, #745]", + "ldrb w25, [x28, #746]", + "ldrb w26, [x28, #750]", + "lsl w23, w23, #8", + "orr x22, x22, x23", + "lsl w23, w24, #9", + "orr x22, x22, x23", + "lsl w23, w25, #10", + "orr x22, x22, x23", + "lsl w23, w26, #14", + "orr x22, x22, x23", + "strh w22, [x21, #2]", + "ldrh w22, [x28, #1010]", + "strh w22, [x21, #4]", + "ldr q4, [x28, #752]", + "str q4, [x21, #32]", + "ldr q4, [x28, #768]", + "str q4, [x21, #48]", + "ldr q4, [x28, #784]", + "str q4, [x21, #64]", + "ldr q4, [x28, #800]", + "str q4, [x21, #80]", + "ldr q4, [x28, #816]", + "str q4, [x21, #96]", + "ldr q4, [x28, #832]", + "str q4, [x21, #112]", + "ldr q4, [x28, #848]", + "str q4, [x21, #128]", + "ldr q4, [x28, #864]", + "str q4, [x21, #144]", + "ubfx x22, x20, #1, #1", + "cbnz x22, #+0x8", + "b #+0x44", + "str q16, [x21, #160]", + "str q17, [x21, #176]", + "str q18, [x21, #192]", + "str q19, [x21, #208]", + "str q20, [x21, #224]", + "str q21, [x21, #240]", + "str q22, [x21, #256]", + "str q23, [x21, #272]", + "str q24, [x21, #288]", + "str q25, [x21, #304]", + "str q26, [x21, #320]", + "str q27, [x21, #336]", + "str q28, [x21, #352]", + "str q29, [x21, #368]", + "str q30, [x21, #384]", + "str q31, [x21, #400]", + "ubfx x22, x20, #1, #2", + "cbnz x22, #+0x8", + "b #+0x54", + "orr w22, wzr, #0x1f80", + "mrs x23, fpcr", + "lsr x23, x23, #22", + "and x0, x23, #0x3", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, xzr, eq", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "orr x23, x23, x1", + "bfxil x23, x1, #0, #2", + "bfi w22, w23, #13, #3", + "add x23, x21, #0x18 (24)", + "str w22, [x21, #24]", + "orr w22, wzr, #0xffff", + "str w22, [x23, #4]", + "ubfx x20, x20, #0, #3", + "str x20, [x21, #512]" + ] }, "lfence": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /5" + "Comment": "GROUP15 0x0F 0xAE /5", + "ExpectedArm64ASM": [ + "dmb ld" + ] }, "xrstor [rax]": { "ExpectedInstructionCount": 191, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /5" + "Comment": "GROUP15 0x0F 0xAE /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr x21, [x20, #512]", + "ubfx x22, x21, #0, #1", + "cbnz x22, #+0x8", + "b #+0x120", + "ldrh w22, [x20]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w22", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w22, [x28, #1008]", + "ldrh w22, [x20, #2]", + "ubfx x23, x22, #11, #3", + "strb w23, [x28, #747]", + "ubfx x23, x22, #8, #1", + "ubfx x24, x22, #9, #1", + "ubfx x25, x22, #10, #1", + "ubfx x22, x22, #14, #1", + "strb w23, [x28, #744]", + "strb w24, [x28, #745]", + "strb w25, [x28, #746]", + "strb w22, [x28, #750]", + "ldrh w22, [x20, #4]", + "strh w22, [x28, #1010]", + "ldr q4, [x20, #32]", + "str q4, [x28, #752]", + "ldr q4, [x20, #48]", + "str q4, [x28, #768]", + "ldr q4, [x20, #64]", + "str q4, [x28, #784]", + "ldr q4, [x20, #80]", + "str q4, [x28, #800]", + "ldr q4, [x20, #96]", + "str q4, [x28, #816]", + "ldr q4, [x20, #112]", + "str q4, [x28, #832]", + "ldr q4, [x20, #128]", + "str q4, [x28, #848]", + "ldr q4, [x20, #144]", + "str q4, [x28, #864]", + "b #+0xec", + "mov w22, #0x0", + "mov w23, #0x37f", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w23", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w23, [x28, #1008]", + "strb w22, [x28, #747]", + "strb w22, [x28, #744]", + "strb w22, [x28, #745]", + "strb w22, [x28, #746]", + "strb w22, [x28, #750]", + "orr w22, wzr, #0xffff", + "strh w22, [x28, #1010]", + "movi v4.2d, #0x0", + "str q4, [x28, #752]", + "str q4, [x28, #768]", + "str q4, [x28, #784]", + "str q4, [x28, #800]", + "str q4, [x28, #816]", + "str q4, [x28, #832]", + "str q4, [x28, #848]", + "str q4, [x28, #864]", + "ubfx x22, x21, #1, #1", + "cbnz x22, #+0x8", + "b #+0x48", + "ldr q16, [x20, #160]", + "ldr q17, [x20, #176]", + "ldr q18, [x20, #192]", + "ldr q19, [x20, #208]", + "ldr q20, [x20, #224]", + "ldr q21, [x20, #240]", + "ldr q22, [x20, #256]", + "ldr q23, [x20, #272]", + "ldr q24, [x20, #288]", + "ldr q25, [x20, #304]", + "ldr q26, [x20, #320]", + "ldr q27, [x20, #336]", + "ldr q28, [x20, #352]", + "ldr q29, [x20, #368]", + "ldr q30, [x20, #384]", + "ldr q31, [x20, #400]", + "b #+0x44", + "movi v16.2d, #0x0", + "mov v17.16b, v16.16b", + "mov v18.16b, v16.16b", + "mov v19.16b, v16.16b", + "mov v20.16b, v16.16b", + "mov v21.16b, v16.16b", + "mov v22.16b, v16.16b", + "mov v23.16b, v16.16b", + "mov v24.16b, v16.16b", + "mov v25.16b, v16.16b", + "mov v26.16b, v16.16b", + "mov v27.16b, v16.16b", + "mov v28.16b, v16.16b", + "mov v29.16b, v16.16b", + "mov v30.16b, v16.16b", + "mov v31.16b, v16.16b", + "ubfx x21, x21, #1, #2", + "cbnz x21, #+0x8", + "b #+0x4c", + "ldr w20, [x20, #24]", + "ubfx x20, x20, #13, #3", + "and x0, x20, #0x3", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, xzr, eq", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "b #+0x4" + ] }, "mfence": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /6" + "Comment": "GROUP15 0x0F 0xAE /6", + "ExpectedArm64ASM": [ + "dmb sy" + ] }, "clwb [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /6" + "Comment": "GROUP15 0x0F 0xAE /6", + "ExpectedArm64ASM": [ + "mov x0, x4", + "dc cvac, x0", + "add x0, x0, #0x40 (64)" + ] }, "sfence": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "GROUP15 0x0F 0xAE /7" + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "dmb st" + ] }, "clflush [rax]": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /7" + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "mov x0, x4", + "dc civac, x0", + "add x0, x0, #0x40 (64)", + "dsb ish" + ] }, "clflushopt [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "GROUP15 0x0F 0xAE /7" + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "mov x0, x4", + "dc civac, x0", + "add x0, x0, #0x40 (64)" + ] }, "prefetchnta [rax]": { "ExpectedInstructionCount": 0, @@ -587,7 +1723,8 @@ "Comment": [ "GROUP16 0x0F 0x18 /0", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "prefetcht0 [rax]": { "ExpectedInstructionCount": 0, @@ -595,7 +1732,8 @@ "Comment": [ "GROUP16 0x0F 0x18 /1", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "prefetcht1 [rax]": { "ExpectedInstructionCount": 0, @@ -603,7 +1741,8 @@ "Comment": [ "GROUP16 0x0F 0x18 /2", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "prefetcht2 [rax]": { "ExpectedInstructionCount": 0, @@ -611,7 +1750,8 @@ "Comment": [ "GROUP16 0x0F 0x18 /3", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "db 0x0f, 0x18, 0x20;": { "ExpectedInstructionCount": 0, @@ -620,7 +1760,8 @@ "GROUP16 0x0F 0x18 /4", "nop dword [rax]", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "db 0x0f, 0x0d, 0x00": { "ExpectedInstructionCount": 0, @@ -629,7 +1770,8 @@ "GROUPP 0x0F 0x0D /0", "prefetch_exclusive [rax]", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "prefetchw [rax]": { "ExpectedInstructionCount": 0, @@ -637,7 +1779,8 @@ "Comment": [ "GROUPP 0x0F 0x0D /1", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] }, "prefetchwt1 [rax]": { "ExpectedInstructionCount": 0, @@ -645,7 +1788,8 @@ "Comment": [ "GROUPP 0x0F 0x0D /2", "NOP implementation" - ] + ], + "ExpectedArm64ASM": [] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index f4961f5f2..47095b7f3 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -13,17 +13,85 @@ "xgetbv": { "ExpectedInstructionCount": 44, "Optimal": "No", - "Comment": "0xF 0x01 /2 RM-0" + "Comment": "0xF 0x01 /2 RM-0", + "ExpectedArm64ASM": [ + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "ldr x0, [x28, #1096]", + "ldr x2, [x28, #1112]", + "mov w1, w5", + "blr x2", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "mov w20, w0", + "lsr x21, x0, #32", + "mov w4, w20", + "mov w6, w21" + ] }, "rdtscp": { "ExpectedInstructionCount": 17, "Optimal": "No", - "Comment": "0xF 0x01 /7 RM-1" + "Comment": "0xF 0x01 /7 RM-1", + "ExpectedArm64ASM": [ + "dmb ld", + "mrs x20, S3_3_c14_c0_2", + "ubfx x4, x20, #0, #32", + "lsr x6, x20, #32", + "str x8, [x28, #40]", + "orr w0, wzr, #0x100", + "str x0, [x28, #1040]", + "sub sp, sp, #0x10 (16)", + "mov w8, #0xa8", + "mov x0, sp", + "add x1, sp, #0x4 (4)", + "svc #0x0", + "ldp w0, w1, [sp]", + "sub sp, sp, #0x10 (16)", + "ldr x8, [x28, #40]", + "str xzr, [x28, #1040]", + "orr x5, x0, x1, lsl #12" + ] }, "clzero rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xF 0x01 /7 RM-4" + "Comment": "0xF 0x01 /7 RM-4", + "ExpectedArm64ASM": [ + "dc zva, x4" + ] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index fbff01824..834d25d84 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -11,22 +11,58 @@ "push fs": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xa0" + "Comment": "0x0f 0xa0", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #146]", + "str w21, [x20]" + ] }, "pop fs": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xa1" + "Comment": "0x0f 0xa1", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "strh w21, [x28, #146]", + "ubfx x20, x21, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #176]" + ] }, "push gs": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x0f 0xa8" + "Comment": "0x0f 0xa8", + "ExpectedArm64ASM": [ + "mov w20, w8", + "sub x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "ldrh w21, [x28, #144]", + "str w21, [x20]" + ] }, "pop gs": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x0f 0xa9" + "Comment": "0x0f 0xa9", + "ExpectedArm64ASM": [ + "mov w20, w8", + "ldr w21, [x20]", + "add x20, x20, #0x4 (4)", + "bfxil x8, x20, #0, #32", + "strh w21, [x28, #144]", + "ubfx x20, x21, #3, #13", + "add x0, x28, x20, lsl #2", + "ldr w20, [x0, #880]", + "str w20, [x28, #168]" + ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 4abfe8b16..23f8f3ce2 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -11,327 +11,658 @@ "movupd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x10" + "Comment": "0x66 0x0f 0x10", + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b" + ] }, "movupd xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x10" + "Comment": "0x66 0x0f 0x10", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "movupd [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x11" + "Comment": "0x66 0x0f 0x11", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "movlpd xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x12" + "Comment": "0x66 0x0f 0x12", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v16.d[0], v4.d[0]" + ] }, "movlpd [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x13" + "Comment": "0x66 0x0f 0x13", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "str d4, [x4]" + ] }, "unpcklpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x14" + "Comment": "0x66 0x0f 0x14", + "ExpectedArm64ASM": [ + "zip1 v16.2d, v16.2d, v17.2d" + ] }, "unpckhpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x15" + "Comment": "0x66 0x0f 0x15", + "ExpectedArm64ASM": [ + "zip2 v16.2d, v16.2d, v17.2d" + ] }, "movhpd xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x16" + "Comment": "0x66 0x0f 0x16", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v16.d[1], v4.d[0]" + ] }, "movhpd [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x17" + "Comment": "0x66 0x0f 0x17", + "ExpectedArm64ASM": [ + "mov x20, v16.d[1]", + "str x20, [x4]" + ] }, "movapd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x28" + "Comment": "0x66 0x0f 0x28", + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b" + ] }, "movapd xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x28" + "Comment": "0x66 0x0f 0x28", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "movapd [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x29" + "Comment": "0x66 0x0f 0x29", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "cvtpi2pd xmm0, mm0": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x2a" + "Comment": "0x66 0x0f 0x2a", + "ExpectedArm64ASM": [ + "ldr d4, [x28, #752]", + "sxtl v4.2d, v4.2s", + "scvtf v16.2d, v4.2d" + ] }, "movntpd [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x2b" + "Comment": "0x66 0x0f 0x2b", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "cvttpd2pi mm0, xmm0": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x2c" + "Comment": "0x66 0x0f 0x2c", + "ExpectedArm64ASM": [ + "fcvtn v4.2s, v16.2d", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "cvtpd2pi mm0, xmm0": { "ExpectedInstructionCount": 4, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x2d" + "Comment": "0x66 0x0f 0x2d", + "ExpectedArm64ASM": [ + "fcvtn v4.2s, v16.2d", + "frinti v4.4s, v4.4s", + "fcvtzs v4.4s, v4.4s", + "str d4, [x28, #752]" + ] }, "ucomisd xmm0, xmm1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x66 0x0f 0x2e" + "Comment": "0x66 0x0f 0x2e", + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "comisd xmm0, xmm1": { "ExpectedInstructionCount": 23, "Optimal": "No", - "Comment": "0x66 0x0f 0x2f" + "Comment": "0x66 0x0f 0x2f", + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" + ] }, "movmskpd eax, xmm0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0x50" + "Comment": "0x66 0x0f 0x50", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov x21, v16.d[0]", + "lsr x21, x21, #63", + "orr x20, x20, x21", + "mov x21, v16.d[1]", + "lsr x21, x21, #63", + "lsl x21, x21, #1", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" + ] }, "sqrtpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x51" + "Comment": "0x66 0x0f 0x51", + "ExpectedArm64ASM": [ + "fsqrt v16.2d, v17.2d" + ] }, "addpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x58" + "Comment": "0x66 0x0f 0x58", + "ExpectedArm64ASM": [ + "fadd v16.2d, v16.2d, v17.2d" + ] }, "mulpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x59" + "Comment": "0x66 0x0f 0x59", + "ExpectedArm64ASM": [ + "fmul v16.2d, v16.2d, v17.2d" + ] }, "cvtpd2ps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x5a" + "Comment": "0x66 0x0f 0x5a", + "ExpectedArm64ASM": [ + "fcvtn v16.2s, v17.2d" + ] }, "cvtpd2ps xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x5a" + "Comment": "0xf2 0x0f 0x5a", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "fcvtn v16.2s, v4.2d" + ] }, "cvtps2dq xmm0, xmm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x5b" + "Comment": "0x66 0x0f 0x5b", + "ExpectedArm64ASM": [ + "frinti v16.4s, v17.4s", + "fcvtzs v16.4s, v16.4s" + ] }, "cvtps2dq xmm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x5b" + "Comment": "0xf2 0x0f 0x5b", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "frinti v16.4s, v4.4s", + "fcvtzs v16.4s, v16.4s" + ] }, "subpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x5c" + "Comment": "0x66 0x0f 0x5c", + "ExpectedArm64ASM": [ + "fsub v16.2d, v16.2d, v17.2d" + ] }, "minpd xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x66 0x0f 0x5d" + "Comment": "0x66 0x0f 0x5d", + "ExpectedArm64ASM": [ + "fcmgt v0.2d, v17.2d, v16.2d", + "mov v1.16b, v16.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v16.16b, v1.16b" + ] }, "divpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x5e" + "Comment": "0x66 0x0f 0x5e", + "ExpectedArm64ASM": [ + "fdiv v16.2d, v16.2d, v17.2d" + ] }, "maxpd xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x66 0x0f 0x5f" + "Comment": "0x66 0x0f 0x5f", + "ExpectedArm64ASM": [ + "fcmgt v0.2d, v17.2d, v16.2d", + "mov v1.16b, v16.16b", + "bit v1.16b, v17.16b, v0.16b", + "mov v16.16b, v1.16b" + ] }, "punpcklbw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x60" + "Comment": "0x66 0x0f 0x60", + "ExpectedArm64ASM": [ + "zip1 v16.16b, v16.16b, v17.16b" + ] }, "punpcklbw xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x60" + "Comment": "0x66 0x0f 0x60", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip1 v16.16b, v16.16b, v4.16b" + ] }, "punpcklwd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x61" + "Comment": "0x66 0x0f 0x61", + "ExpectedArm64ASM": [ + "zip1 v16.8h, v16.8h, v17.8h" + ] }, "punpcklwd xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x61" + "Comment": "0x66 0x0f 0x61", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip1 v16.8h, v16.8h, v4.8h" + ] }, "punpckldq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x62" + "Comment": "0x66 0x0f 0x62", + "ExpectedArm64ASM": [ + "zip1 v16.4s, v16.4s, v17.4s" + ] }, "punpckldq xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x62" + "Comment": "0x66 0x0f 0x62", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip1 v16.4s, v16.4s, v4.4s" + ] }, "packsswb xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x66 0x0f 0x63" + "Comment": "0x66 0x0f 0x63", + "ExpectedArm64ASM": [ + "sqxtn v4.8b, v16.8h", + "mov v0.16b, v4.16b", + "sqxtn2 v0.16b, v17.8h", + "mov v16.16b, v0.16b" + ] }, "packsswb xmm0, [rax]": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0x66 0x0f 0x63" + "Comment": "0x66 0x0f 0x63", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "sqxtn v5.8b, v16.8h", + "mov v0.16b, v5.16b", + "sqxtn2 v0.16b, v4.8h", + "mov v16.16b, v0.16b" + ] }, "pcmpgtb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x64" + "Comment": "0x66 0x0f 0x64", + "ExpectedArm64ASM": [ + "cmgt v16.16b, v16.16b, v17.16b" + ] }, "pcmpgtw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x65" + "Comment": "0x66 0x0f 0x65", + "ExpectedArm64ASM": [ + "cmgt v16.8h, v16.8h, v17.8h" + ] }, "pcmpgtd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x66" + "Comment": "0x66 0x0f 0x66", + "ExpectedArm64ASM": [ + "cmgt v16.4s, v16.4s, v17.4s" + ] }, "punpckhbw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x68" + "Comment": "0x66 0x0f 0x68", + "ExpectedArm64ASM": [ + "zip2 v16.16b, v16.16b, v17.16b" + ] }, "punpckhbw xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x68" + "Comment": "0x66 0x0f 0x68", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip2 v16.16b, v16.16b, v4.16b" + ] }, "punpckhwd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x69" + "Comment": "0x66 0x0f 0x69", + "ExpectedArm64ASM": [ + "zip2 v16.8h, v16.8h, v17.8h" + ] }, "punpckhwd xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x69" + "Comment": "0x66 0x0f 0x69", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip2 v16.8h, v16.8h, v4.8h" + ] }, "punpckhdq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6a" + "Comment": "0x66 0x0f 0x6a", + "ExpectedArm64ASM": [ + "zip2 v16.4s, v16.4s, v17.4s" + ] }, "punpckhdq xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6a" + "Comment": "0x66 0x0f 0x6a", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "zip2 v16.4s, v16.4s, v4.4s" + ] }, "packssdw xmm0, xmm1": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0x66 0x0f 0x6b" + "Comment": "0x66 0x0f 0x6b", + "ExpectedArm64ASM": [ + "sqxtn v4.4h, v16.4s", + "mov v0.16b, v4.16b", + "sqxtn2 v0.8h, v17.4s", + "mov v16.16b, v0.16b" + ] }, "punpcklqdq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6c" + "Comment": "0x66 0x0f 0x6c", + "ExpectedArm64ASM": [ + "zip1 v16.2d, v16.2d, v17.2d" + ] }, "punpckhqdq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6d" + "Comment": "0x66 0x0f 0x6d", + "ExpectedArm64ASM": [ + "zip2 v16.2d, v16.2d, v17.2d" + ] }, "movd xmm0, dword [rax]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x6e" + "Comment": "0x66 0x0f 0x6e", + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "fmov s16, w20" + ] }, "movd xmm0, eax": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x6e" + "Comment": "0x66 0x0f 0x6e", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "fmov s16, w20" + ] }, "movq xmm0, qword [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6e" + "Comment": "0x66 0x0f 0x6e", + "ExpectedArm64ASM": [ + "ldr d16, [x4]" + ] }, "movq xmm0, rax": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6e" + "Comment": "0x66 0x0f 0x6e", + "ExpectedArm64ASM": [ + "fmov d16, x4" + ] }, "movdqa xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6f" + "Comment": "0x66 0x0f 0x6f", + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b" + ] }, "movdqa xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x6f" + "Comment": "0x66 0x0f 0x6f", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "pshufd xmm0, xmm1, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[0]", + "mov v4.s[2], v17.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[0]", + "mov v16.16b, v0.16b" + ] }, "pshufd xmm0, [rax], 0": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v16.16b, v0.16b" + ] }, "pshufd xmm0, xmm1, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.s[0], v17.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[0]", + "mov v4.s[2], v17.s[0]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[0]", + "mov v16.16b, v0.16b" + ] }, "pshufd xmm0, [rax], 1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[1]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v16.16b, v0.16b" + ] }, "pshufd xmm0, xmm1, 0xff": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.s[0], v17.s[3]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v17.s[3]", + "mov v4.s[2], v17.s[3]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v17.s[3]", + "mov v16.16b, v0.16b" + ] }, "pshufd xmm0, [rax], 0xff": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0x70" + "Comment": "0x66 0x0f 0x70", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[3]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[3]", + "mov v5.s[2], v4.s[3]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v16.16b, v0.16b" + ] }, "pcmpeqb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x74" + "Comment": "0x66 0x0f 0x74", + "ExpectedArm64ASM": [ + "cmeq v16.16b, v16.16b, v17.16b" + ] }, "pcmpeqw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x75" + "Comment": "0x66 0x0f 0x75", + "ExpectedArm64ASM": [ + "cmeq v16.8h, v16.8h, v17.8h" + ] }, "pcmpeqd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x76" + "Comment": "0x66 0x0f 0x76", + "ExpectedArm64ASM": [ + "cmeq v16.4s, v16.4s, v17.4s" + ] }, "extrq xmm0, 64, 0": { "ExpectedInstructionCount": 7, @@ -372,252 +703,519 @@ "haddpd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x7c" + "Comment": "0x66 0x0f 0x7c", + "ExpectedArm64ASM": [ + "faddp v16.2d, v16.2d, v17.2d" + ] }, "hsubpd xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0x7c" + "Comment": "0x66 0x0f 0x7c", + "ExpectedArm64ASM": [ + "fneg v4.2d, v16.2d", + "fneg v5.2d, v17.2d", + "mov v0.16b, v16.16b", + "mov v0.d[1], v4.d[1]", + "mov v4.16b, v0.16b", + "mov v0.16b, v17.16b", + "mov v0.d[1], v5.d[1]", + "mov v5.16b, v0.16b", + "faddp v16.2d, v4.2d, v5.2d" + ] }, "movd dword [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x7e" + "Comment": "0x66 0x0f 0x7e", + "ExpectedArm64ASM": [ + "mov w20, v16.s[0]", + "str w20, [x4]" + ] }, "movq qword [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0x66 0x0f 0x7e" + "Comment": "0x66 0x0f 0x7e", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "str d4, [x4]" + ] }, "movdqa [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0x7f" + "Comment": "0x66 0x0f 0x7f", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "addsubpd xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd0" + "Comment": "0x66 0x0f 0xd0", + "ExpectedArm64ASM": [ + "fadd v4.2d, v16.2d, v17.2d", + "fsub v5.2d, v16.2d, v17.2d", + "uzp1 v5.2d, v5.2d, v5.2d", + "uzp2 v4.2d, v4.2d, v4.2d", + "zip1 v16.2d, v5.2d, v4.2d" + ] }, "psrlw xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0xd1" + "Comment": "0x66 0x0f 0xd1", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x10", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "neg v0.8h, v0.8h", + "ushl v16.8h, v16.8h, v0.8h" + ] }, "psrld xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0xd2" + "Comment": "0x66 0x0f 0xd2", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x20", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "neg v0.4s, v0.4s", + "ushl v16.4s, v16.4s, v0.4s" + ] }, "psrlq xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0xd3" + "Comment": "0x66 0x0f 0xd3", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x40", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.2d, v4.d[0]", + "neg v0.2d, v0.2d", + "ushl v16.2d, v16.2d, v0.2d" + ] }, "paddq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd4" + "Comment": "0x66 0x0f 0xd4", + "ExpectedArm64ASM": [ + "add v16.2d, v16.2d, v17.2d" + ] }, "pmullw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd3" + "Comment": "0x66 0x0f 0xd3", + "ExpectedArm64ASM": [ + "mul v16.8h, v16.8h, v17.8h" + ] }, "pmovmskb eax, xmm0": { "ExpectedInstructionCount": 11, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd7" + "Comment": "0x66 0x0f 0xd7", + "ExpectedArm64ASM": [ + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v4.2d, x20", + "cmlt v5.16b, v16.16b, #0", + "and v4.16b, v5.16b, v4.16b", + "addp v4.16b, v4.16b, v4.16b", + "addp v4.8b, v4.8b, v4.8b", + "addp v4.8b, v4.8b, v4.8b", + "umov w4, v4.h[0]" + ] }, "psubusb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd8" + "Comment": "0x66 0x0f 0xd8", + "ExpectedArm64ASM": [ + "uqsub v16.16b, v16.16b, v17.16b" + ] }, "psubusw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xd9" + "Comment": "0x66 0x0f 0xd9", + "ExpectedArm64ASM": [ + "uqsub v16.8h, v16.8h, v17.8h" + ] }, "pminub xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xda" + "Comment": "0x66 0x0f 0xda", + "ExpectedArm64ASM": [ + "umin v16.16b, v16.16b, v17.16b" + ] }, "pand xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xdb" + "Comment": "0x66 0x0f 0xdb", + "ExpectedArm64ASM": [ + "and v16.16b, v16.16b, v17.16b" + ] }, "paddusb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xdc" + "Comment": "0x66 0x0f 0xdc", + "ExpectedArm64ASM": [ + "uqadd v16.16b, v16.16b, v17.16b" + ] }, "paddusw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xdd" + "Comment": "0x66 0x0f 0xdd", + "ExpectedArm64ASM": [ + "uqadd v16.8h, v16.8h, v17.8h" + ] }, "pmaxub xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xde" + "Comment": "0x66 0x0f 0xde", + "ExpectedArm64ASM": [ + "umax v16.16b, v16.16b, v17.16b" + ] }, "pandn xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xdf" + "Comment": "0x66 0x0f 0xdf", + "ExpectedArm64ASM": [ + "bic v16.16b, v17.16b, v16.16b" + ] }, "pavgb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe0" + "Comment": "0x66 0x0f 0xe0", + "ExpectedArm64ASM": [ + "urhadd v16.16b, v16.16b, v17.16b" + ] }, "psraw xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0xe1" + "Comment": "0x66 0x0f 0xe1", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x10", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "neg v0.8h, v0.8h", + "sshl v16.8h, v16.8h, v0.8h" + ] }, "psrad xmm0, xmm1": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0x66 0x0f 0xe2" + "Comment": "0x66 0x0f 0xe2", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x20", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "neg v0.4s, v0.4s", + "sshl v16.4s, v16.4s, v0.4s" + ] }, "pavgw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe3" + "Comment": "0x66 0x0f 0xe3", + "ExpectedArm64ASM": [ + "urhadd v16.8h, v16.8h, v17.8h" + ] }, "pmulhuw xmm0, xmm1": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x66 0x0f 0xe4" + "Comment": "0x66 0x0f 0xe4", + "ExpectedArm64ASM": [ + "umull v4.4s, v16.4h, v17.4h", + "umull2 v5.4s, v16.8h, v17.8h", + "shrn v4.4h, v4.4s, #16", + "mov v0.16b, v4.16b", + "shrn2 v0.8h, v5.4s, #16", + "mov v16.16b, v0.16b" + ] }, "pmulhw xmm0, xmm1": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x66 0x0f 0xe5" + "Comment": "0x66 0x0f 0xe5", + "ExpectedArm64ASM": [ + "smull v4.4s, v16.4h, v17.4h", + "smull2 v5.4s, v16.8h, v17.8h", + "shrn v4.4h, v4.4s, #16", + "mov v0.16b, v4.16b", + "shrn2 v0.8h, v5.4s, #16", + "mov v16.16b, v0.16b" + ] }, "cvttpd2dq xmm0, xmm1": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe6" + "Comment": "0x66 0x0f 0xe6", + "ExpectedArm64ASM": [ + "fcvtn v4.2s, v17.2d", + "fcvtzs v16.4s, v4.4s" + ] }, "movntdq [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe7" + "Comment": "0x66 0x0f 0xe7", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "psubsb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe8" + "Comment": "0x66 0x0f 0xe8", + "ExpectedArm64ASM": [ + "sqsub v16.16b, v16.16b, v17.16b" + ] }, "psubsw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xe9" + "Comment": "0x66 0x0f 0xe9", + "ExpectedArm64ASM": [ + "sqsub v16.8h, v16.8h, v17.8h" + ] }, "pminsw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xea" + "Comment": "0x66 0x0f 0xea", + "ExpectedArm64ASM": [ + "smin v16.8h, v16.8h, v17.8h" + ] }, "por xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xeb" + "Comment": "0x66 0x0f 0xeb", + "ExpectedArm64ASM": [ + "orr v16.16b, v16.16b, v17.16b" + ] }, "paddsb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xec" + "Comment": "0x66 0x0f 0xec", + "ExpectedArm64ASM": [ + "sqadd v16.16b, v16.16b, v17.16b" + ] }, "paddsw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xed" + "Comment": "0x66 0x0f 0xed", + "ExpectedArm64ASM": [ + "sqadd v16.8h, v16.8h, v17.8h" + ] }, "pmaxsw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xee" + "Comment": "0x66 0x0f 0xee", + "ExpectedArm64ASM": [ + "smax v16.8h, v16.8h, v17.8h" + ] }, "pxor xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xef" + "Comment": "0x66 0x0f 0xef", + "ExpectedArm64ASM": [ + "eor v16.16b, v16.16b, v17.16b" + ] }, "psllw xmm0, xmm1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0xf1" + "Comment": "0x66 0x0f 0xf1", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x10", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.8h, v4.h[0]", + "ushl v16.8h, v16.8h, v0.8h" + ] }, "pslld xmm0, xmm1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0xf2" + "Comment": "0x66 0x0f 0xf2", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x20", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.4s, v4.s[0]", + "ushl v16.4s, v16.4s, v0.4s" + ] }, "psllq xmm0, xmm1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0x66 0x0f 0xf3" + "Comment": "0x66 0x0f 0xf3", + "ExpectedArm64ASM": [ + "orr w0, wzr, #0x40", + "dup v4.2d, x0", + "cmhi v0.2d, v17.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v17.16b, v0.16b", + "mov v4.16b, v1.16b", + "dup v0.2d, v4.d[0]", + "ushl v16.2d, v16.2d, v0.2d" + ] }, "pmuludq xmm0, xmm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x66 0x0f 0xf4" + "Comment": "0x66 0x0f 0xf4", + "ExpectedArm64ASM": [ + "mov v0.16b, v16.16b", + "mov v0.s[1], v16.s[2]", + "mov v4.16b, v0.16b", + "mov v0.16b, v17.16b", + "mov v0.s[1], v17.s[2]", + "mov v5.16b, v0.16b", + "umull v16.2d, v4.2s, v5.2s" + ] }, "pmaddwd xmm0, xmm1": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0x66 0x0f 0xf5" + "Comment": "0x66 0x0f 0xf5", + "ExpectedArm64ASM": [ + "sxtl v4.4s, v16.4h", + "sxtl2 v5.4s, v16.8h", + "sxtl v6.4s, v17.4h", + "sxtl2 v7.4s, v17.8h", + "mul v4.4s, v4.4s, v6.4s", + "mul v5.4s, v5.4s, v7.4s", + "addp v16.4s, v4.4s, v5.4s" + ] }, "psadbw xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0x66 0x0f 0xf6" + "Comment": "0x66 0x0f 0xf6", + "ExpectedArm64ASM": [ + "uabdl v4.8h, v16.8b, v17.8b", + "uabdl2 v5.8h, v16.16b, v17.16b", + "addv h4, v4.8h", + "addv h5, v5.8h", + "zip1 v16.2d, v4.2d, v5.2d" + ] }, "maskmovdqu xmm0, xmm1": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0x66 0x0f 0xf7" + "Comment": "0x66 0x0f 0xf7", + "ExpectedArm64ASM": [ + "cmlt v4.16b, v17.16b, #0", + "ldr q5, [x11]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v16.16b, v5.16b", + "mov v4.16b, v0.16b", + "str q4, [x11]" + ] }, "psubb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xf8" + "Comment": "0x66 0x0f 0xf8", + "ExpectedArm64ASM": [ + "sub v16.16b, v16.16b, v17.16b" + ] }, "psubw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xf9" + "Comment": "0x66 0x0f 0xf9", + "ExpectedArm64ASM": [ + "sub v16.8h, v16.8h, v17.8h" + ] }, "psubd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xfa" + "Comment": "0x66 0x0f 0xfa", + "ExpectedArm64ASM": [ + "sub v16.4s, v16.4s, v17.4s" + ] }, "psubq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xfb" + "Comment": "0x66 0x0f 0xfb", + "ExpectedArm64ASM": [ + "sub v16.2d, v16.2d, v17.2d" + ] }, "paddb xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xfc" + "Comment": "0x66 0x0f 0xfc", + "ExpectedArm64ASM": [ + "add v16.16b, v16.16b, v17.16b" + ] }, "paddw xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xfd" + "Comment": "0x66 0x0f 0xfd", + "ExpectedArm64ASM": [ + "add v16.8h, v16.8h, v17.8h" + ] }, "paddd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "No", - "Comment": "0x66 0x0f 0xfe" + "Comment": "0x66 0x0f 0xfe", + "ExpectedArm64ASM": [ + "add v16.4s, v16.4s, v17.4s" + ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 7209ea81d..1f06df6f0 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -11,37 +11,80 @@ "movss xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x10" + "Comment": "0xf3 0x0f 0x10", + "ExpectedArm64ASM": [ + "mov v16.s[0], v17.s[0]" + ] }, "movss xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x10" + "Comment": "0xf3 0x0f 0x10", + "ExpectedArm64ASM": [ + "ldr s16, [x4]" + ] }, "movss [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x11" + "Comment": "0xf3 0x0f 0x11", + "ExpectedArm64ASM": [ + "str s16, [x4]" + ] }, "movsldup xmm0, xmm1": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0xf3 0x0f 0x12" + "Comment": "0xf3 0x0f 0x12", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.s[3], v17.s[2]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[1], v17.s[0]", + "mov v16.16b, v0.16b" + ] }, "movsldup xmm0, [rax]": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xf3 0x0f 0x12" + "Comment": "0xf3 0x0f 0x12", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v4.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[1], v4.s[0]", + "mov v16.16b, v0.16b" + ] }, "movshdup xmm0, xmm1": { "ExpectedInstructionCount": 6, "Optimal": "No", - "Comment": "0xf3 0x0f 0x16" + "Comment": "0xf3 0x0f 0x16", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.s[2], v17.s[3]", + "mov v4.16b, v0.16b", + "mov v0.16b, v4.16b", + "mov v0.s[0], v17.s[1]", + "mov v16.16b, v0.16b" + ] }, "movshdup xmm0, [rax]": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xf3 0x0f 0x16" + "Comment": "0xf3 0x0f 0x16", + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[2], v4.s[3]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[1]", + "mov v16.16b, v0.16b" + ] }, "cvtsi2ss xmm0, eax": { "ExpectedInstructionCount": 3, @@ -49,6 +92,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "scvtf s4, w20", + "mov v16.s[0], v4.s[0]" ] }, "cvtsi2ss xmm0, dword [rax]": { @@ -57,12 +105,21 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf s4, w20", + "mov v16.s[0], v4.s[0]" ] }, "cvtsi2ss xmm0, rax": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x2a" + "Comment": "0xf3 0x0f 0x2a", + "ExpectedArm64ASM": [ + "scvtf s4, x4", + "mov v16.s[0], v4.s[0]" + ] }, "cvtsi2ss xmm0, qword [rax]": { "ExpectedInstructionCount": 3, @@ -70,57 +127,115 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x4]", + "scvtf s4, x20", + "mov v16.s[0], v4.s[0]" ] }, "movntss [rax], xmm0": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0xf3 0x0f 0x2b" + "Comment": "0xf3 0x0f 0x2b", + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v16.s[0]", + "mov v4.16b, v0.16b", + "str s4, [x4]" + ] }, "cvttss2si eax, xmm0": { "ExpectedInstructionCount": 4, "Optimal": "No", - "Comment": "0xf3 0x0f 0x2c" + "Comment": "0xf3 0x0f 0x2c", + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v16.s[0]", + "mov v4.16b, v0.16b", + "fcvtzs w4, s4" + ] }, "cvttss2si eax, dword [rbx]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x2c" + "Comment": "0xf3 0x0f 0x2c", + "ExpectedArm64ASM": [ + "ldr s4, [x7]", + "fcvtzs w4, s4" + ] }, "cvttss2si rax, xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf3 0x0f 0x2c" + "Comment": "0xf3 0x0f 0x2c", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "fcvtzs x4, s4" + ] }, "cvttss2si rax, dword [rbx]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x2c" + "Comment": "0xf3 0x0f 0x2c", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "fcvtzs x4, s4" + ] }, "cvtss2si eax, xmm0": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0xf3 0x0f 0x2d" + "Comment": "0xf3 0x0f 0x2d", + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v16.s[0]", + "mov v4.16b, v0.16b", + "frinti s0, s4", + "fcvtzs w4, s0" + ] }, "cvtss2si eax, dword [rbx]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x2d" + "Comment": "0xf3 0x0f 0x2d", + "ExpectedArm64ASM": [ + "ldr s4, [x7]", + "frinti s0, s4", + "fcvtzs w4, s0" + ] }, "cvtss2si rax, xmm0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0xf3 0x0f 0x2d" + "Comment": "0xf3 0x0f 0x2d", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "frinti s0, s4", + "fcvtzs x4, s0" + ] }, "cvtss2si rax, dword [rbx]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x2d" + "Comment": "0xf3 0x0f 0x2d", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "frinti s0, s4", + "fcvtzs x4, s0" + ] }, "sqrtss xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0xf3 0x0f 0x51" + "Comment": "0xf3 0x0f 0x51", + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fsqrt s4, s4", + "mov v16.s[0], v4.s[0]" + ] }, "rsqrtss xmm0, xmm1": { "ExpectedInstructionCount": 7, @@ -128,6 +243,15 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0xf3 0x0f 0x52" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s4", + "fdiv s4, s0, s1", + "mov v16.s[0], v4.s[0]" ] }, "rcpss xmm0, xmm1": { @@ -136,6 +260,14 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "0xf3 0x0f 0x53" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fmov s0, #0x70 (1.0000)", + "fdiv s4, s0, s4", + "mov v16.s[0], v4.s[0]" ] }, "addss xmm0, xmm1": { @@ -144,6 +276,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd s4, s16, s17", + "mov v16.s[0], v4.s[0]" ] }, "mulss xmm0, xmm1": { @@ -152,22 +288,41 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul s4, s16, s17", + "mov v16.s[0], v4.s[0]" ] }, "cvtss2sd xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "No", - "Comment": "0xf3 0x0f 0x5a" + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcvt d4, s4", + "mov v16.d[0], v4.d[0]" + ] }, "cvtss2sd xmm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x5a" + "Comment": "0xf3 0x0f 0x5a", + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "fcvt d4, s4", + "mov v16.d[0], v4.d[0]" + ] }, "cvttps2dq xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x5b" + "Comment": "0xf3 0x0f 0x5b", + "ExpectedArm64ASM": [ + "fcvtzs v16.4s, v17.4s" + ] }, "subss xmm0, xmm1": { "ExpectedInstructionCount": 2, @@ -175,6 +330,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub s4, s16, s17", + "mov v16.s[0], v4.s[0]" ] }, "minss xmm0, xmm1": { @@ -183,6 +342,14 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmp s16, s4", + "fcsel s4, s16, s4, mi", + "mov v16.s[0], v4.s[0]" ] }, "divss xmm0, xmm1": { @@ -191,6 +358,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv s4, s16, s17", + "mov v16.s[0], v4.s[0]" ] }, "maxss xmm0, xmm1": { @@ -199,92 +370,254 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmp s16, s4", + "fcsel s4, s4, s16, mi", + "mov v16.s[0], v4.s[0]" ] }, "movdqu xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x6f" + "Comment": "0xf3 0x0f 0x6f", + "ExpectedArm64ASM": [ + "mov v16.16b, v17.16b" + ] }, "movdqu xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x6f" + "Comment": "0xf3 0x0f 0x6f", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] }, "pshufhw xmm0, xmm1, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf3 0x0f 0x70" + "Comment": "0xf3 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[4], v17.h[4]", + "mov v4.16b, v0.16b", + "mov v4.h[5], v17.h[4]", + "mov v4.h[6], v17.h[4]", + "mov v0.16b, v4.16b", + "mov v0.h[7], v17.h[4]", + "mov v16.16b, v0.16b" + ] }, "pshufhw xmm0, xmm1, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf3 0x0f 0x70" + "Comment": "0xf3 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[4], v17.h[5]", + "mov v4.16b, v0.16b", + "mov v4.h[5], v17.h[4]", + "mov v4.h[6], v17.h[4]", + "mov v0.16b, v4.16b", + "mov v0.h[7], v17.h[4]", + "mov v16.16b, v0.16b" + ] }, "pshufhw xmm0, xmm1, 0xff": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf3 0x0f 0x70" + "Comment": "0xf3 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[4], v17.h[7]", + "mov v4.16b, v0.16b", + "mov v4.h[5], v17.h[7]", + "mov v4.h[6], v17.h[7]", + "mov v0.16b, v4.16b", + "mov v0.h[7], v17.h[7]", + "mov v16.16b, v0.16b" + ] }, "movq xmm0, xmm1": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf3 0x0f 0x7e" + "Comment": "0xf3 0x0f 0x7e", + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "mov v16.16b, v4.16b" + ] }, "movq xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x7e" + "Comment": "0xf3 0x0f 0x7e", + "ExpectedArm64ASM": [ + "ldr d16, [x4]" + ] }, "movdqu [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0x7f" + "Comment": "0xf3 0x0f 0x7f", + "ExpectedArm64ASM": [ + "str q16, [x4]" + ] }, "popcnt ax, bx": { "ExpectedInstructionCount": 13, "Optimal": "No", - "Comment": "0xf3 0x0f 0xb8" + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "fmov s0, w20", + "cnt v0.8b, v0.8b", + "addp v0.8b, v0.8b, v0.8b", + "umov w20, v0.b[0]", + "bfxil x4, x20, #0, #16", + "mov w21, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "strb w21, [x28, #706]", + "strb w21, [x28, #708]", + "str w20, [x28, #728]" + ] }, "popcnt eax, ebx": { "ExpectedInstructionCount": 12, "Optimal": "No", - "Comment": "0xf3 0x0f 0xb8" + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "fmov s0, w20", + "cnt v0.8b, v0.8b", + "addv b0, v0.8b", + "umov w4, v0.b[0]", + "mov w20, #0x0", + "cmp x4, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #30", + "strb w20, [x28, #706]", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "popcnt rax, rbx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0xf3 0x0f 0xb8" + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "fmov d0, x7", + "cnt v0.8b, v0.8b", + "addv b0, v0.8b", + "umov w4, v0.b[0]", + "mov w20, #0x0", + "cmp x4, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #30", + "strb w20, [x28, #706]", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] }, "tzcnt ax, bx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0xf3 0x0f 0xbc" + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "rbit w20, w20", + "orr w20, w20, #0x8000", + "clz w20, w20", + "bfxil x4, x20, #0, #16", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "ubfx x20, x20, #0, #1", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "tzcnt eax, ebx": { "ExpectedInstructionCount": 9, "Optimal": "No", - "Comment": "0xf3 0x0f 0xbc" + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "rbit w4, w20", + "clz w4, w4", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "ubfx x21, x4, #0, #1", + "orr x20, x20, x21, lsl #30", + "str w20, [x28, #728]" + ] }, "tzcnt rax, rbx": { "ExpectedInstructionCount": 8, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0xbc" + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "rbit x4, x7", + "clz x4, x4", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "ubfx x21, x4, #0, #1", + "orr x20, x20, x21, lsl #30", + "str w20, [x28, #728]" + ] }, "lzcnt ax, bx": { "ExpectedInstructionCount": 11, "Optimal": "No", - "Comment": "0xf3 0x0f 0xbd" + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "uxth x20, w7", + "lsl w21, w20, #16", + "orr w21, w21, #0x8000", + "clz w21, w21", + "bfxil x4, x21, #0, #16", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "ubfx x20, x20, #15, #1", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "lzcnt eax, ebx": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf3 0x0f 0xbd" + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "clz w4, w20", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "ubfx x20, x20, #31, #1", + "orr x20, x21, x20, lsl #30", + "str w20, [x28, #728]" + ] }, "lzcnt rax, rbx": { "ExpectedInstructionCount": 7, "Optimal": "No", - "Comment": "0xf3 0x0f 0xbd" + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "clz x4, x7", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "lsr x21, x7, #63", + "orr x20, x20, x21, lsl #30", + "str w20, [x28, #728]" + ] }, "cmpss xmm0, xmm1, 0": { "ExpectedInstructionCount": 5, @@ -292,6 +625,13 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmeq s4, s16, s4", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 1": { @@ -300,6 +640,13 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmgt s4, s4, s16", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 2": { @@ -308,6 +655,13 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmge s4, s4, s16", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 3": { @@ -316,6 +670,16 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmge s0, s16, s4", + "fcmgt s1, s4, s16", + "orr v4.8b, v0.8b, v1.8b", + "mvn v4.8b, v4.8b", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 4": { @@ -324,6 +688,14 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmeq s4, s16, s4", + "mvn v4.8b, v4.8b", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 5": { @@ -332,6 +704,14 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmgt s4, s4, s16", + "mvn v4.16b, v4.16b", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 6": { @@ -340,6 +720,14 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmge s4, s4, s16", + "mvn v4.16b, v4.16b", + "mov v16.s[0], v4.s[0]" ] }, "cmpss xmm0, xmm1, 7": { @@ -348,22 +736,44 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf3 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "movi v0.2d, #0x0", + "mov v0.s[0], v17.s[0]", + "mov v4.16b, v0.16b", + "fcmge s0, s16, s4", + "fcmgt s1, s4, s16", + "orr v4.8b, v0.8b, v1.8b", + "mov v16.s[0], v4.s[0]" ] }, "movq2dq xmm0, mm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0xd6" + "Comment": "0xf3 0x0f 0xd6", + "ExpectedArm64ASM": [ + "ldr d16, [x28, #752]" + ] }, "cvtdq2pd xmm0, xmm1": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0xf3 0x0f 0xe6" + "Comment": "0xf3 0x0f 0xe6", + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "sxtl v4.2d, v4.2s", + "scvtf v16.2d, v4.2d" + ] }, "cvtdq2pd xmm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf3 0x0f 0xe6" + "Comment": "0xf3 0x0f 0xe6", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "sxtl v4.2d, v4.2s", + "scvtf v16.2d, v4.2d" + ] } } } \ No newline at end of file diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 6e522e204..59b5df3db 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -11,27 +11,44 @@ "movsd xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x10" + "Comment": "0xf2 0x0f 0x10", + "ExpectedArm64ASM": [ + "mov v16.d[0], v17.d[0]" + ] }, "movsd xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x10" + "Comment": "0xf2 0x0f 0x10", + "ExpectedArm64ASM": [ + "ldr d16, [x4]" + ] }, "movsd [rax], xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x11" + "Comment": "0xf2 0x0f 0x11", + "ExpectedArm64ASM": [ + "str d16, [x4]" + ] }, "movddup xmm0, xmm1": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf2 0x0f 0x12" + "Comment": "0xf2 0x0f 0x12", + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "dup v16.2d, v4.d[0]" + ] }, "movddup xmm0, [rax]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x12" + "Comment": "0xf2 0x0f 0x12", + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "dup v16.2d, v4.d[0]" + ] }, "cvtsi2sd xmm0, eax": { "ExpectedInstructionCount": 3, @@ -39,6 +56,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "scvtf d4, w20", + "mov v16.d[0], v4.d[0]" ] }, "cvtsi2sd xmm0, dword [rax]": { @@ -47,6 +69,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "scvtf d4, w20", + "mov v16.d[0], v4.d[0]" ] }, "cvtsi2sd xmm0, rax": { @@ -55,6 +82,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "scvtf d4, x4", + "mov v16.d[0], v4.d[0]" ] }, "cvtsi2sd xmm0, qword [rax]": { @@ -63,52 +94,97 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x2a" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x4]", + "scvtf d4, x20", + "mov v16.d[0], v4.d[0]" ] }, "movntsd [rax], xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2b" + "Comment": "0xf2 0x0f 0x2b", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "str d4, [x4]" + ] }, "cvttsd2si eax, xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2c" + "Comment": "0xf2 0x0f 0x2c", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "fcvtzs w4, d4" + ] }, "cvttsd2si eax, qword [rbx]": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2c" + "Comment": "0xf2 0x0f 0x2c", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "fcvtzs w4, d4" + ] }, "cvttsd2si rax, xmm0": { "ExpectedInstructionCount": 2, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2c" + "Comment": "0xf2 0x0f 0x2c", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "fcvtzs x4, d4" + ] }, "cvttsd2si rax, qword [rbx]": { "ExpectedInstructionCount": 2, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x2c" + "Comment": "0xf2 0x0f 0x2c", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "fcvtzs x4, d4" + ] }, "cvtsd2si eax, xmm0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2d" + "Comment": "0xf2 0x0f 0x2d", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "frinti d0, d4", + "fcvtzs x4, d0" + ] }, "cvtsd2si eax, qword [rbx]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x2d" + "Comment": "0xf2 0x0f 0x2d", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "frinti d0, d4", + "fcvtzs x4, d0" + ] }, "cvtsd2si rax, xmm0": { "ExpectedInstructionCount": 3, "Optimal": "No", - "Comment": "0xf2 0x0f 0x2d" + "Comment": "0xf2 0x0f 0x2d", + "ExpectedArm64ASM": [ + "mov v4.8b, v16.8b", + "frinti d0, d4", + "fcvtzs x4, d0" + ] }, "cvtsd2si rax, qword [rbx]": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x2d" + "Comment": "0xf2 0x0f 0x2d", + "ExpectedArm64ASM": [ + "ldr d4, [x7]", + "frinti d0, d4", + "fcvtzs x4, d0" + ] }, "sqrtsd xmm0, xmm1": { "ExpectedInstructionCount": 3, @@ -116,6 +192,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x51" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fsqrt d4, d4", + "mov v16.d[0], v4.d[0]" ] }, "addsd xmm0, xmm1": { @@ -124,6 +205,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x58" + ], + "ExpectedArm64ASM": [ + "fadd d4, d16, d17", + "mov v16.d[0], v4.d[0]" ] }, "mulsd xmm0, xmm1": { @@ -132,6 +217,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x59" + ], + "ExpectedArm64ASM": [ + "fmul d4, d16, d17", + "mov v16.d[0], v4.d[0]" ] }, "cvtsd2ss xmm0, xmm1": { @@ -140,6 +229,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcvt s4, d4", + "mov v16.s[0], v4.s[0]" ] }, "cvtsd2ss xmm0, [rax]": { @@ -148,6 +242,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5a" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "fcvt s4, d4", + "mov v16.s[0], v4.s[0]" ] }, "subsd xmm0, xmm1": { @@ -156,6 +255,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5c" + ], + "ExpectedArm64ASM": [ + "fsub d4, d16, d17", + "mov v16.d[0], v4.d[0]" ] }, "minsd xmm0, xmm1": { @@ -164,6 +267,12 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5d" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmp d16, d4", + "fcsel d4, d16, d4, mi", + "mov v16.d[0], v4.d[0]" ] }, "divsd xmm0, xmm1": { @@ -172,6 +281,10 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5e" + ], + "ExpectedArm64ASM": [ + "fdiv d4, d16, d17", + "mov v16.d[0], v4.d[0]" ] }, "maxsd xmm0, xmm1": { @@ -180,22 +293,58 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0x5f" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmp d16, d4", + "fcsel d4, d4, d16, mi", + "mov v16.d[0], v4.d[0]" ] }, "pshuflw xmm0, xmm1, 0": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf2 0x0f 0x70" + "Comment": "0xf2 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[0], v17.h[0]", + "mov v4.16b, v0.16b", + "mov v4.h[1], v17.h[0]", + "mov v4.h[2], v17.h[0]", + "mov v0.16b, v4.16b", + "mov v0.h[3], v17.h[0]", + "mov v16.16b, v0.16b" + ] }, "pshuflw xmm0, xmm1, 1": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf2 0x0f 0x70" + "Comment": "0xf2 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[0], v17.h[1]", + "mov v4.16b, v0.16b", + "mov v4.h[1], v17.h[0]", + "mov v4.h[2], v17.h[0]", + "mov v0.16b, v4.16b", + "mov v0.h[3], v17.h[0]", + "mov v16.16b, v0.16b" + ] }, "pshuflw xmm0, xmm1, 0xff": { "ExpectedInstructionCount": 8, "Optimal": "No", - "Comment": "0xf2 0x0f 0x70" + "Comment": "0xf2 0x0f 0x70", + "ExpectedArm64ASM": [ + "mov v0.16b, v17.16b", + "mov v0.h[0], v17.h[3]", + "mov v4.16b, v0.16b", + "mov v4.h[1], v17.h[3]", + "mov v4.h[2], v17.h[3]", + "mov v0.16b, v4.16b", + "mov v0.h[3], v17.h[3]", + "mov v16.16b, v0.16b" + ] }, "insertq xmm0, xmm1, 0, 0": { "ExpectedInstructionCount": 7, @@ -236,12 +385,32 @@ "haddps xmm0, xmm1": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0x7c" + "Comment": "0xf2 0x0f 0x7c", + "ExpectedArm64ASM": [ + "faddp v16.4s, v16.4s, v17.4s" + ] }, "hsubps xmm0, xmm1": { "ExpectedInstructionCount": 15, "Optimal": "No", - "Comment": "0xf2 0x0f 0x7d" + "Comment": "0xf2 0x0f 0x7d", + "ExpectedArm64ASM": [ + "fneg v4.4s, v16.4s", + "fneg v5.4s, v17.4s", + "mov v0.16b, v16.16b", + "mov v0.s[1], v4.s[1]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v0.16b, v17.16b", + "mov v0.s[1], v5.s[1]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[3], v5.s[3]", + "mov v5.16b, v0.16b", + "faddp v16.4s, v4.4s, v5.4s" + ] }, "cmpsd xmm0, xmm1, 0": { "ExpectedInstructionCount": 3, @@ -249,6 +418,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmeq d4, d16, d4", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 1": { @@ -257,6 +431,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmgt d4, d4, d16", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 2": { @@ -265,6 +444,11 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmge d4, d4, d16", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 3": { @@ -273,6 +457,14 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmge d0, d16, d4", + "fcmgt d1, d4, d16", + "orr v4.8b, v0.8b, v1.8b", + "mvn v4.8b, v4.8b", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 4": { @@ -281,6 +473,12 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmeq d4, d16, d4", + "mvn v4.8b, v4.8b", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 5": { @@ -289,6 +487,12 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmgt d4, d4, d16", + "mvn v4.16b, v4.16b", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 6": { @@ -297,6 +501,12 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmge d4, d4, d16", + "mvn v4.16b, v4.16b", + "mov v16.d[0], v4.d[0]" ] }, "cmpsd xmm0, xmm1, 7": { @@ -305,27 +515,52 @@ "Comment": [ "With AFP mode FEX can remove an insert after the operation.", "0xf2 0x0f 0xc2" + ], + "ExpectedArm64ASM": [ + "mov v4.8b, v17.8b", + "fcmge d0, d16, d4", + "fcmgt d1, d4, d16", + "orr v4.8b, v0.8b, v1.8b", + "mov v16.d[0], v4.d[0]" ] }, "addsubps xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0xd0" + "Comment": "0xf2 0x0f 0xd0", + "ExpectedArm64ASM": [ + "fadd v4.4s, v16.4s, v17.4s", + "fsub v5.4s, v16.4s, v17.4s", + "uzp1 v5.4s, v5.4s, v5.4s", + "uzp2 v4.4s, v4.4s, v4.4s", + "zip1 v16.4s, v5.4s, v4.4s" + ] }, "movdq2q mm0, xmm0": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0xd6" + "Comment": "0xf2 0x0f 0xd6", + "ExpectedArm64ASM": [ + "str d16, [x28, #752]" + ] }, "cvtpd2dq xmm0, xmm1": { "ExpectedInstructionCount": 3, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0xe6" + "Comment": "0xf2 0x0f 0xe6", + "ExpectedArm64ASM": [ + "fcvtn v4.2s, v17.2d", + "frinti v16.4s, v4.4s", + "fcvtzs v16.4s, v16.4s" + ] }, "lddqu xmm0, [rax]": { "ExpectedInstructionCount": 1, "Optimal": "Yes", - "Comment": "0xf2 0x0f 0xf0" + "Comment": "0xf2 0x0f 0xf0", + "ExpectedArm64ASM": [ + "ldr q16, [x4]" + ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index a97bae3c1..8768bb33c 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -14,6 +14,10 @@ "SVE 128-bit load already zero's the upper bits", "Spurious move afterwards", "Map 1 0b00 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovups ymm0, [rax]": { @@ -22,6 +26,10 @@ "Comment": [ "Doesn't load directly in to destination", "Map 1 0b00 0x10 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovupd xmm0, [rax]": { @@ -31,6 +39,10 @@ "SVE 128-bit load already zero's the upper bits", "Spurious move afterwards", "Map 1 0b01 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovupd ymm0, [rax]": { @@ -39,6 +51,10 @@ "Comment": [ "Doesn't load directly in to destination", "Map 1 0b01 0x10 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovss xmm0, [rax]": { @@ -48,6 +64,10 @@ "32-bit vector load already zero's the upper bits", "Spurious move afterwards", "Map 1 0b10 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovss xmm0, xmm1, xmm2": { @@ -56,6 +76,16 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b10 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovsd xmm0, [rax]": { @@ -65,6 +95,10 @@ "32-bit vector load already zero's the upper bits", "Spurious move afterwards", "Map 1 0b11 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovsd xmm0, xmm1, xmm2": { @@ -73,6 +107,14 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b11 0x10 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovups [rax], xmm0": { @@ -80,6 +122,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovups [rax], ymm0": { @@ -87,6 +133,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x11 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vmovupd [rax], xmm0": { @@ -94,6 +144,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovupd [rax], ymm0": { @@ -101,6 +155,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x11 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vmovss [rax], xmm0": { @@ -108,6 +166,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "str s4, [x4]" ] }, "db 0xc5, 0xf2, 0x11, 0xc2": { @@ -118,6 +183,16 @@ "Need to manually encode since nasm won't encode this", "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b10 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z16.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z18.d, p7/m, z4.d" ] }, "vmovsd [rax], xmm0": { @@ -125,6 +200,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "str d4, [x4]" ] }, "db 0xc5, 0xf3, 0x11, 0xc2": { @@ -135,6 +215,14 @@ "Need to manually encode since nasm won't encode this", "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b11 0x11 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z16.d", + "mov v5.8b, v5.8b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z18.d, p7/m, z4.d" ] }, "vmovlps xmm0, xmm1, [rax]": { @@ -143,6 +231,14 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b00 0x12 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovlpd xmm0, xmm1, [rax]": { @@ -151,6 +247,14 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b01 0x12 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovsldup xmm0, [rax]": { @@ -158,6 +262,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x12 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[3], v4.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[1], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovsldup ymm0, [rax]": { @@ -165,6 +281,38 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x12 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vmovddup xmm0, [rax]": { @@ -172,6 +320,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x12 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov v4.d[1], v4.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovddup ymm0, [rax]": { @@ -179,6 +334,24 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x12 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmovlps [rax], xmm0": { @@ -186,6 +359,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x13 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str d4, [x4]" ] }, "vmovlpd [rax], xmm0": { @@ -193,6 +370,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x13 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str d4, [x4]" ] }, "vunpcklps xmm0, xmm1, [rax]": { @@ -200,6 +381,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x14 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "zip1 v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vunpcklps ymm0, ymm1, [rax]": { @@ -207,6 +395,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x14 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ld1b {z5.b}, p7/z, [x4]", + "zip1 z6.s, z4.s, z5.s", + "zip2 z4.s, z4.s, z5.s", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vunpcklpd xmm0, xmm1, [rax]": { @@ -214,6 +416,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x14 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "zip1 v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vunpcklpd ymm0, ymm1, [rax]": { @@ -221,6 +430,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x14 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ld1b {z5.b}, p7/z, [x4]", + "zip1 z6.d, z4.d, z5.d", + "zip2 z4.d, z4.d, z5.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vunpckhps xmm0, xmm1, [rax]": { @@ -228,6 +451,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x15 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "zip2 v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vunpckhps ymm0, ymm1, [rax]": { @@ -235,6 +465,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x15 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ld1b {z5.b}, p7/z, [x4]", + "zip1 z6.s, z4.s, z5.s", + "zip2 z4.s, z4.s, z5.s", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vunpckhpd xmm0, xmm1, [rax]": { @@ -242,6 +486,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x15 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ldr q5, [x4]", + "zip2 v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vunpckhpd ymm0, ymm1, [rax]": { @@ -249,6 +500,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x15 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ld1b {z5.b}, p7/z, [x4]", + "zip1 z6.d, z4.d, z5.d", + "zip2 z4.d, z4.d, z5.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vmovhps xmm0, xmm1, [rax]": { @@ -256,6 +521,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "ldr d5, [x4]", + "mov v4.d[1], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovhpd xmm0, xmm1, [rax]": { @@ -263,6 +537,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "ldr d5, [x4]", + "mov v4.d[1], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovshdup xmm0, [rax]": { @@ -270,6 +553,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov v0.16b, v4.16b", + "mov v0.s[2], v4.s[3]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[1]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovshdup ymm0, [rax]": { @@ -277,6 +572,38 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x16 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmovhps [rax], xmm0": { @@ -284,6 +611,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x17 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.d[0], v4.d[1]", + "str d4, [x4]" ] }, "vmovhpd [rax], xmm0": { @@ -291,6 +623,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x17 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.d[0], v4.d[1]", + "str d4, [x4]" ] }, "vmovmskps rax, xmm0": { @@ -298,6 +635,26 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x50 128-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov z4.d, p7/m, z16.d", + "mov w21, v4.s[0]", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21", + "mov w21, v4.s[1]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #1", + "orr x20, x20, x21", + "mov w21, v4.s[2]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #2", + "orr x20, x20, x21", + "mov w21, v4.s[3]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #3", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" ] }, "vmovmskps rax, ymm0": { @@ -305,6 +662,50 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x50 256-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov z4.d, p7/m, z16.d", + "mov w21, v4.s[0]", + "ubfx x21, x21, #31, #1", + "orr x20, x20, x21", + "mov w21, v4.s[1]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #1", + "orr x20, x20, x21", + "mov w21, v4.s[2]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #2", + "orr x20, x20, x21", + "mov w21, v4.s[3]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #3", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov w21, v4.s[0]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #4", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov w21, v4.s[1]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #5", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov w21, v4.s[2]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #6", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov w21, v4.s[3]", + "ubfx x21, x21, #31, #1", + "lsl w21, w21, #7", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" ] }, "vmovmskpd rax, xmm0": { @@ -312,6 +713,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x50 128-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov z4.d, p7/m, z16.d", + "mov x21, v4.d[0]", + "lsr x21, x21, #63", + "orr x20, x20, x21", + "mov x21, v4.d[1]", + "lsr x21, x21, #63", + "lsl x21, x21, #1", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" ] }, "vmovmskpd rax, ymm0": { @@ -319,6 +732,30 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x50 256-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov z4.d, p7/m, z16.d", + "mov x21, v4.d[0]", + "lsr x21, x21, #63", + "orr x20, x20, x21", + "mov x21, v4.d[1]", + "lsr x21, x21, #63", + "lsl x21, x21, #1", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov x21, v4.d[0]", + "lsr x21, x21, #63", + "lsl x21, x21, #2", + "orr x20, x20, x21", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "mov x21, v4.d[1]", + "lsr x21, x21, #63", + "lsl x21, x21, #3", + "orr x20, x20, x21", + "ubfx x4, x20, #0, #32" ] }, "vsqrtps xmm0, xmm1": { @@ -326,6 +763,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fsqrt v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsqrtps ymm0, ymm1": { @@ -333,6 +776,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x51 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fsqrt z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vsqrtpd xmm0, xmm1": { @@ -340,6 +788,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fsqrt v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsqrtpd ymm0, ymm1": { @@ -347,6 +801,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x51 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fsqrt z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vsqrtss xmm0, xmm1, xmm2": { @@ -355,6 +814,19 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b10 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov z5.d, p7/m, z17.d", + "fsqrt s4, s4", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsqrtsd xmm0, xmm1, xmm2": { @@ -363,6 +835,17 @@ "Comment": [ "Insert in to first element could be more optimal, which is the common case.", "Map 1 0b11 0x51 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov v4.8b, v4.8b", + "mov z5.d, p7/m, z17.d", + "fsqrt d4, d4", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vrsqrtps xmm0, xmm1": { @@ -371,6 +854,14 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b00 0x52 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fmov v0.4s, #0x70 (1.0000)", + "fsqrt v1.4s, v4.4s", + "fdiv v4.4s, v0.4s, v1.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vrsqrtps ymm0, ymm1": { @@ -379,6 +870,13 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b00 0x52 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fsqrt z0.s, p7/m, z4.s", + "fmov z4.s, #0x70 (1.0000)", + "fdiv z4.s, p7/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vrsqrtss xmm0, xmm1, xmm2": { @@ -387,6 +885,21 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b10 0x52 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov z5.d, p7/m, z17.d", + "fmov s0, #0x70 (1.0000)", + "fsqrt s1, s4", + "fdiv s4, s0, s1", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vrcpps xmm0, xmm1": { @@ -395,6 +908,13 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b00 0x53 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fmov v0.4s, #0x70 (1.0000)", + "fdiv v4.4s, v0.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vrcpps ymm0, ymm1": { @@ -403,6 +923,13 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b00 0x53 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fmov z0.s, #0x70 (1.0000)", + "fdiv z0.s, p7/m, z0.s, z4.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vrcpss xmm0, xmm1, xmm2": { @@ -411,6 +938,20 @@ "Comment": [ "FEAT_FPRES could make this more optimal", "Map 1 0b10 0x53 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov z5.d, p7/m, z17.d", + "fmov s0, #0x70 (1.0000)", + "fdiv s4, s0, s4", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vandps xmm0, xmm1": { @@ -418,6 +959,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x54 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vandps ymm0, ymm1": { @@ -425,6 +974,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x54 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vandpd xmm0, xmm1": { @@ -432,6 +987,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x54 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vandpd ymm0, ymm1": { @@ -439,6 +1002,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x54 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vandnps xmm0, xmm1": { @@ -446,6 +1015,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x55 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "bic v4.16b, v5.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vandnps ymm0, ymm1": { @@ -453,6 +1030,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x55 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "bic z4.d, z5.d, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vandnpd xmm0, xmm1": { @@ -460,6 +1043,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x55 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "bic v4.16b, v5.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vandnpd ymm0, ymm1": { @@ -467,6 +1058,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x55 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "bic z4.d, z5.d, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vorps xmm0, xmm1": { @@ -474,6 +1071,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x56 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vorps ymm0, ymm1": { @@ -481,6 +1086,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x56 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vorpd xmm0, xmm1": { @@ -488,6 +1099,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x56 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vorpd ymm0, ymm1": { @@ -495,6 +1114,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x56 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vxorps xmm0, xmm1": { @@ -502,6 +1127,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x57 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "eor v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vxorps ymm0, ymm1": { @@ -509,6 +1142,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x57 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "eor z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vxorpd xmm0, xmm1": { @@ -516,6 +1155,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x57 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "eor v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vxorpd ymm0, ymm1": { @@ -523,6 +1170,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x57 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "eor z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklbw xmm0, xmm1, xmm2": { @@ -530,6 +1183,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x60 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklbw ymm0, ymm1, ymm2": { @@ -537,6 +1197,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x60 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.b, z4.b, z5.b", + "zip2 z4.b, z4.b, z5.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklwd xmm0, xmm1, xmm2": { @@ -544,6 +1218,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x61 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklwd ymm0, ymm1, ymm2": { @@ -551,6 +1232,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x61 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.h, z4.h, z5.h", + "zip2 z4.h, z4.h, z5.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckldq xmm0, xmm1, xmm2": { @@ -558,6 +1253,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x62 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckldq ymm0, ymm1, ymm2": { @@ -565,6 +1267,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x62 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.s, z4.s, z5.s", + "zip2 z4.s, z4.s, z5.s", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpacksswb xmm0, xmm1, xmm2": { @@ -572,6 +1288,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x63 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtn v4.8b, v4.8h", + "mov v0.16b, v4.16b", + "sqxtn2 v0.16b, v5.8h", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpacksswb ymm0, ymm1, ymm2": { @@ -579,6 +1306,31 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x63 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtnb z4.b, z4.h", + "uzp1 z4.b, z4.b, z4.b", + "sqxtnb z1.b, z5.h", + "uzp1 z1.b, z1.b, z1.b", + "movprfx z4, z4", + "splice z4.b, p6, z4.b, z1.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtb xmm0, xmm1, xmm2": { @@ -586,6 +1338,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x64 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmgt v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtb ymm0, ymm1, ymm2": { @@ -593,6 +1353,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x64 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpgt p0.b, p7/z, z4.b, z5.b", + "not z0.b, p0/m, z4.b", + "movprfx z4.b, p0/z, z4.b", + "orr z4.b, p0/m, z4.b, z0.b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtw xmm0, xmm1, xmm2": { @@ -600,6 +1369,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x65 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmgt v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtw ymm0, ymm1, ymm2": { @@ -607,6 +1384,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x65 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpgt p0.h, p7/z, z4.h, z5.h", + "not z0.h, p0/m, z4.h", + "movprfx z4.h, p0/z, z4.h", + "orr z4.h, p0/m, z4.h, z0.h", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtd xmm0, xmm1, xmm2": { @@ -614,6 +1400,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x66 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmgt v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtd ymm0, ymm1, ymm2": { @@ -621,6 +1415,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x66 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpgt p0.s, p7/z, z4.s, z5.s", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vpackuswb xmm0, xmm1, xmm2": { @@ -628,6 +1431,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x67 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtun v4.8b, v4.8h", + "mov v0.16b, v4.16b", + "sqxtun2 v0.16b, v5.8h", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpackuswb ymm0, ymm1, ymm2": { @@ -635,6 +1449,31 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x67 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtunb z4.b, z4.h", + "uzp1 z4.b, z4.b, z4.b", + "sqxtunb z1.b, z5.h", + "uzp1 z1.b, z1.b, z1.b", + "movprfx z4, z4", + "splice z4.b, p6, z4.b, z1.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd xmm0, xmm1, 00b": { @@ -642,6 +1481,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd xmm0, xmm1, 01b": { @@ -649,6 +1501,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[1]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd xmm0, xmm1, 10b": { @@ -656,6 +1521,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[2]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd xmm0, xmm1, 11b": { @@ -663,6 +1541,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[3]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd ymm0, ymm1, 00b": { @@ -670,6 +1561,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd ymm0, ymm1, 01b": { @@ -677,6 +1628,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd ymm0, ymm1, 10b": { @@ -684,6 +1695,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpshufd ymm0, ymm1, 11b": { @@ -691,6 +1762,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z4.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw xmm0, xmm1, 00b": { @@ -698,6 +1829,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[4], v4.h[4]", + "mov v5.16b, v0.16b", + "mov v5.h[5], v4.h[4]", + "mov v5.h[6], v4.h[4]", + "mov v0.16b, v5.16b", + "mov v0.h[7], v4.h[4]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw xmm0, xmm1, 01b": { @@ -705,6 +1849,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[4], v4.h[5]", + "mov v5.16b, v0.16b", + "mov v5.h[5], v4.h[4]", + "mov v5.h[6], v4.h[4]", + "mov v0.16b, v5.16b", + "mov v0.h[7], v4.h[4]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw xmm0, xmm1, 10b": { @@ -712,6 +1869,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[4], v4.h[6]", + "mov v5.16b, v0.16b", + "mov v5.h[5], v4.h[4]", + "mov v5.h[6], v4.h[4]", + "mov v0.16b, v5.16b", + "mov v0.h[7], v4.h[4]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw xmm0, xmm1, 11b": { @@ -719,6 +1889,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[4], v4.h[7]", + "mov v5.16b, v0.16b", + "mov v5.h[5], v4.h[4]", + "mov v5.h[6], v4.h[4]", + "mov v0.16b, v5.16b", + "mov v0.h[7], v4.h[4]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw ymm0, ymm1, 00b": { @@ -726,6 +1909,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x400", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "add z0.b, p0/m, z0.b, z0.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "adr x0, #+0x0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw ymm0, ymm1, 01b": { @@ -733,6 +1976,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[5]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[13]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x400", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "add z0.b, p0/m, z0.b, z0.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "adr x0, #+0x0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw ymm0, ymm1, 10b": { @@ -740,6 +2043,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[6]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[14]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x400", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "add z0.b, p0/m, z0.b, z0.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "adr x0, #+0x0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshufhw ymm0, ymm1, 11b": { @@ -747,6 +2110,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[7]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[15]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x400", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "add z0.b, p0/m, z0.b, z0.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "adr x0, #+0x0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw xmm0, xmm1, 00b": { @@ -754,6 +2177,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[0]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw xmm0, xmm1, 01b": { @@ -761,6 +2197,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[1]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw xmm0, xmm1, 10b": { @@ -768,6 +2217,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[2]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw xmm0, xmm1, 11b": { @@ -775,6 +2237,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v0.16b, v4.16b", + "mov v0.h[0], v4.h[3]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[0]", + "mov v5.h[2], v4.h[0]", + "mov v0.16b, v5.16b", + "mov v0.h[3], v4.h[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw ymm0, ymm1, 00b": { @@ -782,6 +2257,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x40", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw ymm0, ymm1, 01b": { @@ -789,6 +2324,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[1]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[9]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x40", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw ymm0, ymm1, 10b": { @@ -796,6 +2391,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[2]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[10]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x40", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpshuflw ymm0, ymm1, 11b": { @@ -803,6 +2458,66 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x70 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[3]", + "mov z5.d, z4.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[11]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h4", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "udf #0x40", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[8]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqb xmm0, xmm1, xmm2": { @@ -810,6 +2525,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x74 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmeq v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqb ymm0, ymm1, ymm2": { @@ -817,6 +2540,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x74 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpeq p0.b, p7/z, z4.b, z5.b", + "not z0.b, p0/m, z4.b", + "movprfx z4.b, p0/z, z4.b", + "orr z4.b, p0/m, z4.b, z0.b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqw xmm0, xmm1, xmm2": { @@ -824,6 +2556,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x75 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmeq v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqw ymm0, ymm1, ymm2": { @@ -831,6 +2571,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x75 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpeq p0.h, p7/z, z4.h, z5.h", + "not z0.h, p0/m, z4.h", + "movprfx z4.h, p0/z, z4.h", + "orr z4.h, p0/m, z4.h, z0.h", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqd xmm0, xmm1, xmm2": { @@ -838,6 +2587,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x76 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmeq v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqd ymm0, ymm1, ymm2": { @@ -845,6 +2602,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x76 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpeq p0.s, p7/z, z4.s, z5.s", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vzeroupper": { @@ -852,6 +2618,56 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x77 L=0" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z17.d, p7/m, z4.d", + "mov z4.d, p7/m, z18.d", + "mov v4.16b, v4.16b", + "mov z18.d, p7/m, z4.d", + "mov z4.d, p7/m, z19.d", + "mov v4.16b, v4.16b", + "mov z19.d, p7/m, z4.d", + "mov z4.d, p7/m, z20.d", + "mov v4.16b, v4.16b", + "mov z20.d, p7/m, z4.d", + "mov z4.d, p7/m, z21.d", + "mov v4.16b, v4.16b", + "mov z21.d, p7/m, z4.d", + "mov z4.d, p7/m, z22.d", + "mov v4.16b, v4.16b", + "mov z22.d, p7/m, z4.d", + "mov z4.d, p7/m, z23.d", + "mov v4.16b, v4.16b", + "mov z23.d, p7/m, z4.d", + "mov z4.d, p7/m, z24.d", + "mov v4.16b, v4.16b", + "mov z24.d, p7/m, z4.d", + "mov z4.d, p7/m, z25.d", + "mov v4.16b, v4.16b", + "mov z25.d, p7/m, z4.d", + "mov z4.d, p7/m, z26.d", + "mov v4.16b, v4.16b", + "mov z26.d, p7/m, z4.d", + "mov z4.d, p7/m, z27.d", + "mov v4.16b, v4.16b", + "mov z27.d, p7/m, z4.d", + "mov z4.d, p7/m, z28.d", + "mov v4.16b, v4.16b", + "mov z28.d, p7/m, z4.d", + "mov z4.d, p7/m, z29.d", + "mov v4.16b, v4.16b", + "mov z29.d, p7/m, z4.d", + "mov z4.d, p7/m, z30.d", + "mov v4.16b, v4.16b", + "mov z30.d, p7/m, z4.d", + "mov z4.d, p7/m, z31.d", + "mov v4.16b, v4.16b", + "mov z31.d, p7/m, z4.d" ] }, "vzeroall": { @@ -860,6 +2676,25 @@ "Comment": [ "Should use movi for all registers", "Map 1 0b01 0x77 L=1" + ], + "ExpectedArm64ASM": [ + "mov z4.d, #0", + "mov z16.d, p7/m, z4.d", + "mov z17.d, p7/m, z4.d", + "mov z18.d, p7/m, z4.d", + "mov z19.d, p7/m, z4.d", + "mov z20.d, p7/m, z4.d", + "mov z21.d, p7/m, z4.d", + "mov z22.d, p7/m, z4.d", + "mov z23.d, p7/m, z4.d", + "mov z24.d, p7/m, z4.d", + "mov z25.d, p7/m, z4.d", + "mov z26.d, p7/m, z4.d", + "mov z27.d, p7/m, z4.d", + "mov z28.d, p7/m, z4.d", + "mov z29.d, p7/m, z4.d", + "mov z30.d, p7/m, z4.d", + "mov z31.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x00": { @@ -867,6 +2702,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x00": { @@ -874,6 +2717,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq p0.s, p7/z, z4.s, z5.s", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x01": { @@ -881,6 +2733,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v4.4s, v5.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x01": { @@ -888,6 +2748,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.s, p7/z, z5.s, z4.s", + "not z0.s, p0/m, z5.s", + "movprfx z4.s, p0/z, z5.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x02": { @@ -895,6 +2764,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v4.4s, v5.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x02": { @@ -902,6 +2779,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge p0.s, p7/z, z5.s, z4.s", + "not z0.s, p0/m, z5.s", + "movprfx z4.s, p0/z, z5.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x03": { @@ -909,6 +2795,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v0.4s, v4.4s, v5.4s", + "fcmgt v1.4s, v5.4s, v4.4s", + "orr v4.16b, v0.16b, v1.16b", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x03": { @@ -916,6 +2813,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmuo p0.s, p7/z, z4.s, z5.s", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x04": { @@ -923,6 +2829,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq v4.4s, v4.4s, v5.4s", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x04": { @@ -930,6 +2845,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmne p0.s, p7/z, z4.s, z5.s", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x05": { @@ -937,6 +2861,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v4.4s, v5.4s, v4.4s", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x05": { @@ -944,6 +2877,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.s, p7/z, z5.s, z4.s", + "not z0.s, p0/m, z5.s", + "movprfx z4.s, p0/z, z5.s", + "orr z4.s, p0/m, z4.s, z0.s", + "not z4.b, p7/m, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x06": { @@ -951,6 +2894,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v4.4s, v5.4s, v4.4s", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x06": { @@ -958,6 +2910,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge p0.s, p7/z, z5.s, z4.s", + "not z0.s, p0/m, z5.s", + "movprfx z4.s, p0/z, z5.s", + "orr z4.s, p0/m, z4.s, z0.s", + "not z4.b, p7/m, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps xmm0, xmm1, xmm2, 0x07": { @@ -965,6 +2927,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v0.4s, v4.4s, v5.4s", + "fcmgt v1.4s, v5.4s, v4.4s", + "orr v4.16b, v0.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpps ymm0, ymm1, ymm2, 0x07": { @@ -972,6 +2944,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmuo p0.s, p7/z, z4.s, z5.s", + "not p0.b, p7/z, p0.b", + "not z0.s, p0/m, z4.s", + "movprfx z4.s, p0/z, z4.s", + "orr z4.s, p0/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x00": { @@ -979,6 +2961,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x00": { @@ -986,6 +2976,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq p0.d, p7/z, z4.d, z5.d", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x01": { @@ -993,6 +2992,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v4.2d, v5.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x01": { @@ -1000,6 +3007,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.d, p7/z, z5.d, z4.d", + "not z0.d, p0/m, z5.d", + "movprfx z4.d, p0/z, z5.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x02": { @@ -1007,6 +3023,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v4.2d, v5.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x02": { @@ -1014,6 +3038,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge p0.d, p7/z, z5.d, z4.d", + "not z0.d, p0/m, z5.d", + "movprfx z4.d, p0/z, z5.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x03": { @@ -1021,6 +3054,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v0.2d, v4.2d, v5.2d", + "fcmgt v1.2d, v5.2d, v4.2d", + "orr v4.16b, v0.16b, v1.16b", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x03": { @@ -1028,6 +3072,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmuo p0.d, p7/z, z4.d, z5.d", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x04": { @@ -1035,6 +3088,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmeq v4.2d, v4.2d, v5.2d", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x04": { @@ -1042,6 +3104,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmne p0.d, p7/z, z4.d, z5.d", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x05": { @@ -1049,6 +3120,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v4.2d, v5.2d, v4.2d", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x05": { @@ -1056,6 +3136,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.d, p7/z, z5.d, z4.d", + "not z0.d, p0/m, z5.d", + "movprfx z4.d, p0/z, z5.d", + "orr z4.d, p0/m, z4.d, z0.d", + "not z4.b, p7/m, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x06": { @@ -1063,6 +3153,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v4.2d, v5.2d, v4.2d", + "mvn v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x06": { @@ -1070,6 +3169,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge p0.d, p7/z, z5.d, z4.d", + "not z0.d, p0/m, z5.d", + "movprfx z4.d, p0/z, z5.d", + "orr z4.d, p0/m, z4.d, z0.d", + "not z4.b, p7/m, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd xmm0, xmm1, xmm2, 0x07": { @@ -1077,6 +3186,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmge v0.2d, v4.2d, v5.2d", + "fcmgt v1.2d, v5.2d, v4.2d", + "orr v4.16b, v0.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmppd ymm0, ymm1, ymm2, 0x07": { @@ -1084,6 +3203,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmuo p0.d, p7/z, z4.d, z5.d", + "not p0.b, p7/z, p0.b", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x00": { @@ -1091,6 +3220,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmeq s5, s4, s5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x01": { @@ -1098,6 +3239,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmgt s5, s5, s4", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x02": { @@ -1105,6 +3258,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmge s5, s5, s4", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x03": { @@ -1112,6 +3277,21 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmge s0, s4, s5", + "fcmgt s1, s5, s4", + "orr v5.8b, v0.8b, v1.8b", + "mvn v5.8b, v5.8b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x04": { @@ -1119,6 +3299,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmeq s5, s4, s5", + "mvn v5.8b, v5.8b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x05": { @@ -1126,6 +3319,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmgt s5, s5, s4", + "mvn v5.16b, v5.16b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x06": { @@ -1133,6 +3339,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmge s5, s5, s4", + "mvn v5.16b, v5.16b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpss xmm0, xmm1, xmm2, 0x07": { @@ -1140,6 +3359,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmge s0, s4, s5", + "fcmgt s1, s5, s4", + "orr v5.8b, v0.8b, v1.8b", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x00": { @@ -1147,6 +3380,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmeq d5, d4, d5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x01": { @@ -1154,6 +3397,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmgt d5, d5, d4", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x02": { @@ -1161,6 +3414,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmge d5, d5, d4", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x03": { @@ -1168,6 +3431,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmge d0, d4, d5", + "fcmgt d1, d5, d4", + "orr v5.8b, v0.8b, v1.8b", + "mvn v5.8b, v5.8b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x04": { @@ -1175,6 +3451,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmeq d5, d4, d5", + "mvn v5.8b, v5.8b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x05": { @@ -1182,6 +3469,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmgt d5, d5, d4", + "mvn v5.16b, v5.16b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x06": { @@ -1189,6 +3487,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmge d5, d5, d4", + "mvn v5.16b, v5.16b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcmpsd xmm0, xmm1, xmm2, 0x07": { @@ -1196,6 +3505,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xC2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmge d0, d4, d5", + "fcmgt d1, d5, d4", + "orr v5.8b, v0.8b, v1.8b", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrw xmm0, xmm1, eax, 000b": { @@ -1203,6 +3524,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.h[0], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrw xmm0, xmm1, eax, 001b": { @@ -1210,6 +3540,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.h[1], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrw xmm0, xmm1, eax, 111b": { @@ -1217,6 +3556,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" + ], + "ExpectedArm64ASM": [ + "uxth x20, w4", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.h[7], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpextrw eax, xmm0, 000b": { @@ -1224,6 +3572,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.h[0]", + "uxth x4, w20" ] }, "vpextrw eax, xmm0, 001b": { @@ -1231,6 +3584,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.h[1]", + "uxth x4, w20" ] }, "vpextrw eax, xmm0, 111b": { @@ -1238,6 +3596,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.h[7]", + "uxth x4, w20" ] }, "vshufps xmm0, xmm1, xmm2, 00b": { @@ -1245,6 +3608,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[0]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[0]", + "mov v4.s[3], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufps ymm0, ymm1, ymm2, 00b": { @@ -1252,6 +3629,67 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vshufps xmm0, xmm1, xmm2, 01b": { @@ -1259,6 +3697,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[1]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[0]", + "mov v4.s[3], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufps ymm0, ymm1, ymm2, 01b": { @@ -1266,6 +3718,67 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vshufps xmm0, xmm1, xmm2, 10b": { @@ -1273,6 +3786,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[2]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[0]", + "mov v4.s[3], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufps ymm0, ymm1, ymm2, 10b": { @@ -1280,6 +3807,67 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vshufps xmm0, xmm1, xmm2, 11b": { @@ -1287,6 +3875,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v0.16b, v4.16b", + "mov v0.s[0], v4.s[3]", + "mov v6.16b, v0.16b", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[0]", + "mov v4.s[3], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufps ymm0, ymm1, ymm2, 11b": { @@ -1294,6 +3896,67 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vshufpd xmm0, xmm1, xmm2, 0b": { @@ -1301,6 +3964,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.d[0], v4.d[0]", + "mov v4.d[1], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufpd ymm0, ymm1, ymm2, 0b": { @@ -1308,6 +3979,39 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z4.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vshufpd xmm0, xmm1, xmm2, 1b": { @@ -1315,6 +4019,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.d[0], v4.d[1]", + "mov v4.d[1], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vshufpd ymm0, ymm1, ymm2, 1b": { @@ -1322,6 +4034,39 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xC6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z6.d, z4.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmovaps xmm0, [rax]": { @@ -1329,6 +4074,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x28 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovaps ymm0, [rax]": { @@ -1336,6 +4085,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x28 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovapd xmm0, [rax]": { @@ -1343,6 +4096,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x28 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovapd ymm0, [rax]": { @@ -1350,6 +4107,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x28 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovaps [rax], xmm0": { @@ -1357,6 +4118,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x29 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovaps [rax], ymm0": { @@ -1364,6 +4129,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x29 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vmovapd [rax], xmm0": { @@ -1371,6 +4140,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x29 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovapd [rax], ymm0": { @@ -1378,6 +4151,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x29 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vcvtsi2ss xmm0, xmm1, eax": { @@ -1385,6 +4162,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ubfx x20, x4, #0, #32", + "scvtf s5, w20", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtsi2ss xmm0, xmm1, rax": { @@ -1392,6 +4177,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "scvtf s5, x4", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtsi2sd xmm0, xmm1, eax": { @@ -1399,6 +4191,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ubfx x20, x4, #0, #32", + "scvtf d5, w20", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtsi2sd xmm0, xmm1, rax": { @@ -1406,6 +4206,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2A 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "scvtf d5, x4", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovntps [rax], xmm0": { @@ -1413,6 +4220,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x2B 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovntps [rax], ymm0": { @@ -1420,6 +4231,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x2B 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vmovntpd [rax], xmm0": { @@ -1427,6 +4242,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x2B 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovntpd [rax], ymm0": { @@ -1434,6 +4253,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x2B 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vcvttss2si eax, xmm0": { @@ -1441,6 +4264,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "fcvtzs w4, s4" ] }, "vcvttss2si rax, xmm0": { @@ -1448,6 +4278,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "fcvtzs x4, s4" ] }, "vcvttsd2si eax, xmm0": { @@ -1455,6 +4290,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "fcvtzs w4, d4" ] }, "vcvttsd2si rax, xmm0": { @@ -1462,6 +4302,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "fcvtzs x4, d4" ] }, "vcvtss2si eax, xmm0": { @@ -1469,6 +4314,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frinti s0, s4", + "fcvtzs w4, s0" ] }, "vcvtss2si rax, xmm0": { @@ -1476,6 +4329,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "frinti s0, s4", + "fcvtzs x4, s0" ] }, "vcvtsd2si eax, xmm0": { @@ -1483,6 +4342,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "frinti d0, d4", + "fcvtzs x4, d0" ] }, "vcvtsd2si rax, xmm0": { @@ -1490,6 +4355,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "frinti d0, d4", + "fcvtzs x4, d0" ] }, "vucomiss xmm0, xmm1": { @@ -1497,6 +4368,33 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "fcmp s4, s5", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "vucomisd xmm0, xmm1": { @@ -1504,6 +4402,33 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "fcmp d4, d5", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "vcomiss xmm0, xmm1": { @@ -1511,6 +4436,33 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "fcmp s4, s5", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "vcomisd xmm0, xmm1": { @@ -1518,6 +4470,33 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "fcmp d4, d5", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "bfi w21, w20, #31, #1", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "vaddps xmm0, xmm1, xmm2": { @@ -1525,6 +4504,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaddps ymm0, ymm1, ymm2": { @@ -1532,6 +4519,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x58 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vaddpd xmm0, xmm1, xmm2": { @@ -1539,6 +4532,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaddpd ymm0, ymm1, ymm2": { @@ -1546,6 +4547,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x58 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vaddss xmm0, xmm1, xmm2": { @@ -1553,6 +4560,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd s5, s4, s5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaddsd xmm0, xmm1, xmm2": { @@ -1560,6 +4576,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd d5, d4, d5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmulps xmm0, xmm1, xmm2": { @@ -1567,6 +4592,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmulps ymm0, ymm1, ymm2": { @@ -1574,6 +4607,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x59 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vmulpd xmm0, xmm1, xmm2": { @@ -1581,6 +4620,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmulpd ymm0, ymm1, ymm2": { @@ -1588,6 +4635,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x59 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vmulss xmm0, xmm1, xmm2": { @@ -1595,6 +4648,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul s5, s4, s5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmulsd xmm0, xmm1, xmm2": { @@ -1602,6 +4664,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fmul d5, d4, d5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtps2pd xmm0, xmm1": { @@ -1609,6 +4680,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "fcvtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtpd2ps xmm0, xmm1": { @@ -1616,6 +4695,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtn v4.2s, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtss2sd xmm0, xmm1, xmm2": { @@ -1623,6 +4709,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcvt d5, s5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtsd2ss xmm0, xmm1, xmm2": { @@ -1630,6 +4727,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x5a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcvt s5, d5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtdq2ps xmm0, xmm1": { @@ -1637,6 +4743,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "scvtf v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtdq2ps ymm0, ymm1": { @@ -1644,6 +4757,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "scvtf z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vcvtps2dq xmm0, xmm1": { @@ -1651,6 +4769,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti v4.4s, v4.4s", + "fcvtzs v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtps2dq ymm0, ymm1": { @@ -1658,6 +4784,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti z4.s, p7/m, z4.s", + "fcvtzs z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vcvttps2dq xmm0, xmm1": { @@ -1665,6 +4797,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtzs v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvttps2dq ymm0, ymm1": { @@ -1672,6 +4811,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtzs z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vsubps xmm0, xmm1, xmm2": { @@ -1679,6 +4823,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsubps ymm0, ymm1, ymm2": { @@ -1686,6 +4838,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vsubpd xmm0, xmm1, xmm2": { @@ -1693,6 +4851,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsubpd ymm0, ymm1, ymm2": { @@ -1700,6 +4866,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vsubss xmm0, xmm1, xmm2": { @@ -1707,6 +4879,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub s5, s4, s5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vsubsd xmm0, xmm1, xmm2": { @@ -1714,6 +4895,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x5c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fsub d5, d4, d5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vminps xmm0, xmm1, xmm2": { @@ -1721,6 +4911,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v0.4s, v5.4s, v4.4s", + "mov v1.16b, v4.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v4.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vminps ymm0, ymm1, ymm2": { @@ -1728,6 +4929,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.s, p7/z, z5.s, z4.s", + "not p0.b, p7/z, p0.b", + "mov z0.d, z4.d", + "mov z0.s, p0/m, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vminpd xmm0, xmm1, xmm2": { @@ -1735,6 +4946,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v0.2d, v5.2d, v4.2d", + "mov v1.16b, v4.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v4.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vminpd ymm0, ymm1, ymm2": { @@ -1742,6 +4964,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.d, p7/z, z5.d, z4.d", + "not p0.b, p7/z, p0.b", + "mov z0.d, z4.d", + "mov z0.d, p0/m, z5.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vminss xmm0, xmm1, xmm2": { @@ -1749,6 +4981,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmp s4, s5", + "fcsel s5, s4, s5, mi", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vminsd xmm0, xmm1, xmm2": { @@ -1756,6 +5001,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x5d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmp d4, d5", + "fcsel d5, d4, d5, mi", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdivps xmm0, xmm1, xmm2": { @@ -1763,6 +5019,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fdiv v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdivps ymm0, ymm1, ymm2": { @@ -1770,6 +5034,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "fdiv z0.s, p7/m, z0.s, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vdivpd xmm0, xmm1, xmm2": { @@ -1777,6 +5049,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fdiv v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdivpd ymm0, ymm1, ymm2": { @@ -1784,6 +5064,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "fdiv z0.d, p7/m, z0.d, z5.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vdivss xmm0, xmm1, xmm2": { @@ -1791,6 +5079,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fdiv s5, s4, s5", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdivsd xmm0, xmm1, xmm2": { @@ -1798,6 +5095,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x5e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fdiv d5, d4, d5", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaxps xmm0, xmm1, xmm2": { @@ -1805,6 +5111,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v0.4s, v5.4s, v4.4s", + "mov v1.16b, v4.16b", + "bit v1.16b, v5.16b, v0.16b", + "mov v4.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaxps ymm0, ymm1, ymm2": { @@ -1812,6 +5129,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b00 0x5f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.s, p7/z, z5.s, z4.s", + "mov z0.d, z4.d", + "mov z0.s, p0/m, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vmaxpd xmm0, xmm1, xmm2": { @@ -1819,6 +5145,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt v0.2d, v5.2d, v4.2d", + "mov v1.16b, v4.16b", + "bit v1.16b, v5.16b, v0.16b", + "mov v4.16b, v1.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaxpd ymm0, ymm1, ymm2": { @@ -1826,6 +5163,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x5f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fcmgt p0.d, p7/z, z5.d, z4.d", + "mov z0.d, z4.d", + "mov z0.d, p0/m, z5.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vmaxss xmm0, xmm1, xmm2": { @@ -1833,6 +5179,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "fcmp s4, s5", + "fcsel s5, s5, s4, mi", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaxsd xmm0, xmm1, xmm2": { @@ -1840,6 +5199,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x5f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v5.8b, v5.8b", + "fcmp d4, d5", + "fcsel d5, d5, d4, mi", + "mov v4.d[0], v5.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhbw xmm0, xmm1, xmm2": { @@ -1847,6 +5217,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x68 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip2 v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhbw ymm0, ymm1, ymm2": { @@ -1854,6 +5231,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x68 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.b, z4.b, z5.b", + "zip2 z4.b, z4.b, z5.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhwd xmm0, xmm1, xmm2": { @@ -1861,6 +5252,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x69 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip2 v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhwd ymm0, ymm1, ymm2": { @@ -1868,6 +5266,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x69 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.h, z4.h, z5.h", + "zip2 z4.h, z4.h, z5.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhdq xmm0, xmm1, xmm2": { @@ -1875,6 +5287,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip2 v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhdq ymm0, ymm1, ymm2": { @@ -1882,6 +5301,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6a 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.s, z4.s, z5.s", + "zip2 z4.s, z4.s, z5.s", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vpackssdw xmm0, xmm1, xmm2": { @@ -1889,6 +5322,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtn v4.4h, v4.4s", + "mov v0.16b, v4.16b", + "sqxtn2 v0.8h, v5.4s", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpackssdw ymm0, ymm1, ymm2": { @@ -1896,6 +5340,31 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtnb z4.h, z4.s", + "uzp1 z4.h, z4.h, z4.h", + "sqxtnb z1.h, z5.s", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z4", + "splice z4.h, p6, z4.h, z1.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklqdq xmm0, xmm1, xmm2": { @@ -1903,6 +5372,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpcklqdq ymm0, ymm1, ymm2": { @@ -1910,6 +5386,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.d, z4.d, z5.d", + "zip2 z4.d, z4.d, z5.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhqdq xmm0, xmm1, xmm2": { @@ -1917,6 +5407,13 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip2 v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpunpckhqdq ymm0, ymm1, ymm2": { @@ -1924,6 +5421,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "zip1 z6.d, z4.d, z5.d", + "zip2 z4.d, z4.d, z5.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z6.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vmovd xmm0, dword [rax]": { @@ -1931,6 +5442,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6e 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "fmov s4, w20", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovq xmm0, qword [rax]": { @@ -1938,6 +5455,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6e 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovdqa xmm0, [rax]": { @@ -1945,6 +5466,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6f 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovdqa [rax], xmm0": { @@ -1952,6 +5477,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x6f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovdqu xmm0, [rax]": { @@ -1959,6 +5488,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x6f 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovdqu [rax], xmm0": { @@ -1966,6 +5499,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x6f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vhaddpd xmm0, xmm1, xmm2": { @@ -1973,6 +5510,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "faddp v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vhaddpd ymm0, ymm1, ymm2": { @@ -1980,6 +5525,30 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "faddp z0.d, p7/m, z0.d, z5.d", + "uzp1 z4.d, z0.d, z0.d", + "uzp2 z1.d, z0.d, z0.d", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vhaddps xmm0, xmm1, xmm2": { @@ -1987,6 +5556,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x7c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "faddp v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vhaddps ymm0, ymm1, ymm2": { @@ -1994,6 +5571,30 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x7c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z5.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vhsubpd xmm0, xmm1, xmm2": { @@ -2001,6 +5602,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fneg v6.2d, v4.2d", + "fneg v7.2d, v5.2d", + "mov v4.d[1], v6.d[1]", + "mov v5.d[1], v7.d[1]", + "faddp v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vhsubpd ymm0, ymm1, ymm2": { @@ -2008,6 +5620,38 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fneg z6.d, p7/m, z4.d", + "fneg z7.d, p7/m, z5.d", + "uzp1 z4.d, z4.d, z4.d", + "uzp1 z5.d, z5.d, z5.d", + "uzp2 z6.d, z6.d, z6.d", + "uzp2 z7.d, z7.d, z7.d", + "zip1 z4.d, z4.d, z6.d", + "zip1 z5.d, z5.d, z7.d", + "movprfx z0, z4", + "faddp z0.d, p7/m, z0.d, z5.d", + "uzp1 z4.d, z0.d, z0.d", + "uzp2 z1.d, z0.d, z0.d", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vhsubps xmm0, xmm1, xmm2": { @@ -2015,6 +5659,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x7d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fneg v6.4s, v4.4s", + "fneg v7.4s, v5.4s", + "mov v4.s[1], v6.s[1]", + "mov v4.s[3], v6.s[3]", + "mov v5.s[1], v7.s[1]", + "mov v5.s[3], v7.s[3]", + "faddp v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vhsubps ymm0, ymm1, ymm2": { @@ -2022,6 +5679,38 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0x7d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fneg z6.s, p7/m, z4.s", + "fneg z7.s, p7/m, z5.s", + "uzp1 z4.s, z4.s, z4.s", + "uzp1 z5.s, z5.s, z5.s", + "uzp2 z6.s, z6.s, z6.s", + "uzp2 z7.s, z7.s, z7.s", + "zip1 z4.s, z4.s, z6.s", + "zip1 z5.s, z5.s, z7.s", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z5.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmovd dword [rax], xmm0": { @@ -2029,6 +5718,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov w20, v4.s[0]", + "str w20, [x4]" ] }, "vmovq qword [rax], xmm0": { @@ -2036,6 +5733,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "str d4, [x4]" ] }, "vmovdqa ymm0, [rax]": { @@ -2043,6 +5745,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7f 128-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovdqa [rax], ymm0": { @@ -2050,6 +5756,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0x7f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vmovdqu ymm0, [rax]": { @@ -2057,6 +5767,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x7f 128-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovdqu [rax], ymm0": { @@ -2064,6 +5778,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0x7f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vaddsubpd xmm0, xmm1, xmm2": { @@ -2071,6 +5789,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd0 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd v6.2d, v4.2d, v5.2d", + "fsub v4.2d, v4.2d, v5.2d", + "uzp1 v4.2d, v4.2d, v4.2d", + "uzp2 v5.2d, v6.2d, v6.2d", + "zip1 v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaddsubpd ymm0, ymm1, ymm2": { @@ -2078,6 +5808,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd0 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd z6.d, z4.d, z5.d", + "fsub z4.d, z4.d, z5.d", + "uzp1 z4.d, z4.d, z4.d", + "uzp2 z5.d, z6.d, z6.d", + "zip1 z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vaddsubps xmm0, xmm1, xmm2": { @@ -2085,6 +5825,18 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xd0 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd v6.4s, v4.4s, v5.4s", + "fsub v4.4s, v4.4s, v5.4s", + "uzp1 v4.4s, v4.4s, v4.4s", + "uzp2 v5.4s, v6.4s, v6.4s", + "zip1 v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaddsubps ymm0, ymm1, ymm2": { @@ -2092,6 +5844,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xd0 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "fadd z6.s, z4.s, z5.s", + "fsub z4.s, z4.s, z5.s", + "uzp1 z4.s, z4.s, z4.s", + "uzp2 z5.s, z6.s, z6.s", + "zip1 z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw xmm0, xmm1, xmm2": { @@ -2099,6 +5861,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd1 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.8h, v5.h[0]", + "neg v0.8h, v0.8h", + "ushl v4.8h, v4.8h, v0.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw ymm0, ymm1, xmm2": { @@ -2106,6 +5884,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd1 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.h, h5", + "movprfx z4, z4", + "lsr z4.h, p7/m, z4.h, z0.h", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld xmm0, xmm1, xmm2": { @@ -2113,6 +5905,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.4s, v5.s[0]", + "neg v0.4s, v0.4s", + "ushl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld ymm0, ymm1, xmm2": { @@ -2120,6 +5928,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.s, s5", + "movprfx z4, z4", + "lsr z4.s, p7/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq xmm0, xmm1, xmm2": { @@ -2127,6 +5949,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd3 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.2d, v5.d[0]", + "neg v0.2d, v0.2d", + "ushl v4.2d, v4.2d, v0.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq ymm0, ymm1, xmm2": { @@ -2134,6 +5972,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd3 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.d, d5", + "movprfx z4, z4", + "lsr z4.d, p7/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpaddq xmm0, xmm1, xmm2": { @@ -2141,6 +5993,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd4 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddq ymm0, ymm1, ymm2": { @@ -2148,6 +6008,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd4 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmullw xmm0, xmm1, xmm2": { @@ -2155,6 +6021,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mul v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmullw ymm0, ymm1, ymm2": { @@ -2162,6 +6036,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd4 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mul z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vmovq [rax], xmm0": { @@ -2169,6 +6049,11 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.8b, v4.8b", + "str d4, [x4]" ] }, "vpmovmskb rax, xmm0": { @@ -2176,6 +6061,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd7 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v5.2d, x20", + "cmlt v4.16b, v4.16b, #0", + "and v4.16b, v4.16b, v5.16b", + "addp v4.16b, v4.16b, v4.16b", + "addp v4.8b, v4.8b, v4.8b", + "addp v4.8b, v4.8b, v4.8b", + "umov w4, v4.h[0]" ] }, "vpmovmskb rax, ymm0": { @@ -2183,6 +6082,28 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd7 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "mov z5.d, x20", + "mov z0.d, #0", + "cmplt p0.b, p7/z, z4.b, #0", + "not z0.b, p0/m, z4.b", + "orr z0.b, p0/m, z0.b, z4.b", + "mov z4.d, z0.d", + "and z4.d, z4.d, z5.d", + "movprfx z0, z4", + "addp z0.b, p7/m, z0.b, z4.b", + "uzp1 z4.b, z0.b, z0.b", + "uzp2 z1.b, z0.b, z0.b", + "splice z4.d, p6, z4.d, z1.d", + "addp v4.16b, v4.16b, v4.16b", + "addp v4.8b, v4.8b, v4.8b", + "mov w4, v4.s[0]" ] }, "vpsubusb xmm0, xmm1, xmm2": { @@ -2190,6 +6111,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd8 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqsub v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubusb ymm0, ymm1, ymm2": { @@ -2197,6 +6126,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd8 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqsub z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubusw xmm0, xmm1, xmm2": { @@ -2204,6 +6139,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd9 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqsub v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubusw ymm0, ymm1, ymm2": { @@ -2211,6 +6154,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xd9 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqsub z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpminub xmm0, xmm1, xmm2": { @@ -2218,6 +6167,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xda 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umin v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminub ymm0, ymm1, ymm2": { @@ -2225,6 +6182,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xda 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umin z0.b, p7/m, z0.b, z5.b", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpand xmm0, xmm1, xmm2": { @@ -2232,6 +6197,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdb 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "and v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpand ymm0, ymm1, ymm2": { @@ -2239,6 +6212,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdb 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "and z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpaddusb xmm0, xmm1, xmm2": { @@ -2246,6 +6225,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdc 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqadd v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddusb ymm0, ymm1, ymm2": { @@ -2253,6 +6240,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdc 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqadd z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddusw xmm0, xmm1, xmm2": { @@ -2260,6 +6253,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdd 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqadd v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddusw ymm0, ymm1, ymm2": { @@ -2267,6 +6268,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdd 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uqadd z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxub xmm0, xmm1, xmm2": { @@ -2274,6 +6281,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdd 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umax v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxub ymm0, ymm1, ymm2": { @@ -2281,6 +6296,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xde 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umax z0.b, p7/m, z0.b, z5.b", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpandn xmm0, xmm1, xmm2": { @@ -2288,6 +6311,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdf 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "bic v4.16b, v5.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpandn ymm0, ymm1, ymm2": { @@ -2295,6 +6326,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xdf 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "bic z4.d, z5.d, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vpavgb xmm0, xmm1, xmm2": { @@ -2302,6 +6339,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe0 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "urhadd v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpavgb ymm0, ymm1, ymm2": { @@ -2309,6 +6354,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe0 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "urhadd z0.b, p7/m, z0.b, z5.b", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw xmm0, xmm1, xmm2": { @@ -2316,6 +6369,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe1 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.8h, v5.h[0]", + "neg v0.8h, v0.8h", + "sshl v4.8h, v4.8h, v0.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw ymm0, ymm1, xmm2": { @@ -2323,6 +6392,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe1 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.h, h5", + "movprfx z4, z4", + "asr z4.h, p7/m, z4.h, z0.h", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad xmm0, xmm1, xmm2": { @@ -2330,6 +6413,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.4s, v5.s[0]", + "neg v0.4s, v0.4s", + "sshl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad ymm0, ymm1, xmm2": { @@ -2337,6 +6436,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.s, s5", + "movprfx z4, z4", + "asr z4.s, p7/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vpavgw xmm0, xmm1, xmm2": { @@ -2344,6 +6457,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe3 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "urhadd v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpavgw ymm0, ymm1, ymm2": { @@ -2351,6 +6472,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe3 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "urhadd z0.h, p7/m, z0.h, z5.h", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhuw xmm0, xmm1, xmm2": { @@ -2358,6 +6487,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe4 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umull v6.4s, v4.4h, v5.4h", + "umull2 v4.4s, v4.8h, v5.8h", + "shrn v5.4h, v6.4s, #16", + "mov v0.16b, v5.16b", + "shrn2 v0.8h, v4.4s, #16", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhuw ymm0, ymm1, ymm2": { @@ -2365,6 +6507,23 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe4 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umullb z0.s, z4.h, z5.h", + "umullt z1.s, z4.h, z5.h", + "zip1 z6.s, z0.s, z1.s", + "umullb z0.s, z4.h, z5.h", + "umullt z1.s, z4.h, z5.h", + "zip2 z4.s, z0.s, z1.s", + "shrnb z5.h, z6.s, #16", + "uzp1 z5.h, z5.h, z5.h", + "shrnb z1.h, z4.s, #16", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z5", + "splice z4.h, p6, z4.h, z1.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhw xmm0, xmm1, xmm2": { @@ -2372,6 +6531,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smull v6.4s, v4.4h, v5.4h", + "smull2 v4.4s, v4.8h, v5.8h", + "shrn v5.4h, v6.4s, #16", + "mov v0.16b, v5.16b", + "shrn2 v0.8h, v4.4s, #16", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhw ymm0, ymm1, ymm2": { @@ -2379,6 +6551,23 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe5 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip1 z6.s, z0.s, z1.s", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip2 z4.s, z0.s, z1.s", + "shrnb z5.h, z6.s, #16", + "uzp1 z5.h, z5.h, z5.h", + "shrnb z1.h, z4.s, #16", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z5", + "splice z4.h, p6, z4.h, z1.h", + "mov z16.d, p7/m, z4.d" ] }, "vcvttpd2dq xmm0, xmm1": { @@ -2386,6 +6575,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtn v4.2s, v4.2d", + "fcvtzs v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvttpd2dq xmm0, ymm1": { @@ -2393,6 +6590,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtnt z4.s, p7/m, z4.d", + "uzp2 z4.s, z4.s, z4.s", + "fcvtzs z4.s, p7/m, z4.s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtdq2pd xmm0, xmm1": { @@ -2400,6 +6605,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xe6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "sxtl v4.2d, v4.2s", + "scvtf v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtdq2pd ymm0, xmm1": { @@ -2407,6 +6621,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b10 0xe6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.d, z4.s", + "scvtf z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vcvtpd2dq xmm0, xmm1": { @@ -2414,6 +6634,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xe6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtn v4.2s, v4.2d", + "frinti v4.4s, v4.4s", + "fcvtzs v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtpd2dq xmm0, ymm1": { @@ -2421,6 +6650,15 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xe6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "fcvtnt z4.s, p7/m, z4.d", + "uzp2 z4.s, z4.s, z4.s", + "frinti z4.s, p7/m, z4.s", + "fcvtzs z4.s, p7/m, z4.s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmovntdq [rax], xmm0": { @@ -2428,6 +6666,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe7 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "str q4, [x4]" ] }, "vmovntdq [rax], ymm0": { @@ -2435,6 +6677,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe7 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "st1b {z4.b}, p7, [x4]" ] }, "vpsubsb xmm0, xmm1, xmm2": { @@ -2442,6 +6688,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe8 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqsub v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubsb ymm0, ymm1, ymm2": { @@ -2449,6 +6703,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe8 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqsub z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubsw xmm0, xmm1, xmm2": { @@ -2456,6 +6716,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe9 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqsub v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubsw ymm0, ymm1, ymm2": { @@ -2463,6 +6731,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xe9 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqsub z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpminsw xmm0, xmm1, xmm2": { @@ -2470,6 +6744,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xea 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smin v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminsw ymm0, ymm1, ymm2": { @@ -2477,6 +6759,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xea 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smin z0.h, p7/m, z0.h, z5.h", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpor xmm0, xmm1, xmm2": { @@ -2484,6 +6774,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xeb 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpor ymm0, ymm1, ymm2": { @@ -2491,6 +6789,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xeb 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpaddsb xmm0, xmm1, xmm2": { @@ -2498,6 +6802,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xec 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqadd v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddsb ymm0, ymm1, ymm2": { @@ -2505,6 +6817,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xec 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqadd z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddsw xmm0, xmm1, xmm2": { @@ -2512,6 +6830,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xed 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqadd v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddsw ymm0, ymm1, ymm2": { @@ -2519,6 +6845,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xed 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqadd z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsw xmm0, xmm1, xmm2": { @@ -2526,6 +6858,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xee 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smax v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsw ymm0, ymm1, ymm2": { @@ -2533,6 +6873,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xee 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smax z0.h, p7/m, z0.h, z5.h", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpxor xmm0, xmm1, xmm2": { @@ -2540,6 +6888,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xef 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpxor ymm0, ymm1, ymm2": { @@ -2547,6 +6903,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xef 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vlddqu xmm0, [rax]": { @@ -2554,6 +6916,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xf0 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vlddqu ymm0, [rax]": { @@ -2561,6 +6927,10 @@ "Optimal": "No", "Comment": [ "Map 1 0b11 0xf0 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw xmm0, xmm1, xmm2": { @@ -2568,6 +6938,21 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf1 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.8h, v5.h[0]", + "ushl v4.8h, v4.8h, v0.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw ymm0, ymm1, xmm2": { @@ -2575,6 +6960,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf1 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x10", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.h, h5", + "movprfx z4, z4", + "lsl z4.h, p7/m, z4.h, z0.h", + "mov z16.d, p7/m, z4.d" ] }, "vpslld xmm0, xmm1, xmm2": { @@ -2582,6 +6981,21 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf2 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.4s, v5.s[0]", + "ushl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslld ymm0, ymm1, xmm2": { @@ -2589,6 +7003,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf2 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x20", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.s, s5", + "movprfx z4, z4", + "lsl z4.s, p7/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq xmm0, xmm1, xmm2": { @@ -2596,6 +7024,21 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf3 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "dup v0.2d, v5.d[0]", + "ushl v4.2d, v4.2d, v0.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq ymm0, ymm1, xmm2": { @@ -2603,6 +7046,20 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf3 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v6.2d, x0", + "cmhi v0.2d, v5.2d, v6.2d", + "mov v1.16b, v6.16b", + "bif v1.16b, v5.16b, v0.16b", + "mov v5.16b, v1.16b", + "mov z0.d, d5", + "movprfx z4, z4", + "lsl z4.d, p7/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmuludq xmm0, xmm1, xmm2": { @@ -2610,6 +7067,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf4 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.s[1], v4.s[2]", + "mov v5.s[1], v5.s[2]", + "umull v4.2d, v4.2s, v5.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmuludq ymm0, ymm1, ymm2": { @@ -2617,6 +7084,56 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf4 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[2]", + "mov z7.d, z5.d", + "mov z7.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z6.d, z7.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[6]", + "mov z5.d, z6.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "umullb z0.d, z4.s, z5.s", + "umullt z1.d, z4.s, z5.s", + "zip1 z4.d, z0.d, z1.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmaddwd xmm0, xmm1, xmm2": { @@ -2624,6 +7141,19 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf5 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sxtl v6.4s, v4.4h", + "sxtl2 v4.4s, v4.8h", + "sxtl v7.4s, v5.4h", + "sxtl2 v5.4s, v5.8h", + "mul v6.4s, v6.4s, v7.4s", + "mul v4.4s, v4.4s, v5.4s", + "addp v4.4s, v6.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaddwd ymm0, ymm1, ymm2": { @@ -2631,6 +7161,22 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf5 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sunpklo z6.s, z4.h", + "sunpkhi z4.s, z4.h", + "sunpklo z7.s, z5.h", + "sunpkhi z5.s, z5.h", + "mul z6.s, z6.s, z7.s", + "mul z4.s, z4.s, z5.s", + "movprfx z0, z6", + "addp z0.s, p7/m, z0.s, z4.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsadbw xmm0, xmm1, xmm2": { @@ -2638,6 +7184,17 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf6 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uabdl v6.8h, v4.8b, v5.8b", + "uabdl2 v4.8h, v4.16b, v5.16b", + "addv h5, v6.8h", + "addv h4, v4.8h", + "zip1 v4.2d, v5.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsadbw ymm0, ymm1, ymm2": { @@ -2645,6 +7202,52 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf6 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uabdlb z0.h, z4.b, z5.b", + "uabdlt z1.h, z4.b, z5.b", + "zip1 z6.h, z0.h, z1.h", + "uabdlb z0.h, z4.b, z5.b", + "uabdlt z1.h, z4.b, z5.b", + "zip2 z4.h, z0.h, z1.h", + "addv h5, v6.8h", + "addv h7, v4.8h", + "zip1 z5.d, z5.d, z7.d", + "mov z6.q, z6.q[1]", + "mov z4.q, z4.q[1]", + "addv h6, v6.8h", + "addv h4, v4.8h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovdqu xmm0, xmm1": { @@ -2652,6 +7255,16 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf7 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmlt v4.16b, v4.16b, #0", + "mov z5.d, p7/m, z16.d", + "ldr q6, [x11]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v5.16b, v6.16b", + "mov v4.16b, v0.16b", + "str q4, [x11]" ] }, "vpsubb xmm0, xmm1, xmm2": { @@ -2659,6 +7272,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf8 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubb ymm0, ymm1, ymm2": { @@ -2666,6 +7287,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf8 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubw xmm0, xmm1, xmm2": { @@ -2673,6 +7300,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf9 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubw ymm0, ymm1, ymm2": { @@ -2680,6 +7315,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xf9 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpsubd xmm0, xmm1, xmm2": { @@ -2687,6 +7328,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfa 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubd ymm0, ymm1, ymm2": { @@ -2694,6 +7343,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfa 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsubq xmm0, xmm1, xmm2": { @@ -2701,6 +7356,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfb 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsubq ymm0, ymm1, ymm2": { @@ -2708,6 +7371,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfb 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sub z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpaddb xmm0, xmm1, xmm2": { @@ -2715,6 +7384,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfc 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddb ymm0, ymm1, ymm2": { @@ -2722,6 +7399,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfc 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add z4.b, z4.b, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddw xmm0, xmm1, xmm2": { @@ -2729,6 +7412,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfd 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddw ymm0, ymm1, ymm2": { @@ -2736,6 +7427,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfd 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add z4.h, z4.h, z5.h", + "mov z16.d, p7/m, z4.d" ] }, "vpaddd xmm0, xmm1, xmm2": { @@ -2743,6 +7440,14 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfe 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpaddd ymm0, ymm1, ymm2": { @@ -2750,6 +7455,12 @@ "Optimal": "No", "Comment": [ "Map 1 0b01 0xfe 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "add z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] } } diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index c4b93087e..239f43bf7 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -12,6 +12,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x00 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.16b, #0x8f", + "and v5.16b, v5.16b, v6.16b", + "tbl v4.16b, {v4.16b}, v5.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpshufb ymm0, ymm1, ymm2": { @@ -19,6 +28,29 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x00 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.b, #-113", + "and z5.d, z5.d, z6.d", + "tbl v6.16b, {v4.16b}, v5.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "tbl v4.16b, {v4.16b}, v5.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vphaddw xmm0, xmm1, xmm2": { @@ -26,6 +58,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x01 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "addp v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphaddw ymm0, ymm1, ymm2": { @@ -33,6 +73,30 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x01 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "addp z0.h, p7/m, z0.h, z5.h", + "uzp1 z4.h, z0.h, z0.h", + "uzp2 z1.h, z0.h, z0.h", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vphaddd xmm0, xmm1, xmm2": { @@ -40,6 +104,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "addp v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphaddd ymm0, ymm1, ymm2": { @@ -47,6 +119,30 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x02 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "addp z0.s, p7/m, z0.s, z5.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vphaddsw xmm0, xmm1, xmm2": { @@ -54,6 +150,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x03 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uzp1 v6.8h, v4.8h, v5.8h", + "uzp2 v4.8h, v4.8h, v5.8h", + "sqadd v4.8h, v6.8h, v4.8h", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphaddsw ymm0, ymm1, ymm2": { @@ -61,6 +166,28 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x03 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uzp1 z6.h, z4.h, z5.h", + "uzp2 z4.h, z4.h, z5.h", + "sqadd z4.h, z6.h, z4.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpmaddubsw xmm0, xmm1, xmm2": { @@ -68,6 +195,26 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x04 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uxtl v6.8h, v4.8b", + "uxtl2 v4.8h, v4.16b", + "sxtl v7.8h, v5.8b", + "sxtl2 v5.8h, v5.16b", + "smull v8.4s, v6.4h, v7.4h", + "smull2 v6.4s, v6.8h, v7.8h", + "smull v7.4s, v4.4h, v5.4h", + "smull2 v4.4s, v4.8h, v5.8h", + "addp v5.4s, v8.4s, v6.4s", + "addp v4.4s, v7.4s, v4.4s", + "sqxtn v5.4h, v5.4s", + "mov v0.16b, v5.16b", + "sqxtn2 v0.8h, v4.4s", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaddubsw ymm0, ymm1, ymm2": { @@ -75,6 +222,43 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x04 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uunpklo z6.h, z4.b", + "uunpkhi z4.h, z4.b", + "sunpklo z7.h, z5.b", + "sunpkhi z5.h, z5.b", + "smullb z0.s, z6.h, z7.h", + "smullt z1.s, z6.h, z7.h", + "zip1 z8.s, z0.s, z1.s", + "smullb z0.s, z6.h, z7.h", + "smullt z1.s, z6.h, z7.h", + "zip2 z6.s, z0.s, z1.s", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip1 z7.s, z0.s, z1.s", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip2 z4.s, z0.s, z1.s", + "movprfx z0, z8", + "addp z0.s, p7/m, z0.s, z6.s", + "uzp1 z5.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z5.d, p6, z5.d, z1.d", + "movprfx z0, z7", + "addp z0.s, p7/m, z0.s, z4.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "sqxtnb z5.h, z5.s", + "uzp1 z5.h, z5.h, z5.h", + "sqxtnb z1.h, z4.s", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z5", + "splice z4.h, p6, z4.h, z1.h", + "mov z16.d, p7/m, z4.d" ] }, "vphsubw xmm0, xmm1, xmm2": { @@ -82,6 +266,22 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x05 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "neg v6.8h, v4.8h", + "neg v7.8h, v5.8h", + "uzp1 v4.8h, v4.8h, v4.8h", + "uzp1 v5.8h, v5.8h, v5.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "uzp2 v7.8h, v7.8h, v7.8h", + "zip1 v4.8h, v4.8h, v6.8h", + "zip1 v5.8h, v5.8h, v7.8h", + "addp v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphsubw ymm0, ymm1, ymm2": { @@ -89,6 +289,38 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "neg z6.h, p7/m, z4.h", + "neg z7.h, p7/m, z5.h", + "uzp1 z4.h, z4.h, z4.h", + "uzp1 z5.h, z5.h, z5.h", + "uzp2 z6.h, z6.h, z6.h", + "uzp2 z7.h, z7.h, z7.h", + "zip1 z4.h, z4.h, z6.h", + "zip1 z5.h, z5.h, z7.h", + "movprfx z0, z4", + "addp z0.h, p7/m, z0.h, z5.h", + "uzp1 z4.h, z0.h, z0.h", + "uzp2 z1.h, z0.h, z0.h", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vphsubd xmm0, xmm1, xmm2": { @@ -96,6 +328,22 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x06 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "neg v6.4s, v4.4s", + "neg v7.4s, v5.4s", + "uzp1 v4.4s, v4.4s, v4.4s", + "uzp1 v5.4s, v5.4s, v5.4s", + "uzp2 v6.4s, v6.4s, v6.4s", + "uzp2 v7.4s, v7.4s, v7.4s", + "zip1 v4.4s, v4.4s, v6.4s", + "zip1 v5.4s, v5.4s, v7.4s", + "addp v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphsubd ymm0, ymm1, ymm2": { @@ -103,6 +351,38 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "neg z6.s, p7/m, z4.s", + "neg z7.s, p7/m, z5.s", + "uzp1 z4.s, z4.s, z4.s", + "uzp1 z5.s, z5.s, z5.s", + "uzp2 z6.s, z6.s, z6.s", + "uzp2 z7.s, z7.s, z7.s", + "zip1 z4.s, z4.s, z6.s", + "zip1 z5.s, z5.s, z7.s", + "movprfx z0, z4", + "addp z0.s, p7/m, z0.s, z5.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vphsubsw xmm0, xmm1, xmm2": { @@ -110,6 +390,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x07 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uzp1 v6.8h, v4.8h, v5.8h", + "uzp2 v4.8h, v4.8h, v5.8h", + "sqsub v4.8h, v6.8h, v4.8h", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vphsubsw ymm0, ymm1, ymm2": { @@ -117,6 +406,28 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x07 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "uzp1 z6.h, z4.h, z5.h", + "uzp2 z4.h, z4.h, z5.h", + "sqsub z4.h, z6.h, z4.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpsignb xmm0, xmm1, xmm2": { @@ -124,6 +435,23 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "neg v7.16b, v4.16b", + "cmlt v8.16b, v5.16b, #0", + "cmeq v9.16b, v5.16b, #0", + "cmgt v5.16b, v5.16b, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v5.16b, v4.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsignb ymm0, ymm1, ymm2": { @@ -131,6 +459,32 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "neg z7.b, p7/m, z4.b", + "mov z0.d, #0", + "cmplt p0.b, p7/z, z5.b, #0", + "not z0.b, p0/m, z5.b", + "orr z0.b, p0/m, z0.b, z5.b", + "mov z8.d, z0.d", + "mov z0.d, #0", + "cmpeq p0.b, p7/z, z5.b, #0", + "not z0.b, p0/m, z5.b", + "mov z9.d, z0.d", + "mov z0.d, #0", + "cmpgt p0.b, p7/z, z5.b, #0", + "not z0.b, p0/m, z5.b", + "orr z0.b, p0/m, z0.b, z5.b", + "mov z5.d, z0.d", + "and z7.d, z8.d, z7.d", + "and z6.d, z9.d, z6.d", + "and z4.d, z5.d, z4.d", + "orr z5.d, z7.d, z6.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsignw xmm0, xmm1, xmm2": { @@ -138,6 +492,23 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "neg v7.8h, v4.8h", + "cmlt v8.8h, v5.8h, #0", + "cmeq v9.8h, v5.8h, #0", + "cmgt v5.8h, v5.8h, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v5.16b, v4.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsignw ymm0, ymm1, ymm2": { @@ -145,6 +516,32 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "neg z7.h, p7/m, z4.h", + "mov z0.d, #0", + "cmplt p0.h, p7/z, z5.h, #0", + "not z0.h, p0/m, z5.h", + "orr z0.h, p0/m, z0.h, z5.h", + "mov z8.d, z0.d", + "mov z0.d, #0", + "cmpeq p0.h, p7/z, z5.h, #0", + "not z0.h, p0/m, z5.h", + "mov z9.d, z0.d", + "mov z0.d, #0", + "cmpgt p0.h, p7/z, z5.h, #0", + "not z0.h, p0/m, z5.h", + "orr z0.h, p0/m, z0.h, z5.h", + "mov z5.d, z0.d", + "and z7.d, z8.d, z7.d", + "and z6.d, z9.d, z6.d", + "and z4.d, z5.d, z4.d", + "orr z5.d, z7.d, z6.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsignd xmm0, xmm1, xmm2": { @@ -152,6 +549,23 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "neg v7.4s, v4.4s", + "cmlt v8.4s, v5.4s, #0", + "cmeq v9.4s, v5.4s, #0", + "cmgt v5.4s, v5.4s, #0", + "and v7.16b, v8.16b, v7.16b", + "and v6.16b, v9.16b, v6.16b", + "and v4.16b, v5.16b, v4.16b", + "orr v5.16b, v7.16b, v6.16b", + "orr v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsignd ymm0, ymm1, ymm2": { @@ -159,6 +573,32 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0a 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "neg z7.s, p7/m, z4.s", + "mov z0.d, #0", + "cmplt p0.s, p7/z, z5.s, #0", + "not z0.s, p0/m, z5.s", + "orr z0.s, p0/m, z0.s, z5.s", + "mov z8.d, z0.d", + "mov z0.d, #0", + "cmpeq p0.s, p7/z, z5.s, #0", + "not z0.s, p0/m, z5.s", + "mov z9.d, z0.d", + "mov z0.d, #0", + "cmpgt p0.s, p7/z, z5.s, #0", + "not z0.s, p0/m, z5.s", + "orr z0.s, p0/m, z0.s, z5.s", + "mov z5.d, z0.d", + "and z7.d, z8.d, z7.d", + "and z6.d, z9.d, z6.d", + "and z4.d, z5.d, z4.d", + "orr z5.d, z7.d, z6.d", + "orr z4.d, z4.d, z5.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhrsw xmm0, xmm1, xmm2": { @@ -166,6 +606,24 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smull v6.4s, v4.4h, v5.4h", + "smull2 v4.4s, v4.8h, v5.8h", + "sshr v5.4s, v6.4s, #14", + "sshr v4.4s, v4.4s, #14", + "movi v6.4s, #0x1, lsl #0", + "add v5.4s, v5.4s, v6.4s", + "add v4.4s, v4.4s, v6.4s", + "shrn v5.4h, v5.4s, #1", + "mov v0.16b, v5.16b", + "shrn2 v0.8h, v4.4s, #1", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmulhrsw ymm0, ymm1, ymm2": { @@ -173,6 +631,30 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip1 z6.s, z0.s, z1.s", + "smullb z0.s, z4.h, z5.h", + "smullt z1.s, z4.h, z5.h", + "zip2 z4.s, z0.s, z1.s", + "movprfx z5, z6", + "asr z5.s, p7/m, z5.s, #14", + "movprfx z4, z4", + "asr z4.s, p7/m, z4.s, #14", + "mov z6.s, #1", + "add z5.s, z5.s, z6.s", + "add z4.s, z4.s, z6.s", + "shrnb z5.h, z5.s, #1", + "uzp1 z5.h, z5.h, z5.h", + "shrnb z1.h, z4.s, #1", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z5", + "splice z4.h, p6, z4.h, z1.h", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps xmm0, xmm1, xmm2": { @@ -180,6 +662,22 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.4s, #0x3, lsl #0", + "and v5.16b, v5.16b, v6.16b", + "trn1 v5.16b, v5.16b, v5.16b", + "trn1 v5.8h, v5.8h, v5.8h", + "shl v5.16b, v5.16b, #2", + "mov w20, #0x100", + "movk w20, #0x302, lsl #16", + "dup v6.4s, w20", + "add v5.16b, v6.16b, v5.16b", + "tbl v4.16b, {v4.16b}, v5.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps ymm0, ymm1, ymm2": { @@ -187,6 +685,32 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.s, #3", + "and z5.d, z5.d, z6.d", + "trn1 z5.b, z5.b, z5.b", + "trn1 z5.h, z5.h, z5.h", + "movprfx z5, z5", + "lsl z5.b, p7/m, z5.b, #2", + "mov w20, #0x100", + "movk w20, #0x302, lsl #16", + "mov z6.s, w20", + "mov z7.d, #0", + "mov z8.b, #16", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q8", + "mov z7.d, z7.d", + "mov z7.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "add z6.b, z6.b, z7.b", + "add z5.b, z6.b, z5.b", + "tbl z4.b, {z4.b}, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd xmm0, xmm1, xmm2": { @@ -194,6 +718,27 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ushr v5.2d, v5.2d, #1", + "orr w0, wzr, #0x1", + "dup v6.2d, x0", + "and v5.16b, v5.16b, v6.16b", + "trn1 v5.16b, v5.16b, v5.16b", + "trn1 v5.8h, v5.8h, v5.8h", + "trn1 v5.4s, v5.4s, v5.4s", + "shl v5.16b, v5.16b, #3", + "mov x20, #0x100", + "movk x20, #0x302, lsl #16", + "movk x20, #0x504, lsl #32", + "movk x20, #0x706, lsl #48", + "dup v6.2d, x20", + "add v5.16b, v6.16b, v5.16b", + "tbl v4.16b, {v4.16b}, v5.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, ymm2": { @@ -201,6 +746,37 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z5, z5", + "lsr z5.d, p7/m, z5.d, #1", + "mov z6.d, #1", + "and z5.d, z5.d, z6.d", + "trn1 z5.b, z5.b, z5.b", + "trn1 z5.h, z5.h, z5.h", + "trn1 z5.s, z5.s, z5.s", + "movprfx z5, z5", + "lsl z5.b, p7/m, z5.b, #3", + "mov x20, #0x100", + "movk x20, #0x302, lsl #16", + "movk x20, #0x504, lsl #32", + "movk x20, #0x706, lsl #48", + "mov z6.d, x20", + "mov z7.d, #0", + "mov z8.b, #16", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q8", + "mov z7.d, z7.d", + "mov z7.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "add z6.b, z6.b, z7.b", + "add z5.b, z6.b, z5.b", + "tbl z4.b, {z4.b}, z5.b", + "mov z16.d, p7/m, z4.d" ] }, "vtestps xmm0, xmm1": { @@ -208,6 +784,37 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr w20, wzr, #0x80000000", + "dup v6.4s, w20", + "and v7.16b, v5.16b, v4.16b", + "bic v4.16b, v5.16b, v4.16b", + "and v5.16b, v7.16b, v6.16b", + "and v4.16b, v4.16b, v6.16b", + "cnt v5.16b, v5.16b", + "cnt v4.16b, v4.16b", + "addv h5, v5.8h", + "addv h4, v4.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vtestps ymm0, ymm1": { @@ -215,6 +822,45 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr w20, wzr, #0x80000000", + "mov z6.s, w20", + "and z7.d, z5.d, z4.d", + "bic z4.d, z5.d, z4.d", + "and z5.d, z7.d, z6.d", + "and z4.d, z4.d, z6.d", + "cnt z5.b, p7/m, z5.b", + "cnt z4.b, p7/m, z4.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z5.d", + "addv h1, v5.8h", + "addv h0, v0.8h", + "add v5.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "addv h1, v4.8h", + "addv h0, v0.8h", + "add v4.8h, v0.8h, v1.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vtestpd xmm0, xmm1": { @@ -222,6 +868,37 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr x20, xzr, #0x8000000000000000", + "dup v6.2d, x20", + "and v7.16b, v5.16b, v4.16b", + "bic v4.16b, v5.16b, v4.16b", + "and v5.16b, v7.16b, v6.16b", + "and v4.16b, v4.16b, v6.16b", + "cnt v5.16b, v5.16b", + "cnt v4.16b, v4.16b", + "addv h5, v5.8h", + "addv h4, v4.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vtestpd ymm0, ymm1": { @@ -229,6 +906,45 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "orr x20, xzr, #0x8000000000000000", + "mov z6.d, x20", + "and z7.d, z5.d, z4.d", + "bic z4.d, z5.d, z4.d", + "and z5.d, z7.d, z6.d", + "and z4.d, z4.d, z6.d", + "cnt z5.b, p7/m, z5.b", + "cnt z4.b, p7/m, z4.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z5.d", + "addv h1, v5.8h", + "addv h0, v0.8h", + "add v5.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "addv h1, v4.8h", + "addv h0, v0.8h", + "add v4.8h, v0.8h, v1.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vcvtph2ps xmm0, xmm1": { @@ -252,6 +968,22 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x16 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.s, #7", + "and z4.d, z4.d, z6.d", + "trn1 z4.b, z4.b, z4.b", + "trn1 z4.h, z4.h, z4.h", + "movprfx z4, z4", + "lsl z4.b, p7/m, z4.b, #2", + "mov w20, #0x100", + "movk w20, #0x302, lsl #16", + "mov z6.s, w20", + "add z4.b, z4.b, z6.b", + "tbl z4.b, {z5.b}, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vptest xmm0, xmm1": { @@ -259,6 +991,33 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and v6.16b, v4.16b, v5.16b", + "bic v4.16b, v5.16b, v4.16b", + "cnt v5.16b, v6.16b", + "cnt v4.16b, v4.16b", + "addv h5, v5.8h", + "addv h4, v4.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vptest ymm0, ymm1": { @@ -266,6 +1025,41 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x16 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "and z6.d, z4.d, z5.d", + "bic z4.d, z5.d, z4.d", + "cnt z5.b, p7/m, z6.b", + "cnt z4.b, p7/m, z4.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z5.d", + "addv h1, v5.8h", + "addv h0, v0.8h", + "add v5.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z4.d", + "addv h1, v4.8h", + "addv h0, v0.8h", + "add v4.8h, v0.8h, v1.8h", + "umov w20, v5.h[0]", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "bfi w20, w21, #29, #1", + "strb w22, [x28, #708]", + "bfi w20, w22, #31, #1", + "bfi w20, w22, #28, #1", + "strb w22, [x28, #706]", + "str w20, [x28, #728]" ] }, "vbroadcastss xmm0, [rax]": { @@ -273,6 +1067,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x18 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "dup v4.4s, v4.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vbroadcastss ymm0, [rax]": { @@ -280,6 +1081,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x18 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "mov z4.s, s4", + "mov z16.d, p7/m, z4.d" ] }, "vbroadcastsd ymm0, [rax]": { @@ -287,6 +1093,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x19 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov z4.d, d4", + "mov z16.d, p7/m, z4.d" ] }, "vbroadcastf128 ymm0, [rax]": { @@ -294,6 +1105,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1a 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z4.q, q4", + "mov z16.d, p7/m, z4.d" ] }, "vpabsb xmm0, xmm1": { @@ -301,6 +1117,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpabsb ymm0, ymm1": { @@ -308,6 +1130,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs z4.b, p7/m, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vpabsw xmm0, xmm1": { @@ -315,6 +1142,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs v4.8h, v4.8h", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpabsw ymm0, ymm1": { @@ -322,6 +1155,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs z4.h, p7/m, z4.h", + "mov z16.d, p7/m, z4.d" ] }, "vpabsd xmm0, xmm1": { @@ -329,6 +1167,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpabsd ymm0, ymm1": { @@ -336,6 +1180,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x1e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "abs z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbw xmm0, xmm1": { @@ -343,6 +1192,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x20 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.8h, v4.8b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbw ymm0, xmm1": { @@ -350,6 +1206,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x20 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.h, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbd xmm0, xmm1": { @@ -357,6 +1218,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x21 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.8h, v4.8b", + "sxtl v4.4s, v4.4h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbd ymm0, xmm1": { @@ -364,6 +1233,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x21 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.h, z4.b", + "sunpklo z4.s, z4.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbq xmm0, xmm1": { @@ -371,6 +1246,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x22 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.8h, v4.8b", + "sxtl v4.4s, v4.4h", + "sxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxbq ymm0, xmm1": { @@ -378,6 +1262,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x22 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.h, z4.b", + "sunpklo z4.s, z4.h", + "sunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxwd xmm0, xmm1": { @@ -385,6 +1276,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x23 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.4s, v4.4h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxwd ymm0, xmm1": { @@ -392,6 +1290,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x23 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.s, z4.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxwq xmm0, xmm1": { @@ -399,6 +1302,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x24 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.4s, v4.4h", + "sxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxwq ymm0, xmm1": { @@ -406,6 +1317,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x24 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.s, z4.h", + "sunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxdq xmm0, xmm1": { @@ -413,6 +1330,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x25 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovsxdq ymm0, xmm1": { @@ -420,6 +1344,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x25 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmuldq xmm0, xmm1, xmm2": { @@ -427,6 +1356,16 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x28 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.s[1], v4.s[2]", + "mov v5.s[1], v5.s[2]", + "smull v4.2d, v4.2s, v5.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmuldq ymm0, ymm1, ymm2": { @@ -434,6 +1373,56 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x28 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z6.d, z4.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[2]", + "mov z7.d, z5.d", + "mov z7.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z6.d, z7.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[6]", + "mov z5.d, z6.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "smullb z0.d, z4.s, z5.s", + "smullt z1.d, z4.s, z5.s", + "zip1 z4.d, z0.d, z1.d", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqq xmm0, xmm1, xmm2": { @@ -441,6 +1430,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x29 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmeq v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpeqq ymm0, ymm1, ymm2": { @@ -448,6 +1445,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x29 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpeq p0.d, p7/z, z4.d, z5.d", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vmovntdqa xmm0, [rax]": { @@ -455,6 +1461,10 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2a 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmovntdqa ymm0, [rax]": { @@ -462,6 +1472,10 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2a 256-bit" + ], + "ExpectedArm64ASM": [ + "ld1b {z4.b}, p7/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vpackusdw xmm0, xmm1, xmm2": { @@ -469,6 +1483,17 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtun v4.4h, v4.4s", + "mov v0.16b, v4.16b", + "sqxtun2 v0.8h, v5.4s", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpackusdw ymm0, ymm1, ymm2": { @@ -476,6 +1501,31 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "sqxtunb z4.h, z4.s", + "uzp1 z4.h, z4.h, z4.h", + "sqxtunb z1.h, z5.s", + "uzp1 z1.h, z1.h, z1.h", + "movprfx z4, z4", + "splice z4.h, p6, z4.h, z1.h", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z4.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovps xmm0, xmm1, [rax]": { @@ -483,6 +1533,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.s, p6/z, z4.s, #0", + "ld1w {z4.s}, p0/z, [x4]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovps ymm0, ymm1, [rax]": { @@ -490,6 +1547,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.s, p7/z, z4.s, #0", + "ld1w {z4.s}, p0/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovpd xmm0, xmm1, [rax]": { @@ -497,6 +1560,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.d, p6/z, z4.d, #0", + "ld1d {z4.d}, p0/z, [x4]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovpd ymm0, ymm1, [rax]": { @@ -504,6 +1574,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.d, p7/z, z4.d, #0", + "ld1d {z4.d}, p0/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vmaskmovps [rax], xmm0, xmm1": { @@ -511,6 +1587,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.s, p6/z, z4.s, #0", + "st1w {z5.s}, p0, [x4]" ] }, "vmaskmovps [rax], ymm0, ymm1": { @@ -518,6 +1600,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.s, p7/z, z4.s, #0", + "st1w {z5.s}, p0, [x4]" ] }, "vmaskmovpd [rax], xmm0, xmm1": { @@ -525,6 +1613,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.d, p6/z, z4.d, #0", + "st1d {z5.d}, p0, [x4]" ] }, "vmaskmovpd [rax], ymm0, ymm1": { @@ -532,6 +1626,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x2f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.d, p7/z, z4.d, #0", + "st1d {z5.d}, p0, [x4]" ] }, "vpmovzxbw xmm0, xmm1": { @@ -539,6 +1639,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x30 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.8h, v4.8b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxbw ymm0, xmm1": { @@ -546,6 +1653,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x30 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.h, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxbd xmm0, xmm1": { @@ -553,6 +1665,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x31 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.8h, v4.8b", + "uxtl v4.4s, v4.4h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxbd ymm0, xmm1": { @@ -560,6 +1680,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x31 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.h, z4.b", + "uunpklo z4.s, z4.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxbq xmm0, xmm1": { @@ -567,6 +1693,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x32 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.8h, v4.8b", + "uxtl v4.4s, v4.4h", + "uxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxbq ymm0, xmm1": { @@ -574,6 +1709,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x32 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.h, z4.b", + "uunpklo z4.s, z4.h", + "uunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxwd xmm0, xmm1": { @@ -581,6 +1723,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x33 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.4s, v4.4h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxwd ymm0, xmm1": { @@ -588,6 +1737,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x33 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.s, z4.h", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxwq xmm0, xmm1": { @@ -595,6 +1749,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x34 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.4s, v4.4h", + "uxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxwq ymm0, xmm1": { @@ -602,6 +1764,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x34 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.s, z4.h", + "uunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxdq xmm0, xmm1": { @@ -609,6 +1777,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x35 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uxtl v4.2d, v4.2s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmovzxdq ymm0, xmm1": { @@ -616,6 +1791,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x35 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uunpklo z4.d, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vpermd ymm0, ymm1, ymm2": { @@ -623,6 +1803,22 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x36 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.s, #7", + "and z4.d, z4.d, z6.d", + "trn1 z4.b, z4.b, z4.b", + "trn1 z4.h, z4.h, z4.h", + "movprfx z4, z4", + "lsl z4.b, p7/m, z4.b, #2", + "mov w20, #0x100", + "movk w20, #0x302, lsl #16", + "mov z6.s, w20", + "add z4.b, z4.b, z6.b", + "tbl z4.b, {z5.b}, z4.b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtq xmm0, xmm1, xmm2": { @@ -630,6 +1826,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x37 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmgt v4.2d, v4.2d, v5.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpcmpgtq ymm0, ymm1, ymm2": { @@ -637,6 +1841,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x37 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "cmpgt p0.d, p7/z, z4.d, z5.d", + "not z0.d, p0/m, z4.d", + "movprfx z4.d, p0/z, z4.d", + "orr z4.d, p0/m, z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpminsb xmm0, xmm1, xmm2": { @@ -644,6 +1857,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x38 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smin v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminsb ymm0, ymm1, ymm2": { @@ -651,6 +1872,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x38 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smin z0.b, p7/m, z0.b, z5.b", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpminsd xmm0, xmm1, xmm2": { @@ -658,6 +1887,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x39 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smin v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminsd ymm0, ymm1, ymm2": { @@ -665,6 +1902,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x39 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smin z0.s, p7/m, z0.s, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpminuw xmm0, xmm1, xmm2": { @@ -672,6 +1917,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umin v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminuw ymm0, ymm1, ymm2": { @@ -679,6 +1932,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3a 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umin z0.h, p7/m, z0.h, z5.h", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpminud xmm0, xmm1, xmm2": { @@ -686,6 +1947,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umin v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpminud ymm0, ymm1, ymm2": { @@ -693,6 +1962,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umin z0.s, p7/m, z0.s, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsb xmm0, xmm1, xmm2": { @@ -700,6 +1977,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smax v4.16b, v4.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsb ymm0, ymm1, ymm2": { @@ -707,6 +1992,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smax z0.b, p7/m, z0.b, z5.b", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsd xmm0, xmm1, xmm2": { @@ -714,6 +2007,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "smax v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxsd ymm0, ymm1, ymm2": { @@ -721,6 +2022,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "smax z0.s, p7/m, z0.s, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxuw xmm0, xmm1, xmm2": { @@ -728,6 +2037,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umax v4.8h, v4.8h, v5.8h", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxuw ymm0, ymm1, ymm2": { @@ -735,6 +2052,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umax z0.h, p7/m, z0.h, z5.h", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxud xmm0, xmm1, xmm2": { @@ -742,6 +2067,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "umax v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaxud ymm0, ymm1, ymm2": { @@ -749,6 +2082,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x3f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movprfx z0, z4", + "umax z0.s, p7/m, z0.s, z5.s", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpmulld xmm0, xmm1, xmm2": { @@ -756,6 +2097,14 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mul v4.4s, v4.4s, v5.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmulld ymm0, ymm1, ymm2": { @@ -763,6 +2112,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x40 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mul z4.s, z4.s, z5.s", + "mov z16.d, p7/m, z4.d" ] }, "vphminposuw xmm0, xmm1": { @@ -770,6 +2125,49 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x41 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "uminv h5, v4.8h", + "mov w20, #0x0", + "orr w20, wzr, #0x1", + "orr w21, wzr, #0x2", + "orr w22, wzr, #0x3", + "orr w23, wzr, #0x4", + "mov w24, #0x5", + "orr w25, wzr, #0x6", + "orr w26, wzr, #0x7", + "umov w27, v5.h[0]", + "umov w30, v4.h[7]", + "cmp w30, w27", + "csel x26, x26, x26, eq", + "umov w30, v4.h[6]", + "cmp w30, w27", + "csel x25, x25, x26, eq", + "umov w26, v4.h[5]", + "cmp w26, w27", + "csel x24, x24, x25, eq", + "umov w25, v4.h[4]", + "cmp w25, w27", + "csel x23, x23, x24, eq", + "umov w24, v4.h[3]", + "cmp w24, w27", + "csel x22, x22, x23, eq", + "umov w23, v4.h[2]", + "cmp w23, w27", + "csel x21, x21, x22, eq", + "umov w22, v4.h[1]", + "cmp w22, w27", + "csel x20, x20, x21, eq", + "umov w21, v4.h[0]", + "mov w22, #0x0", + "cmp w21, w27", + "csel x20, x22, x20, eq", + "mov v4.16b, v5.16b", + "mov v4.h[1], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlvd xmm0, xmm1, xmm2": { @@ -777,6 +2175,17 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x45 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.4s, #0x20, lsl #0", + "umin v0.4s, v0.4s, v5.4s", + "neg v0.4s, v0.4s", + "ushl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlvd ymm0, ymm1, ymm2": { @@ -784,6 +2193,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x45 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z1.s, #32", + "umin z1.s, p7/m, z1.s, z5.s", + "movprfx z4, z4", + "lsr z4.s, p7/m, z4.s, z1.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlvq xmm0, xmm1, xmm2": { @@ -791,6 +2209,19 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x45 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v0.2d, x0", + "cmhi v1.2d, v5.2d, v0.2d", + "bif v0.16b, v5.16b, v1.16b", + "neg v0.2d, v0.2d", + "ushl v4.2d, v4.2d, v0.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlvq ymm0, ymm1, ymm2": { @@ -798,6 +2229,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x45 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z1.d, #64", + "umin z1.d, p7/m, z1.d, z5.d", + "movprfx z4, z4", + "lsr z4.d, p7/m, z4.d, z1.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsravd xmm0, xmm1, xmm2": { @@ -805,6 +2245,17 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x46 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.4s, #0x1f, lsl #0", + "umin v0.4s, v0.4s, v5.4s", + "neg v0.4s, v0.4s", + "sshl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsravd ymm0, ymm1, ymm2": { @@ -812,6 +2263,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z0.s, #31", + "umin z0.s, p7/m, z0.s, z5.s", + "movprfx z4, z4", + "asr z4.s, p7/m, z4.s, z0.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsllvd xmm0, xmm1, xmm2": { @@ -819,6 +2279,16 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x47 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.4s, #0x20, lsl #0", + "umin v0.4s, v0.4s, v5.4s", + "ushl v4.4s, v4.4s, v0.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllvd ymm0, ymm1, ymm2": { @@ -826,6 +2296,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x47 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z1.s, #32", + "umin z1.s, p7/m, z1.s, z5.s", + "movprfx z4, z4", + "lsl z4.s, p7/m, z4.s, z1.s", + "mov z16.d, p7/m, z4.d" ] }, "vpsllvq xmm0, xmm1, xmm2": { @@ -833,6 +2312,18 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x47 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "orr w0, wzr, #0x40", + "dup v0.2d, x0", + "cmhi v1.2d, v5.2d, v0.2d", + "bif v0.16b, v5.16b, v1.16b", + "ushl v4.2d, v4.2d, v0.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllvq ymm0, ymm1, ymm2": { @@ -840,6 +2331,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x47 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z1.d, #64", + "umin z1.d, p7/m, z1.d, z5.d", + "movprfx z4, z4", + "lsl z4.d, p7/m, z4.d, z1.d", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastd xmm0, xmm1": { @@ -847,6 +2347,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "dup v4.4s, v4.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastd xmm0, [rax]": { @@ -854,6 +2361,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x58 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "dup v4.4s, v4.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastd ymm0, xmm1": { @@ -861,6 +2375,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x58 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.s, s4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastd ymm0, [rax]": { @@ -868,6 +2387,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x58 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr s4, [x4]", + "mov z4.s, s4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastq xmm0, xmm1": { @@ -875,6 +2399,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "dup v4.2d, v4.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastq xmm0, [rax]": { @@ -882,6 +2413,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x59 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "dup v4.2d, v4.d[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastq ymm0, xmm1": { @@ -889,6 +2427,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x59 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.d, d4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastq ymm0, [rax]": { @@ -897,13 +2440,23 @@ "Comment": [ "Map 2 0b01 0x59 256-bit" ], - "ExpectedInstructionCount": 3 + "ExpectedInstructionCount": 3, + "ExpectedArm64ASM": [ + "ldr d4, [x4]", + "mov z4.d, d4", + "mov z16.d, p7/m, z4.d" + ] }, "vbroadcasti128 ymm0, [rax]": { "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "Map 2 0b01 0x5a 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr q4, [x4]", + "mov z4.q, q4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastb xmm0, xmm1": { @@ -911,6 +2464,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x78 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "dup v4.16b, v4.b[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastb xmm0, [rax]": { @@ -918,6 +2478,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x78 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr b4, [x4]", + "dup v4.16b, v4.b[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastb ymm0, xmm1": { @@ -925,6 +2492,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x78 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.b, b4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastb ymm0, [rax]": { @@ -933,13 +2505,25 @@ "Comment": [ "Map 2 0b01 0x78 256-bit" ], - "ExpectedInstructionCount": 3 + "ExpectedInstructionCount": 3, + "ExpectedArm64ASM": [ + "ldr b4, [x4]", + "mov z4.b, b4", + "mov z16.d, p7/m, z4.d" + ] }, "vpbroadcastw xmm0, xmm1": { "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x79 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "dup v4.8h, v4.h[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastw xmm0, [rax]": { @@ -947,6 +2531,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x79 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr h4, [x4]", + "dup v4.8h, v4.h[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastw ymm0, xmm1": { @@ -954,6 +2545,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x79 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.h, h4", + "mov z16.d, p7/m, z4.d" ] }, "vpbroadcastw ymm0, [rax]": { @@ -962,13 +2558,25 @@ "Comment": [ "Map 2 0b01 0x79 256-bit" ], - "ExpectedInstructionCount": 3 + "ExpectedInstructionCount": 3, + "ExpectedArm64ASM": [ + "ldr h4, [x4]", + "mov z4.h, h4", + "mov z16.d, p7/m, z4.d" + ] }, "vpmaskmovd xmm0, xmm1, [rax]": { "ExpectedInstructionCount": 5, "Optimal": "No", "Comment": [ "Map 2 0b01 0x8c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.s, p6/z, z4.s, #0", + "ld1w {z4.s}, p0/z, [x4]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaskmovd ymm0, ymm1, [rax]": { @@ -976,6 +2584,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.s, p7/z, z4.s, #0", + "ld1w {z4.s}, p0/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vpmaskmovq xmm0, xmm1, [rax]": { @@ -983,6 +2597,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.d, p6/z, z4.d, #0", + "ld1d {z4.d}, p0/z, [x4]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpmaskmovq ymm0, ymm1, [rax]": { @@ -990,6 +2611,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "cmplt p0.d, p7/z, z4.d, #0", + "ld1d {z4.d}, p0/z, [x4]", + "mov z16.d, p7/m, z4.d" ] }, "vpmaskmovd [rax], xmm0, xmm1": { @@ -997,6 +2624,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.s, p6/z, z4.s, #0", + "st1w {z5.s}, p0, [x4]" ] }, "vpmaskmovd [rax], ymm0, ymm1": { @@ -1004,6 +2637,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.s, p7/z, z4.s, #0", + "st1w {z5.s}, p0, [x4]" ] }, "vpmaskmovq [rax], xmm0, xmm1": { @@ -1011,6 +2650,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.d, p6/z, z4.d, #0", + "st1d {z5.d}, p0, [x4]" ] }, "vpmaskmovq [rax], ymm0, ymm1": { @@ -1018,6 +2663,12 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0x8e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "cmplt p0.d, p7/z, z4.d, #0", + "st1d {z5.d}, p0, [x4]" ] }, "vpgatherdd xmm0, [xmm1*1 + rax], xmm2": { @@ -2305,6 +3956,13 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xdb 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "unimplemented (Unimplemented)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaesenc xmm0, xmm1, xmm2": { @@ -2312,6 +3970,18 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xdc 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "unimplemented (Unimplemented)", + "eor v4.16b, v0.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaesenc ymm0, ymm1, ymm2": { @@ -2327,6 +3997,17 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xdd 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "eor v4.16b, v0.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaesenclast ymm0, ymm1, ymm2": { @@ -2342,6 +4023,18 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xde 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "unimplemented (Unimplemented)", + "eor v4.16b, v0.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaesdec ymm0, ymm1, ymm2": { @@ -2357,6 +4050,17 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xdf 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "eor v4.16b, v0.16b, v5.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaesdeclast ymm0, ymm1, ymm2": { @@ -2372,6 +4076,18 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf2 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "bic w4, w21, w20", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "andn rax, rbx, rcx": { @@ -2379,6 +4095,16 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf2 64-bit" + ], + "ExpectedArm64ASM": [ + "bic x4, x5, x7", + "mov w20, #0x0", + "strb w20, [x28, #708]", + "eor x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" ] }, "bzhi eax, ebx, ecx": { @@ -2386,6 +4112,31 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf5 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "and x21, x21, #0xff", + "mov w22, #0xffff", + "movk w22, #0xffff, lsl #16", + "lsl w22, w22, w21", + "bic w22, w20, w22", + "cmp x21, #0x1f (31)", + "csel w4, w20, w22, hi", + "mov w20, #0x0", + "ldr w22, [x28, #728]", + "bfi w22, w20, #28, #1", + "strb w20, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "mov w0, w22", + "bfi w0, w20, #30, #1", + "lsr w20, w0, #0", + "cmp x21, #0x1f (31)", + "cset x21, hi", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" ] }, "bzhi rax, rbx, rcx": { @@ -2393,6 +4144,30 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf5 64-bit" + ], + "ExpectedArm64ASM": [ + "and x20, x5, #0xff", + "mov x21, #0xffffffffffffffff", + "lsl x21, x21, x20", + "bic x21, x7, x21", + "cmp x20, #0x3f (63)", + "csel x4, x7, x21, hi", + "mov w21, #0x0", + "ldr w22, [x28, #728]", + "bfi w22, w21, #28, #1", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x4, #0x0 (0)", + "cset x21, eq", + "mov w0, w22", + "bfi w0, w21, #30, #1", + "lsr w21, w0, #0", + "cmp x20, #0x3f (63)", + "cset x20, hi", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "pext eax, ebx, ecx": { @@ -2400,6 +4175,27 @@ "Optimal": "No", "Comment": [ "Map 2 0b10 0xf5 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "cbz w21, #+0x40", + "mov w0, w21", + "mov w3, wzr", + "mov w21, wzr", + "rbit w1, w0", + "clz w1, w1", + "sub w2, w0, #0x1 (1)", + "ands w0, w2, w0", + "lsr w1, w20, w1", + "and w1, w1, #0x1", + "lsl w1, w1, w3", + "add w3, w3, #0x1 (1)", + "orr w21, w1, w21", + "b.ne #-0x24", + "mov w4, w21", + "b #+0x8", + "mov w4, wzr" ] }, "pext rax, rbx, rcx": { @@ -2407,6 +4203,27 @@ "Optimal": "No", "Comment": [ "Map 2 0b10 0xf5 64-bit" + ], + "ExpectedArm64ASM": [ + "cbz x5, #+0x48", + "mov x0, x5", + "mov x3, xzr", + "str x5, [x28, #16]", + "mov x5, xzr", + "rbit x1, x0", + "clz x1, x1", + "sub x2, x0, #0x1 (1)", + "ands x0, x2, x0", + "lsr x1, x7, x1", + "and x1, x1, #0x1", + "lsl x1, x1, x3", + "add x3, x3, #0x1 (1)", + "orr x5, x1, x5", + "b.ne #-0x24", + "mov x4, x5", + "ldr x5, [x28, #16]", + "b #+0x8", + "mov x4, xzr" ] }, "pdep eax, ebx, ecx": { @@ -2414,6 +4231,33 @@ "Optimal": "No", "Comment": [ "Map 2 0b11 0xf5 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "cbz w21, #+0x58", + "mov w3, wzr", + "stp x4, x5, [x28, #8]", + "str x6, [x28, #24]", + "mov w4, w20", + "mov w5, w21", + "mov w6, wzr", + "rbit w0, w5", + "clz w0, w0", + "lsr w1, w4, w3", + "and w1, w1, #0x1", + "sub w2, w5, #0x1 (1)", + "add w3, w3, #0x1 (1)", + "ands w5, w5, w2", + "lsl w0, w1, w0", + "orr w6, w6, w0", + "b.ne #-0x24", + "mov w3, w6", + "ldp x4, x5, [x28, #8]", + "ldr x6, [x28, #24]", + "mov w4, w3", + "b #+0x8", + "mov w4, wzr" ] }, "pdep rax, rbx, rcx": { @@ -2421,6 +4265,31 @@ "Optimal": "No", "Comment": [ "Map 2 0b11 0xf5 64-bit" + ], + "ExpectedArm64ASM": [ + "cbz x5, #+0x58", + "mov x3, xzr", + "stp x4, x5, [x28, #8]", + "str x6, [x28, #24]", + "mov x4, x7", + "mov x5, x5", + "mov x6, xzr", + "rbit x0, x5", + "clz x0, x0", + "lsr x1, x4, x3", + "and x1, x1, #0x1", + "sub x2, x5, #0x1 (1)", + "add x3, x3, #0x1 (1)", + "ands x5, x5, x2", + "lsl x0, x1, x0", + "orr x6, x6, x0", + "b.ne #-0x24", + "mov x3, x6", + "ldp x4, x5, [x28, #8]", + "ldr x6, [x28, #24]", + "mov x4, x3", + "b #+0x8", + "mov x4, xzr" ] }, "mulx eax, ebx, ecx": { @@ -2428,6 +4297,15 @@ "Optimal": "No", "Comment": [ "Map 2 0b11 0xf6 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x5, #0, #32", + "ubfx x21, x6, #0, #32", + "mul w7, w20, w21", + "ubfx x0, x20, #0, #32", + "ubfx x1, x21, #0, #32", + "mul x4, x0, x1", + "lsr x4, x4, #32" ] }, "mulx rax, rbx, rcx": { @@ -2435,6 +4313,10 @@ "Optimal": "Yes", "Comment": [ "Map 2 0b11 0xf6 64-bit" + ], + "ExpectedArm64ASM": [ + "mul x7, x5, x6", + "umulh x4, x5, x6" ] }, "bextr eax, ebx, ecx": { @@ -2442,6 +4324,28 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf7 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "orr w22, wzr, #0x1f", + "uxtb x23, w21", + "lsr w20, w20, w23", + "mov w24, #0x0", + "cmp w23, #0x1f (31)", + "csel w20, w20, w24, ls", + "ubfx x21, x21, #8, #8", + "cmp w21, #0x1f (31)", + "csel w21, w21, w22, ls", + "orr w22, wzr, #0x1", + "lsl w21, w22, w21", + "sub w21, w21, #0x1 (1)", + "and w4, w20, w21", + "strb w24, [x28, #706]", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" ] }, "bextr rax, rbx, rcx": { @@ -2449,6 +4353,26 @@ "Optimal": "No", "Comment": [ "Map 2 0b00 0xf7 64-bit" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x3f", + "uxtb x21, w5", + "lsr x22, x7, x21", + "mov w23, #0x0", + "cmp x21, #0x3f (63)", + "csel x21, x22, x23, ls", + "ubfx x22, x5, #8, #8", + "cmp x22, #0x3f (63)", + "csel x20, x22, x20, ls", + "orr w22, wzr, #0x1", + "lsl x20, x22, x20", + "sub x20, x20, #0x1 (1)", + "and x4, x21, x20", + "strb w23, [x28, #706]", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" ] }, "shlx eax, ebx, ecx": { @@ -2456,6 +4380,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b01 0xf7 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "lsl w4, w20, w21" ] }, "shlx rax, rbx, rcx": { @@ -2463,6 +4392,9 @@ "Optimal": "Yes", "Comment": [ "Map 2 0b01 0xf7 64-bit" + ], + "ExpectedArm64ASM": [ + "lsl x4, x7, x5" ] }, "sarx eax, ebx, ecx": { @@ -2470,6 +4402,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b10 0xf7 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "asr w4, w20, w21" ] }, "sarx rax, rbx, rcx": { @@ -2477,6 +4414,9 @@ "Optimal": "Yes", "Comment": [ "Map 2 0b10 0xf7 64-bit" + ], + "ExpectedArm64ASM": [ + "asr x4, x7, x5" ] }, "shrx eax, ebx, ecx": { @@ -2484,6 +4424,11 @@ "Optimal": "No", "Comment": [ "Map 2 0b11 0xf7 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ubfx x21, x5, #0, #32", + "lsr w4, w20, w21" ] }, "shrx rax, rbx, rcx": { @@ -2491,6 +4436,9 @@ "Optimal": "Yes", "Comment": [ "Map 2 0b11 0xf7 64-bit" + ], + "ExpectedArm64ASM": [ + "lsr x4, x7, x5" ] } } diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index d21c14ac4..f24e944a9 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -12,6 +12,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x00 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermq ymm0, ymm1, 01010101b": { @@ -19,6 +52,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x00 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermq ymm0, ymm1, 10101010b": { @@ -26,6 +92,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x00 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermq ymm0, ymm1, 11111111b": { @@ -33,6 +132,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x00 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermpd ymm0, ymm1, 00000000b": { @@ -40,6 +172,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x01 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermpd ymm0, ymm1, 01010101b": { @@ -47,6 +212,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x01 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermpd ymm0, ymm1, 10101010b": { @@ -54,6 +252,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x01 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermpd ymm0, ymm1, 11111111b": { @@ -61,6 +292,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x01 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0000b": { @@ -68,6 +332,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0001b": { @@ -75,6 +345,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[1]", + "mov v5.s[2], v4.s[2]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0010b": { @@ -82,6 +367,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v0.16b, v6.16b", + "mov v0.s[1], v5.s[1]", + "mov v5.16b, v0.16b", + "mov v5.s[2], v4.s[2]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0011b": { @@ -89,6 +389,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v0.16b, v6.16b", + "mov v0.s[1], v5.s[1]", + "mov v5.16b, v0.16b", + "mov v5.s[2], v4.s[2]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0100b": { @@ -96,6 +411,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v6.s[1], v4.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v5.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0101b": { @@ -103,6 +433,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v6.s[1], v4.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v5.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0110b": { @@ -110,6 +455,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v6.s[1], v5.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v5.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 0111b": { @@ -117,6 +477,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v6.s[1], v5.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v5.s[2]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1000b": { @@ -124,6 +499,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v6.s[1], v4.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v4.s[2]", + "mov v4.16b, v0.16b", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1001b": { @@ -131,6 +519,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v6.s[1], v4.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v4.s[2]", + "mov v4.16b, v0.16b", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1010b": { @@ -138,6 +539,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v6.s[1], v5.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v4.s[2]", + "mov v4.16b, v0.16b", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1011b": { @@ -145,6 +559,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v6.s[1], v5.s[1]", + "mov v0.16b, v6.16b", + "mov v0.s[2], v4.s[2]", + "mov v4.16b, v0.16b", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1100b": { @@ -152,6 +579,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v4.s[0]", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[2]", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1101b": { @@ -159,6 +599,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v6.s[0], v5.s[0]", + "mov v0.16b, v6.16b", + "mov v0.s[1], v4.s[1]", + "mov v4.16b, v0.16b", + "mov v4.s[2], v5.s[2]", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1110b": { @@ -166,6 +619,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.s[1], v5.s[1]", + "mov v4.s[2], v5.s[2]", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd xmm0, xmm1, 1111b": { @@ -173,6 +639,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd ymm0, ymm1, 00000000b": { @@ -180,6 +652,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd ymm0, ymm1, 01010101b": { @@ -187,6 +663,68 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[2]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[6]", + "mov z5.d, z6.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd ymm0, ymm1, 10101010b": { @@ -194,6 +732,68 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[1]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[3]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[5]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[7]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpblendd ymm0, ymm1, 11111111b": { @@ -201,6 +801,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x02 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps xmm0, xmm1, 00000000b": { @@ -208,6 +812,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.s[0], v4.s[0]", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps xmm0, xmm1, 01010101b": { @@ -215,6 +831,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.s[0], v4.s[1]", + "mov v5.s[1], v4.s[1]", + "mov v5.s[2], v4.s[1]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[1]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps xmm0, xmm1, 10101010b": { @@ -222,6 +850,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.s[0], v4.s[2]", + "mov v5.s[1], v4.s[2]", + "mov v5.s[2], v4.s[2]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[2]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps xmm0, xmm1, 11111111b": { @@ -229,6 +869,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.s[0], v4.s[3]", + "mov v5.s[1], v4.s[3]", + "mov v5.s[2], v4.s[3]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps ymm0, ymm1, 00000000b": { @@ -236,6 +888,67 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps ymm0, ymm1, 01010101b": { @@ -243,6 +956,67 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps ymm0, ymm1, 10101010b": { @@ -250,6 +1024,67 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpermilps ymm0, ymm1, 11111111b": { @@ -257,6 +1092,67 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x03 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[7]", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd xmm0, xmm1, 00b": { @@ -264,6 +1160,16 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.d[0], v4.d[0]", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd xmm0, xmm1, 01b": { @@ -271,6 +1177,16 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.d[0], v4.d[1]", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd xmm0, xmm1, 10b": { @@ -278,6 +1194,16 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.d[0], v4.d[0]", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[1]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd xmm0, xmm1, 11b": { @@ -285,6 +1211,16 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "mov v5.d[0], v4.d[1]", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[1]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0000b": { @@ -292,6 +1228,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0001b": { @@ -299,6 +1268,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0010b": { @@ -306,6 +1308,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0011b": { @@ -313,6 +1348,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0100b": { @@ -320,6 +1388,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0101b": { @@ -327,6 +1428,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0110b": { @@ -334,6 +1468,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 0111b": { @@ -341,6 +1508,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1000b": { @@ -348,6 +1548,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1001b": { @@ -355,6 +1588,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1010b": { @@ -362,6 +1628,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1011b": { @@ -369,6 +1668,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1100b": { @@ -376,6 +1708,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1101b": { @@ -383,6 +1748,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1110b": { @@ -390,6 +1788,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpermilpd ymm0, ymm1, 1111b": { @@ -397,6 +1828,39 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x05 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 000000b": { @@ -404,6 +1868,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 000001b": { @@ -411,6 +1894,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 000010b": { @@ -418,6 +1920,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 000011b": { @@ -425,6 +1947,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 010000b": { @@ -432,6 +1974,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 010001b": { @@ -439,6 +2000,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 010010b": { @@ -446,6 +2026,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 010011b": { @@ -453,6 +2053,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 100000b": { @@ -460,6 +2080,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 100001b": { @@ -467,6 +2107,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 100010b": { @@ -474,6 +2134,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 100011b": { @@ -481,6 +2160,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 110000b": { @@ -488,6 +2186,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 110001b": { @@ -495,6 +2213,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov z5.d, p7/m, z17.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 110010b": { @@ -502,6 +2240,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2f128 ymm0, ymm1, 110011b": { @@ -509,6 +2266,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x06 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vroundps xmm0, xmm1, 00000000b": { @@ -517,6 +2293,13 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundps xmm0, xmm1, 00000001b": { @@ -525,6 +2308,13 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintm v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundps xmm0, xmm1, 00000010b": { @@ -533,6 +2323,13 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintp v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundps xmm0, xmm1, 00000011b": { @@ -541,6 +2338,13 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintz v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundps xmm0, xmm1, 00000100b": { @@ -549,6 +2353,13 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x08 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti v4.4s, v4.4s", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundps ymm0, ymm1, 00000000b": { @@ -557,6 +2368,11 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintn z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vroundps ymm0, ymm1, 00000001b": { @@ -565,6 +2381,11 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintm z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vroundps ymm0, ymm1, 00000010b": { @@ -573,6 +2394,11 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintp z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vroundps ymm0, ymm1, 00000011b": { @@ -581,6 +2407,11 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintz z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vroundps ymm0, ymm1, 00000100b": { @@ -589,6 +2420,11 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x08 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti z4.s, p7/m, z4.s", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd xmm0, xmm1, 00000000b": { @@ -597,6 +2433,13 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd xmm0, xmm1, 00000001b": { @@ -605,6 +2448,13 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintm v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd xmm0, xmm1, 00000010b": { @@ -613,6 +2463,13 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintp v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd xmm0, xmm1, 00000011b": { @@ -621,6 +2478,13 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintz v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd xmm0, xmm1, 00000100b": { @@ -629,6 +2493,13 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x09 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti v4.2d, v4.2d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd ymm0, ymm1, 00000000b": { @@ -637,6 +2508,11 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintn z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd ymm0, ymm1, 00000001b": { @@ -645,6 +2521,11 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintm z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd ymm0, ymm1, 00000010b": { @@ -653,6 +2534,11 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintp z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd ymm0, ymm1, 00000011b": { @@ -661,6 +2547,11 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frintz z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vroundpd ymm0, ymm1, 00000100b": { @@ -669,6 +2560,11 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x09 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "frinti z4.d, p7/m, z4.d", + "mov z16.d, p7/m, z4.d" ] }, "vroundss xmm0, xmm1, 00000000b": { @@ -677,6 +2573,20 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frinti v4.4s, v4.4s", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundss xmm0, xmm1, 00000001b": { @@ -685,6 +2595,20 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frintm v4.4s, v4.4s", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundss xmm0, xmm1, 00000010b": { @@ -693,6 +2617,20 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frintp v4.4s, v4.4s", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundss xmm0, xmm1, 00000011b": { @@ -701,6 +2639,20 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frintz v4.4s, v4.4s", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundss xmm0, xmm1, 00000100b": { @@ -709,6 +2661,20 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x0a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v0.2d, #0x0", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "frinti v4.4s, v4.4s", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.s[0], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundsd xmm0, xmm1, 00000000b": { @@ -717,6 +2683,18 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "frinti v4.2d, v4.2d", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundsd xmm0, xmm1, 00000001b": { @@ -725,6 +2703,18 @@ "Comment": [ "-inf rounding", "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "frintm v4.2d, v4.2d", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundsd xmm0, xmm1, 00000010b": { @@ -733,6 +2723,18 @@ "Comment": [ "+inf rounding", "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "frintp v4.2d, v4.2d", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundsd xmm0, xmm1, 00000011b": { @@ -741,6 +2743,18 @@ "Comment": [ "truncate rounding", "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "frintz v4.2d, v4.2d", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vroundsd xmm0, xmm1, 00000100b": { @@ -749,6 +2763,18 @@ "Comment": [ "host mode rounding", "Map 3 0b01 0x0b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.8b, v4.8b", + "frinti v4.2d, v4.2d", + "mov z5.d, p7/m, z16.d", + "mov v0.16b, v5.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendps xmm0, xmm1, xmm2, 0000b": { @@ -756,6 +2782,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendps xmm0, xmm1, xmm2, 0001b": { @@ -763,6 +2795,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.s[0], v5.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[1]", + "mov v5.s[2], v4.s[2]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[3]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendps xmm0, xmm1, xmm2, 1111b": { @@ -770,6 +2817,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendps ymm0, ymm1, ymm2, 00000000b": { @@ -777,6 +2830,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vblendps ymm0, ymm1, ymm2, 10000001b": { @@ -784,6 +2841,68 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s5", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[1]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[2]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[3]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[4]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[5]", + "mov z6.d, z6.d", + "mov z6.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z4.s[6]", + "mov z4.d, z6.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, z5.s[7]", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vblendps ymm0, ymm1, ymm2, 11111111b": { @@ -791,6 +2910,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd xmm0, xmm1, xmm2, 00b": { @@ -798,6 +2921,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd xmm0, xmm1, xmm2, 01b": { @@ -805,6 +2934,19 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.d[0], v5.d[0]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[1]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd xmm0, xmm1, xmm2, 10b": { @@ -812,6 +2954,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.d[0], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.d[1], v5.d[1]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd xmm0, xmm1, xmm2, 11b": { @@ -819,6 +2972,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0000b": { @@ -826,6 +2985,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0001b": { @@ -833,6 +2996,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0010b": { @@ -840,6 +3037,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0011b": { @@ -847,6 +3078,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0100b": { @@ -854,6 +3119,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0101b": { @@ -861,6 +3160,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0110b": { @@ -868,6 +3201,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 0111b": { @@ -875,6 +3242,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[3]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1000b": { @@ -882,6 +3283,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1001b": { @@ -889,6 +3324,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1010b": { @@ -896,6 +3365,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1011b": { @@ -903,6 +3406,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[2]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1100b": { @@ -910,6 +3447,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1101b": { @@ -917,6 +3488,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d5", + "mov z6.d, z6.d", + "mov z6.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z4.d[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1110b": { @@ -924,6 +3529,40 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, d4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[2]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.d, z5.d[3]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendpd ymm0, ymm1, ymm2, 1111b": { @@ -931,6 +3570,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0d 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw xmm0, xmm1, xmm2, 00000000b": { @@ -938,6 +3581,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw xmm0, xmm1, xmm2, 00000001b": { @@ -945,6 +3594,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "mov v0.16b, v6.16b", + "mov v0.h[0], v5.h[0]", + "mov v5.16b, v0.16b", + "mov v5.h[1], v4.h[1]", + "mov v5.h[2], v4.h[2]", + "mov v5.h[3], v4.h[3]", + "mov v5.h[4], v4.h[4]", + "mov v5.h[5], v4.h[5]", + "mov v5.h[6], v4.h[6]", + "mov v0.16b, v5.16b", + "mov v0.h[7], v4.h[7]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw xmm0, xmm1, xmm2, 11111111b": { @@ -952,6 +3620,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw ymm0, ymm1, ymm2, 00000000b": { @@ -959,6 +3633,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw ymm0, ymm1, ymm2, 00000001b": { @@ -966,6 +3644,124 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, h5", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[1]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[2]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[3]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x40", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[4]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[5]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x400", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[6]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[7]", + "mov z6.d, z6.d", + "mov z6.h, p0/m, z1.h", + "b #+0x8", + "udf #0x4000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z5.h[8]", + "mov z5.d, z6.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[9]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[10]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[11]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[12]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[13]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "add z0.b, p0/m, z0.b, z0.b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[14]", + "mov z5.d, z5.d", + "mov z5.h, p0/m, z1.h", + "b #+0x8", + "adr x0, #+0x0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.h, z4.h[15]", + "mov z4.d, z5.d", + "mov z4.h, p0/m, z1.h", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpblendw ymm0, ymm1, ymm2, 11111111b": { @@ -973,6 +3769,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr xmm0, xmm1, xmm2, 0": { @@ -980,6 +3780,13 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v4.16b, v5.16b, v4.16b, #0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr xmm0, xmm1, xmm2, 1": { @@ -987,6 +3794,13 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v4.16b, v5.16b, v4.16b, #1", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr xmm0, xmm1, xmm2, 15": { @@ -994,6 +3808,13 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v4.16b, v5.16b, v4.16b, #15", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr xmm0, xmm1, xmm2, 16": { @@ -1001,6 +3822,14 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "ext v4.16b, v4.16b, v0.16b, #0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr ymm0, ymm1, ymm2, 0": { @@ -1008,6 +3837,34 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v6.16b, v5.16b, v4.16b, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "ext v4.16b, v5.16b, v4.16b, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr ymm0, ymm1, ymm2, 1": { @@ -1015,6 +3872,34 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v6.16b, v5.16b, v4.16b, #1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "ext v4.16b, v5.16b, v4.16b, #1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr ymm0, ymm1, ymm2, 15": { @@ -1022,6 +3907,34 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "ext v6.16b, v5.16b, v4.16b, #15", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "ext v4.16b, v5.16b, v4.16b, #15", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpalignr ymm0, ymm1, ymm2, 16": { @@ -1029,6 +3942,36 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v0.2d, #0x0", + "ext v6.16b, v4.16b, v0.16b, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "movi v0.2d, #0x0", + "ext v4.16b, v4.16b, v0.16b, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpextrb rax, xmm0, 0": { @@ -1036,6 +3979,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x14 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.b[0]", + "uxtb x4, w20" ] }, "vpextrb rax, xmm0, 15": { @@ -1043,6 +3991,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x14 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.b[15]", + "uxtb x4, w20" ] }, "vpextrw rax, xmm0, 0": { @@ -1050,6 +4003,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x15 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.h[0]", + "uxth x4, w20" ] }, "vpextrw rax, xmm0, 7": { @@ -1057,6 +4015,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x15 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "umov w20, v4.h[7]", + "uxth x4, w20" ] }, "vpextrd rax, xmm0, 0": { @@ -1064,6 +4027,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov w4, v4.s[0]" ] }, "vpextrd rax, xmm0, 3": { @@ -1071,6 +4038,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov w4, v4.s[3]" ] }, "vextractps eax, xmm0, 0": { @@ -1078,6 +4049,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x17 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov w4, v4.s[0]" ] }, "vextractps eax, xmm0, 3": { @@ -1085,6 +4060,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x17 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z16.d", + "mov w4, v4.s[3]" ] }, "vinsertf128 ymm0, ymm1, xmm2, 0": { @@ -1092,6 +4071,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x18 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vinsertf128 ymm0, ymm1, xmm2, 1": { @@ -1099,6 +4090,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x18 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vextractf128 xmm0, ymm1, 0": { @@ -1106,6 +4109,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x19 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vextractf128 xmm0, ymm1, 1": { @@ -1113,6 +4121,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x19 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.q, z4.q[1]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vcvtps2ph xmm0, xmm1, 00000000b": { @@ -1211,6 +4225,15 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x20 128-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.b[0], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrb xmm0, xmm1, eax, 15": { @@ -1219,6 +4242,15 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x20 128-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.b[15], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b0000))": { @@ -1227,6 +4259,14 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x21 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.s[0], v5.s[0]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b1111))": { @@ -1235,6 +4275,12 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x21 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vinsertps xmm0, xmm1, xmm2, ((0b11 << 6) | (0b11 << 4) | (0b0000))": { @@ -1243,6 +4289,14 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x21 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov v4.s[3], v5.s[3]", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrd xmm0, xmm1, eax, 0": { @@ -1251,6 +4305,15 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.s[0], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrd xmm0, xmm1, eax, 3": { @@ -1259,6 +4322,15 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #32", + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.s[3], w20", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrq xmm0, xmm1, rax, 0": { @@ -1267,6 +4339,14 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.d[0], x4", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpinsrq xmm0, xmm1, rax, 1": { @@ -1275,6 +4355,14 @@ "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.d[1], x4", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vinserti128 ymm0, ymm1, xmm2, 0": { @@ -1282,6 +4370,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x38 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "mov z16.d, p7/m, z4.d" ] }, "vinserti128 ymm0, ymm1, xmm2, 1": { @@ -1289,6 +4389,18 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x38 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vextracti128 xmm0, ymm1, 0": { @@ -1296,6 +4408,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x39 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vextracti128 xmm0, ymm1, 1": { @@ -1303,6 +4420,12 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x39 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z4.q, z4.q[1]", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdpps xmm0, xmm1, xmm2, 00000000b": { @@ -1310,6 +4433,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdpps xmm0, xmm1, xmm2, 00001111b": { @@ -1317,6 +4445,28 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "fmul v4.4s, v4.4s, v5.4s", + "mov v4.s[0], v6.s[0]", + "mov v4.s[1], v6.s[0]", + "mov v4.s[2], v6.s[0]", + "mov v4.s[3], v6.s[0]", + "faddp v4.4s, v4.4s, v6.4s", + "faddp v4.4s, v4.4s, v6.4s", + "mov v0.16b, v6.16b", + "mov v0.s[0], v4.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdpps xmm0, xmm1, xmm2, 11110000b": { @@ -1324,6 +4474,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdpps xmm0, xmm1, xmm2, 11111111b": { @@ -1331,6 +4486,24 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "fmul v4.4s, v4.4s, v5.4s", + "faddp v4.4s, v4.4s, v6.4s", + "faddp v4.4s, v4.4s, v6.4s", + "mov v0.16b, v6.16b", + "mov v0.s[0], v4.s[0]", + "mov v5.16b, v0.16b", + "mov v5.s[1], v4.s[0]", + "mov v5.s[2], v4.s[0]", + "mov v0.16b, v5.16b", + "mov v0.s[3], v4.s[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdpps ymm0, ymm1, ymm2, 00000000b": { @@ -1338,6 +4511,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, #0", + "mov z16.d, p7/m, z4.d" ] }, "vdpps ymm0, ymm1, ymm2, 00001111b": { @@ -1345,6 +4522,135 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "fmul z4.s, z4.s, z5.s", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s6", + "mov z4.d, z4.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z6.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z6.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z6.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vdpps ymm0, ymm1, ymm2, 11110000b": { @@ -1352,6 +4658,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, #0", + "mov z16.d, p7/m, z4.d" ] }, "vdpps ymm0, ymm1, ymm2, 11111111b": { @@ -1359,6 +4669,79 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x40 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "fmul z4.s, z4.s, z5.s", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z6.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "movprfx z0, z4", + "faddp z0.s, p7/m, z0.s, z6.s", + "uzp1 z4.s, z0.s, z0.s", + "uzp2 z1.s, z0.s, z0.s", + "splice z4.d, p6, z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z6.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x10", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x100", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "udf #0x1000", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z5.d, z5.d", + "mov z5.s, p0/m, z1.s", + "b #+0x8", + "unallocated (Unallocated)", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.s, s4", + "mov z4.d, z5.d", + "mov z4.s, p0/m, z1.s", + "b #+0x8", + "adr x0, #+0x0", + "mov z16.d, p7/m, z4.d" ] }, "vdppd xmm0, xmm1, xmm2, 00000000b": { @@ -1366,6 +4749,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x41 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdppd xmm0, xmm1, xmm2, 00001111b": { @@ -1373,6 +4761,23 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x41 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "fmul v4.2d, v4.2d, v5.2d", + "mov v4.d[0], v6.d[0]", + "mov v4.d[1], v6.d[0]", + "faddp v4.2d, v4.2d, v6.2d", + "mov v0.16b, v6.16b", + "mov v0.d[0], v4.d[0]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdppd xmm0, xmm1, xmm2, 11110000b": { @@ -1380,6 +4785,11 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x41 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vdppd xmm0, xmm1, xmm2, 11111111b": { @@ -1387,6 +4797,21 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x41 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "movi v6.2d, #0x0", + "fmul v4.2d, v4.2d, v5.2d", + "faddp v4.2d, v4.2d, v6.2d", + "mov v0.16b, v6.16b", + "mov v0.d[0], v4.d[0]", + "mov v5.16b, v0.16b", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 000b": { @@ -1394,6 +4819,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[0]", + "ext v6.16b, v4.16b, v4.16b, #0", + "ext v7.16b, v4.16b, v4.16b, #1", + "ext v8.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 001b": { @@ -1401,6 +4849,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[1]", + "ext v6.16b, v4.16b, v4.16b, #0", + "ext v7.16b, v4.16b, v4.16b, #1", + "ext v8.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 010b": { @@ -1408,6 +4879,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[2]", + "ext v6.16b, v4.16b, v4.16b, #0", + "ext v7.16b, v4.16b, v4.16b, #1", + "ext v8.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 011b": { @@ -1415,6 +4909,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[3]", + "ext v6.16b, v4.16b, v4.16b, #0", + "ext v7.16b, v4.16b, v4.16b, #1", + "ext v8.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 100b": { @@ -1422,6 +4939,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[0]", + "ext v6.16b, v4.16b, v4.16b, #4", + "ext v7.16b, v4.16b, v4.16b, #5", + "ext v8.16b, v4.16b, v4.16b, #6", + "ext v4.16b, v4.16b, v4.16b, #7", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 101b": { @@ -1429,6 +4969,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[1]", + "ext v6.16b, v4.16b, v4.16b, #4", + "ext v7.16b, v4.16b, v4.16b, #5", + "ext v8.16b, v4.16b, v4.16b, #6", + "ext v4.16b, v4.16b, v4.16b, #7", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 110b": { @@ -1436,6 +4999,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[2]", + "ext v6.16b, v4.16b, v4.16b, #4", + "ext v7.16b, v4.16b, v4.16b, #5", + "ext v8.16b, v4.16b, v4.16b, #6", + "ext v4.16b, v4.16b, v4.16b, #7", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw xmm0, xmm1, xmm2, 111b": { @@ -1443,6 +5029,29 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v5.4s, v5.s[3]", + "ext v6.16b, v4.16b, v4.16b, #4", + "ext v7.16b, v4.16b, v4.16b, #5", + "ext v8.16b, v4.16b, v4.16b, #6", + "ext v4.16b, v4.16b, v4.16b, #7", + "uabdl v6.8h, v6.8b, v5.8b", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v6.8h, v7.8h", + "addp v4.8h, v8.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 000b": { @@ -1450,6 +5059,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v10.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 001b": { @@ -1457,6 +5114,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[1]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v10.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 010b": { @@ -1464,6 +5169,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[2]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v10.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 011b": { @@ -1471,6 +5224,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[3]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v10.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 100b": { @@ -1478,6 +5279,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #4", + "ext v8.16b, v4.16b, v4.16b, #5", + "ext v9.16b, v4.16b, v4.16b, #6", + "ext v10.16b, v4.16b, v4.16b, #7", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 101b": { @@ -1485,6 +5334,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[1]", + "ext v7.16b, v4.16b, v4.16b, #4", + "ext v8.16b, v4.16b, v4.16b, #5", + "ext v9.16b, v4.16b, v4.16b, #6", + "ext v10.16b, v4.16b, v4.16b, #7", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 110b": { @@ -1492,6 +5389,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[2]", + "ext v7.16b, v4.16b, v4.16b, #4", + "ext v8.16b, v4.16b, v4.16b, #5", + "ext v9.16b, v4.16b, v4.16b, #6", + "ext v10.16b, v4.16b, v4.16b, #7", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vmpsadbw ymm0, ymm1, ymm2, 111b": { @@ -1499,6 +5444,54 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x42 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v6.4s, v5.s[3]", + "ext v7.16b, v4.16b, v4.16b, #4", + "ext v8.16b, v4.16b, v4.16b, #5", + "ext v9.16b, v4.16b, v4.16b, #6", + "ext v10.16b, v4.16b, v4.16b, #7", + "uabdl v7.8h, v7.8b, v6.8b", + "uabdl v8.8h, v8.8b, v6.8b", + "uabdl v9.8h, v9.8b, v6.8b", + "uabdl v6.8h, v10.8b, v6.8b", + "addp v7.8h, v7.8h, v8.8h", + "addp v6.8h, v9.8h, v6.8h", + "addp v6.8h, v7.8h, v6.8h", + "uzp1 v7.8h, v6.8h, v6.8h", + "uzp2 v6.8h, v6.8h, v6.8h", + "mov v0.16b, v7.16b", + "mov v0.d[1], v6.d[0]", + "mov v6.16b, v0.16b", + "mov z4.q, z4.q[1]", + "mov z5.q, z5.q[1]", + "dup v5.4s, v5.s[0]", + "ext v7.16b, v4.16b, v4.16b, #0", + "ext v8.16b, v4.16b, v4.16b, #1", + "ext v9.16b, v4.16b, v4.16b, #2", + "ext v4.16b, v4.16b, v4.16b, #3", + "uabdl v7.8h, v7.8b, v5.8b", + "uabdl v8.8h, v8.8b, v5.8b", + "uabdl v9.8h, v9.8b, v5.8b", + "uabdl v4.8h, v4.8b, v5.8b", + "addp v5.8h, v7.8h, v8.8h", + "addp v4.8h, v9.8h, v4.8h", + "addp v4.8h, v5.8h, v4.8h", + "uzp1 v5.8h, v4.8h, v4.8h", + "uzp2 v4.8h, v4.8h, v4.8h", + "mov v0.16b, v5.16b", + "mov v0.d[1], v4.d[0]", + "mov v4.16b, v0.16b", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpclmulqdq xmm0, xmm1, xmm2, 00000b": { @@ -1506,6 +5499,14 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x44 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpclmulqdq xmm0, xmm1, xmm2, 00001b": { @@ -1513,6 +5514,15 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x44 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v0.2d, v4.d[1]", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpclmulqdq xmm0, xmm1, xmm2, 10000b": { @@ -1520,6 +5530,15 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x44 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "dup v0.2d, v5.d[1]", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpclmulqdq xmm0, xmm1, xmm2, 10001b": { @@ -1527,6 +5546,14 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x44 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpclmulqdq ymm0, ymm1, ymm2, 00000b": { @@ -1566,6 +5593,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 01b": { @@ -1573,6 +5619,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 10b": { @@ -1580,6 +5645,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 11b": { @@ -1587,6 +5672,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 010000b": { @@ -1594,6 +5699,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 010001b": { @@ -1601,6 +5725,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 010010b": { @@ -1608,6 +5751,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 010011b": { @@ -1615,6 +5778,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z5.d, z6.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 100000b": { @@ -1622,6 +5805,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 100001b": { @@ -1629,6 +5832,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q5", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 100010b": { @@ -1636,6 +5859,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 100011b": { @@ -1643,6 +5885,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 110000b": { @@ -1650,6 +5911,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 110001b": { @@ -1657,6 +5938,26 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z5.q[1]", + "mov z4.d, z4.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 110010b": { @@ -1664,6 +5965,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vperm2i128 ymm0, ymm1, ymm2, 110011b": { @@ -1671,6 +5991,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x46 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z18.d", + "mov z5.d, #0", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z5.d, z5.d", + "mov z5.d, p0/m, z1.d", + "b #+0x8", + "udf #0x101", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, z4.q[1]", + "mov z4.d, z5.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vblendvps xmm0, xmm1, xmm2, xmm3": { @@ -1678,6 +6017,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4a 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "sshr v6.4s, v6.4s, #31", + "mov v0.16b, v6.16b", + "bsl v0.16b, v5.16b, v4.16b", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendvps ymm0, ymm1, ymm2, ymm3": { @@ -1685,6 +6035,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4a 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "movprfx z6, z6", + "asr z6.s, p7/m, z6.s, #31", + "movprfx z0, z5", + "bsl z0.d, z0.d, z4.d, z6.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vblendvpd xmm0, xmm1, xmm2, xmm3": { @@ -1692,6 +6053,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4b 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "sshr v6.2d, v6.2d, #63", + "mov v0.16b, v6.16b", + "bsl v0.16b, v5.16b, v4.16b", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vblendvpd ymm0, ymm1, ymm2, ymm3": { @@ -1699,6 +6071,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4b 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "movprfx z6, z6", + "asr z6.d, p7/m, z6.d, #63", + "movprfx z0, z5", + "bsl z0.d, z0.d, z4.d, z6.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vpblendvb xmm0, xmm1, xmm2, xmm3": { @@ -1706,6 +6089,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4c 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "sshr v6.16b, v6.16b, #7", + "mov v0.16b, v6.16b", + "bsl v0.16b, v5.16b, v4.16b", + "mov v4.16b, v0.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpblendvb ymm0, ymm1, ymm2, ymm3": { @@ -1713,6 +6107,17 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0x4c 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, p7/m, z18.d", + "mov z6.d, p7/m, z19.d", + "movprfx z6, z6", + "asr z6.b, p7/m, z6.b, #7", + "movprfx z0, z5", + "bsl z0.d, z0.d, z4.d, z6.d", + "mov z4.d, z0.d", + "mov z16.d, p7/m, z4.d" ] }, "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { @@ -1960,6 +6365,22 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0xdf 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "ldr q2, pc+12", + "tbl v4.16b, {v0.16b}, v2.16b", + "b #+0x14", + "add w4, w8, w14", + "umin z1.b, p3/m, z1.b, z16.b", + "unallocated (Unallocated)", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vaeskeygenassist xmm0, xmm1, 0xFF": { @@ -1967,6 +6388,25 @@ "Optimal": "No", "Comment": [ "Map 3 0b01 0xdf 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "eor v1.16b, v1.16b, v1.16b", + "mov v0.16b, v4.16b", + "unimplemented (Unimplemented)", + "ldr q2, pc+24", + "tbl v0.16b, {v0.16b}, v2.16b", + "orr x0, xzr, #0xff00000000", + "dup v1.2d, x0", + "eor v4.16b, v0.16b, v1.16b", + "b #+0x14", + "add w4, w8, w14", + "umin z1.b, p3/m, z1.b, z16.b", + "unallocated (Unallocated)", + "unallocated (Unallocated)", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "rorx eax, ebx, 0": { @@ -1974,6 +6414,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b11 0xf0 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ror w4, w20, #0" ] }, "rorx eax, ebx, 31": { @@ -1981,6 +6425,10 @@ "Optimal": "No", "Comment": [ "Map 3 0b11 0xf0 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "ror w4, w20, #31" ] }, "rorx rax, rbx, 0": { @@ -1988,6 +6436,9 @@ "Optimal": "Yes", "Comment": [ "Map 3 0b11 0xf0 64-bit" + ], + "ExpectedArm64ASM": [ + "ror x4, x7, #0" ] }, "rorx rax, rbx, 63": { @@ -1995,7 +6446,10 @@ "Optimal": "Yes", "Comment": [ "Map 3 0b11 0xf0 64-bit" + ], + "ExpectedArm64ASM": [ + "ror x4, x7, #63" ] } } -} +} \ No newline at end of file diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 907bdd327..28151aecd 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -12,6 +12,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw xmm0, xmm1, 15": { @@ -19,6 +25,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ushr v4.8h, v4.8h, #15", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw xmm0, xmm1, 16": { @@ -26,6 +39,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw ymm0, ymm1, 0": { @@ -33,6 +53,10 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw ymm0, ymm1, 15": { @@ -40,6 +64,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsr z4.h, p7/m, z4.h, #15", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlw ymm0, ymm1, 16": { @@ -47,6 +77,11 @@ "Optimal": "No", "Comment": [ "Map group 12 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw xmm0, xmm1, 0": { @@ -54,6 +89,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw xmm0, xmm1, 15": { @@ -61,6 +102,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sshr v4.8h, v4.8h, #15", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw xmm0, xmm1, 16": { @@ -68,6 +116,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sshr v4.8h, v4.8h, #15", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw ymm0, ymm1, 0": { @@ -75,6 +130,10 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw ymm0, ymm1, 15": { @@ -82,6 +141,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "asr z4.h, p7/m, z4.h, #15", + "mov z16.d, p7/m, z4.d" ] }, "vpsraw ymm0, ymm1, 16": { @@ -89,6 +154,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "asr z4.h, p7/m, z4.h, #15", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw xmm0, xmm1, 0": { @@ -96,6 +167,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw xmm0, xmm1, 15": { @@ -103,6 +180,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "shl v4.8h, v4.8h, #15", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw xmm0, xmm1, 16": { @@ -110,6 +194,13 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw ymm0, ymm1, 0": { @@ -117,6 +208,10 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw ymm0, ymm1, 15": { @@ -124,6 +219,12 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsl z4.h, p7/m, z4.h, #15", + "mov z16.d, p7/m, z4.d" ] }, "vpsllw ymm0, ymm1, 16": { @@ -131,6 +232,11 @@ "Optimal": "No", "Comment": [ "Map group 12 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld xmm0, xmm1, 0": { @@ -138,6 +244,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld xmm0, xmm1, 31": { @@ -145,6 +257,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ushr v4.4s, v4.4s, #31", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld xmm0, xmm1, 32": { @@ -152,6 +271,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld ymm0, ymm1, 0": { @@ -159,6 +285,10 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld ymm0, ymm1, 31": { @@ -166,6 +296,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsr z4.s, p7/m, z4.s, #31", + "mov z16.d, p7/m, z4.d" ] }, "vpsrld ymm0, ymm1, 32": { @@ -173,6 +309,11 @@ "Optimal": "No", "Comment": [ "Map group 13 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad xmm0, xmm1, 0": { @@ -180,6 +321,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad xmm0, xmm1, 31": { @@ -187,6 +334,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sshr v4.4s, v4.4s, #31", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad xmm0, xmm1, 32": { @@ -194,6 +348,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "sshr v4.4s, v4.4s, #31", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad ymm0, ymm1, 0": { @@ -201,6 +362,10 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad ymm0, ymm1, 31": { @@ -208,6 +373,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "asr z4.s, p7/m, z4.s, #31", + "mov z16.d, p7/m, z4.d" ] }, "vpsrad ymm0, ymm1, 32": { @@ -215,6 +386,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b100 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "asr z4.s, p7/m, z4.s, #31", + "mov z16.d, p7/m, z4.d" ] }, "vpslld xmm0, xmm1, 0": { @@ -222,6 +399,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslld xmm0, xmm1, 31": { @@ -229,6 +412,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "shl v4.4s, v4.4s, #31", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslld xmm0, xmm1, 32": { @@ -236,6 +426,13 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslld ymm0, ymm1, 0": { @@ -243,6 +440,10 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpslld ymm0, ymm1, 31": { @@ -250,6 +451,12 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsl z4.s, p7/m, z4.s, #31", + "mov z16.d, p7/m, z4.d" ] }, "vpslld ymm0, ymm1, 32": { @@ -257,6 +464,11 @@ "Optimal": "No", "Comment": [ "Map group 13 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq xmm0, xmm1, 0": { @@ -264,6 +476,12 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq xmm0, xmm1, 63": { @@ -271,6 +489,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "ushr v4.2d, v4.2d, #63", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq xmm0, xmm1, 64": { @@ -278,6 +503,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq ymm0, ymm1, 0": { @@ -285,6 +517,10 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq ymm0, ymm1, 63": { @@ -292,6 +528,12 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsr z4.d, p7/m, z4.d, #63", + "mov z16.d, p7/m, z4.d" ] }, "vpsrlq ymm0, ymm1, 64": { @@ -299,6 +541,11 @@ "Optimal": "No", "Comment": [ "Map group 14 0b010 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq xmm0, xmm1, 0": { @@ -306,6 +553,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "ext v4.16b, v4.16b, v5.16b, #0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq xmm0, xmm1, 15": { @@ -313,6 +567,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "ext v4.16b, v4.16b, v5.16b, #15", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq xmm0, xmm1, 16": { @@ -320,6 +581,11 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq ymm0, ymm1, 0": { @@ -327,6 +593,22 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "ext v6.16b, v4.16b, v5.16b, #0", + "movprfx z1, z4", + "ext z1.b, z1.b, z5.b, #16", + "mov z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq ymm0, ymm1, 15": { @@ -334,6 +616,22 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "ext v6.16b, v4.16b, v5.16b, #15", + "movprfx z1, z4", + "ext z1.b, z1.b, z5.b, #31", + "mov z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpsrldq ymm0, ymm1, 16": { @@ -341,6 +639,10 @@ "Optimal": "No", "Comment": [ "Map group 14 0b011 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, #0", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq xmm0, xmm1, 0": { @@ -348,6 +650,12 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq xmm0, xmm1, 63": { @@ -355,6 +663,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "shl v4.2d, v4.2d, #63", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq xmm0, xmm1, 64": { @@ -362,6 +677,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq ymm0, ymm1, 0": { @@ -369,6 +691,10 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq ymm0, ymm1, 63": { @@ -376,6 +702,12 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movprfx z4, z4", + "lsl z4.d, p7/m, z4.d, #63", + "mov z16.d, p7/m, z4.d" ] }, "vpsllq ymm0, ymm1, 64": { @@ -383,6 +715,11 @@ "Optimal": "No", "Comment": [ "Map group 14 0b110 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v4.2d, #0x0", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq xmm0, xmm1, 0": { @@ -390,6 +727,11 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq xmm0, xmm1, 15": { @@ -397,6 +739,13 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 128-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "movi v5.2d, #0x0", + "ext v4.16b, v5.16b, v4.16b, #1", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq xmm0, xmm1, 16": { @@ -404,6 +753,11 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 128-bit" + ], + "ExpectedArm64ASM": [ + "movi v4.2d, #0x0", + "mov v4.16b, v4.16b", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq ymm0, ymm1, 0": { @@ -411,6 +765,10 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq ymm0, ymm1, 15": { @@ -418,6 +776,22 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, p7/m, z17.d", + "mov z5.d, #0", + "ext v6.16b, v5.16b, v4.16b, #1", + "movprfx z1, z5", + "ext z1.b, z1.b, z4.b, #17", + "mov z4.d, z1.d", + "adr x0, #+0x18", + "ldr p0, [x0]", + "mov z1.q, q4", + "mov z4.d, z6.d", + "mov z4.d, p0/m, z1.d", + "b #+0x8", + "unallocated (Unallocated)", + "mov z16.d, p7/m, z4.d" ] }, "vpslldq ymm0, ymm1, 16": { @@ -425,6 +799,10 @@ "Optimal": "No", "Comment": [ "Map group 14 0b111 256-bit" + ], + "ExpectedArm64ASM": [ + "mov z4.d, #0", + "mov z16.d, p7/m, z4.d" ] }, "vldmxcsr [rax]": { @@ -432,6 +810,25 @@ "Optimal": "No", "Comment": [ "Map group 15 0b010" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "ubfx x20, x20, #13, #3", + "and x0, x20, #0x3", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, xzr, eq", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" ] }, "vstmxcsr [rax]": { @@ -439,6 +836,25 @@ "Optimal": "No", "Comment": [ "Map group 15 0b011" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1f80", + "mrs x21, fpcr", + "lsr x21, x21, #22", + "and x0, x21, #0x3", + "cmp x0, #0x1 (1)", + "orr w2, wzr, #0x2", + "csel x1, x2, xzr, eq", + "cmp x0, #0x2 (2)", + "orr w2, wzr, #0x1", + "csel x1, x2, x1, eq", + "cmp x0, #0x3 (3)", + "orr w2, wzr, #0x3", + "csel x1, x2, x1, eq", + "orr x21, x21, x1", + "bfxil x21, x1, #0, #2", + "bfi w20, w21, #13, #3", + "str w20, [x4]" ] }, "blsr eax, ebx": { @@ -446,6 +862,22 @@ "Optimal": "No", "Comment": [ "Map group 17 0b001 32-bit" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ubfx x21, x7, #0, #32", + "sub x22, x21, #0x1 (1)", + "and x22, x22, x21", + "ubfx x4, x22, #0, #32", + "mov w23, #0x0", + "tst w22, w22", + "mrs x22, nzcv", + "strb w23, [x28, #708]", + "strb w23, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x20, x23, x20, eq", + "orr x20, x22, x20, lsl #29", + "str w20, [x28, #728]" ] }, "blsr rax, rbx": { @@ -453,6 +885,20 @@ "Optimal": "No", "Comment": [ "Map group 17 0b001 64-bit" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "sub x21, x7, #0x1 (1)", + "and x4, x21, x7", + "mov w21, #0x0", + "tst x4, x4", + "mrs x22, nzcv", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x7, #0x0 (0)", + "csel x20, x21, x20, eq", + "orr x20, x22, x20, lsl #29", + "str w20, [x28, #728]" ] }, "blsmsk eax, ebx": { @@ -460,6 +906,25 @@ "Optimal": "No", "Comment": [ "Map group 17 0b010 32-bit" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "ubfx x21, x7, #0, #32", + "sub x22, x21, #0x1 (1)", + "eor x22, x22, x21", + "ubfx x4, x22, #0, #32", + "mov w22, #0x0", + "ldr w23, [x28, #728]", + "bfi w23, w22, #30, #1", + "bfi w23, w22, #28, #1", + "strb w22, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x20, x22, x20, eq", + "mov w0, w23", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "blsmsk rax, rbx": { @@ -467,6 +932,23 @@ "Optimal": "No", "Comment": [ "Map group 17 0b010 64-bit" + ], + "ExpectedArm64ASM": [ + "orr w20, wzr, #0x1", + "sub x21, x7, #0x1 (1)", + "eor x4, x21, x7", + "mov w21, #0x0", + "ldr w22, [x28, #728]", + "bfi w22, w21, #30, #1", + "bfi w22, w21, #28, #1", + "strb w21, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x7, #0x0 (0)", + "csel x20, x21, x20, eq", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "lsr w20, w0, #0", + "str w20, [x28, #728]" ] }, "blsi eax, ebx": { @@ -474,6 +956,21 @@ "Optimal": "No", "Comment": [ "Map group 17 0b011 32-bit" + ], + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #32", + "neg w21, w20", + "and w4, w20, w21", + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "tst w4, w4", + "mrs x22, nzcv", + "strb w20, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x0 (0)", + "csel x20, x20, x21, eq", + "orr x20, x22, x20, lsl #29", + "str w20, [x28, #728]" ] }, "blsi rax, rbx": { @@ -481,6 +978,20 @@ "Optimal": "No", "Comment": [ "Map group 17 0b011 64-bit" + ], + "ExpectedArm64ASM": [ + "neg x20, x7", + "and x4, x7, x20", + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "tst x4, x4", + "mrs x22, nzcv", + "strb w20, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x0 (0)", + "csel x20, x20, x21, eq", + "orr x20, x22, x20, lsl #29", + "str w20, [x28, #728]" ] } } diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index ee8ebecfa..66f96f736 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -13,6 +13,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul dword [rax]": { @@ -20,6 +115,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcom dword [rax]": { @@ -27,6 +217,107 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcomp dword [rax]": { @@ -34,6 +325,118 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fsub dword [rax]": { @@ -41,6 +444,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr dword [rax]": { @@ -48,6 +546,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv dword [rax]": { @@ -55,6 +648,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr dword [rax]": { @@ -62,6 +750,101 @@ "Optimal": "No", "Comment": [ "0xd8 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st0": { @@ -69,6 +852,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st1": { @@ -76,6 +915,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st2": { @@ -83,6 +978,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st3": { @@ -90,6 +1041,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st4": { @@ -97,6 +1104,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st5": { @@ -104,6 +1167,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st6": { @@ -111,6 +1230,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st0, st7": { @@ -118,6 +1293,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st0": { @@ -125,6 +1356,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st1": { @@ -132,6 +1419,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st2": { @@ -139,6 +1482,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st3": { @@ -146,6 +1545,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st4": { @@ -153,6 +1608,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st5": { @@ -160,6 +1671,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st6": { @@ -167,6 +1734,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st0, st7": { @@ -174,6 +1797,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcom st0, st0": { @@ -181,6 +1860,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" ] }, "fcom st0, st1": { @@ -188,6 +1929,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st2": { @@ -195,6 +1998,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st3": { @@ -202,6 +2067,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st4": { @@ -209,6 +2136,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st5": { @@ -216,6 +2205,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st6": { @@ -223,6 +2274,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcom st0, st7": { @@ -230,6 +2343,68 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcomp st0, st0": { @@ -237,6 +2412,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st1": { @@ -244,6 +2492,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st2": { @@ -251,6 +2572,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st3": { @@ -258,6 +2652,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrh w22, [x28, #1010]", + "lsl w23, w20, #1", + "lsl x24, x21, x23", + "bic w22, w22, w24", + "lsl x21, x21, x23", + "orr x21, x22, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st4": { @@ -265,6 +2732,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st5": { @@ -272,6 +2812,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st6": { @@ -279,6 +2892,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcomp st0, st7": { @@ -286,6 +2972,79 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fsub st0, st0": { @@ -293,6 +3052,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st1": { @@ -300,6 +3115,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st2": { @@ -307,6 +3178,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st3": { @@ -314,6 +3241,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st4": { @@ -321,6 +3304,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st5": { @@ -328,6 +3367,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st6": { @@ -335,6 +3430,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st0, st7": { @@ -342,6 +3493,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st0": { @@ -349,6 +3556,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st1": { @@ -356,6 +3619,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st2": { @@ -363,6 +3682,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st3": { @@ -370,6 +3745,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st4": { @@ -377,6 +3808,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st5": { @@ -384,6 +3871,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st6": { @@ -391,6 +3934,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st0, st7": { @@ -398,6 +3997,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st0": { @@ -405,6 +4060,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st1": { @@ -412,6 +4123,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st2": { @@ -419,6 +4186,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st3": { @@ -426,6 +4249,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st4": { @@ -433,6 +4312,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st5": { @@ -440,6 +4375,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st6": { @@ -447,6 +4438,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st0, st7": { @@ -454,6 +4501,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st0": { @@ -461,6 +4564,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st1": { @@ -468,6 +4627,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st2": { @@ -475,6 +4690,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st3": { @@ -482,6 +4753,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st4": { @@ -489,6 +4816,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st5": { @@ -496,6 +4879,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st6": { @@ -503,6 +4942,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st0, st7": { @@ -510,6 +5005,62 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld dword [rax]": { @@ -517,6 +5068,63 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s4", + "ldr x0, [x28, #1152]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fst dword [rax]": { @@ -524,6 +5132,53 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1168]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "fmov s4, s0", + "str s4, [x4]" ] }, "fstp dword [rax]": { @@ -531,6 +5186,64 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1168]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "fmov s4, s0", + "str s4, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fldenv [rax]": { @@ -538,6 +5251,62 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w20", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx x21, x20, #11, #3", + "strb w21, [x28, #747]", + "ubfx x21, x20, #8, #1", + "ubfx x22, x20, #9, #1", + "ubfx x23, x20, #10, #1", + "ubfx x20, x20, #14, #1", + "strb w21, [x28, #744]", + "strb w22, [x28, #745]", + "strb w23, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "strh w20, [x28, #1010]" ] }, "fldcw [rax]": { @@ -545,6 +5314,49 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w20", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w20, [x28, #1008]" ] }, "fnstenv [rax]": { @@ -552,6 +5364,33 @@ "Optimal": "No", "Comment": [ "0xd9 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "str w20, [x4]", + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "lsl w21, w21, #11", + "orr x21, x20, x21", + "ldrb w22, [x28, #744]", + "ldrb w23, [x28, #745]", + "ldrb w24, [x28, #746]", + "ldrb w25, [x28, #750]", + "lsl w22, w22, #8", + "orr x21, x21, x22", + "lsl w22, w23, #9", + "orr x21, x21, x22", + "lsl w22, w24, #10", + "orr x21, x21, x22", + "lsl w22, w25, #14", + "orr x21, x21, x22", + "str w21, [x4, #4]", + "ldrh w21, [x28, #1010]", + "str w21, [x4, #8]", + "str w20, [x4, #12]", + "str w20, [x4, #16]", + "str w20, [x4, #20]", + "str w20, [x4, #24]" ] }, "fnstcw [rax]": { @@ -559,6 +5398,10 @@ "Optimal": "Yes", "Comment": [ "0xd9 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "strh w20, [x4]" ] }, "fld st0": { @@ -566,6 +5409,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st1": { @@ -573,6 +5434,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st2": { @@ -580,6 +5459,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st3": { @@ -587,6 +5484,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w22, [x28, #1010]", + "lsl x23, x20, #1", + "lsl x21, x21, x23", + "bic w21, w22, w21", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st4": { @@ -594,6 +5509,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st5": { @@ -601,6 +5534,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st6": { @@ -608,6 +5559,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fld st7": { @@ -615,6 +5584,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st0": { @@ -622,6 +5609,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st1": { @@ -629,6 +5629,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st2": { @@ -636,6 +5649,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st3": { @@ -643,6 +5669,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st4": { @@ -650,6 +5689,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st5": { @@ -657,6 +5709,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st6": { @@ -664,6 +5729,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxch st0, st7": { @@ -671,6 +5749,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fnop": { @@ -678,13 +5769,27 @@ "Optimal": "Yes", "Comment": [ "0xd9 11b 0xd0 /2" - ] + ], + "ExpectedArm64ASM": [] }, "fchs": { "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": [ "0xd9 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "mov w21, #0x0", + "orr w22, wzr, #0x8000", + "fmov d5, x21", + "mov v5.16b, v5.16b", + "mov v5.d[1], x22", + "eor v4.16b, v4.16b, v5.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fabs": { @@ -692,6 +5797,19 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "mov x21, #0xffffffffffffffff", + "orr w22, wzr, #0x7fff", + "fmov d5, x21", + "mov v5.16b, v5.16b", + "mov v5.d[1], x22", + "and v4.16b, v4.16b, v5.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "ftst": { @@ -699,6 +5817,65 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "mov w20, #0x0", + "fmov d5, x20", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "strb w20, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]" ] }, "fxam": { @@ -706,6 +5883,27 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "mov x21, v4.d[1]", + "ubfx x21, x21, #15, #1", + "strb w21, [x28, #745]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x1", + "lsl w20, w20, #1", + "lsr w20, w21, w20", + "and x20, x20, #0x3", + "mov w21, #0x0", + "cmp x20, #0x3 (3)", + "cset x23, eq", + "cmp x20, #0x3 (3)", + "csel x20, x21, x22, eq", + "strb w23, [x28, #744]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" ] }, "fld1": { @@ -713,6 +5911,25 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "orr x21, xzr, #0x8000000000000000", + "orr w22, wzr, #0x3fff", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldl2t": { @@ -720,6 +5937,28 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x8afe", + "movk x21, #0xcd1b, lsl #16", + "movk x21, #0x784b, lsl #32", + "movk x21, #0xd49a, lsl #48", + "orr w22, wzr, #0x4000", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldl2e": { @@ -727,6 +5966,28 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xf0bc", + "movk x21, #0x5c17, lsl #16", + "movk x21, #0x3b29, lsl #32", + "movk x21, #0xb8aa, lsl #48", + "orr w22, wzr, #0x3fff", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldpi": { @@ -734,6 +5995,28 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xc235", + "movk x21, #0x2168, lsl #16", + "movk x21, #0xdaa2, lsl #32", + "movk x21, #0xc90f, lsl #48", + "orr w22, wzr, #0x4000", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldlg2": { @@ -741,6 +6024,28 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xf799", + "movk x21, #0xfbcf, lsl #16", + "movk x21, #0x9a84, lsl #32", + "movk x21, #0x9a20, lsl #48", + "mov w22, #0x3ffd", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldln2": { @@ -748,6 +6053,28 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x79ac", + "movk x21, #0xd1cf, lsl #16", + "movk x21, #0x17f7, lsl #32", + "movk x21, #0xb172, lsl #48", + "orr w22, wzr, #0x3ffe", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fldz": { @@ -755,6 +6082,24 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov w21, #0x0", + "fmov d4, x21", + "mov v4.16b, v4.16b", + "mov v4.d[1], x21", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "f2xm1": { @@ -762,6 +6107,56 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1320]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fyl2x": { @@ -769,6 +6164,71 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1424]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fptan": { @@ -776,6 +6236,74 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl x24, x21, #1", + "lsl x23, x23, x24", + "bic w22, w22, w23", + "strh w22, [x28, #1010]", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1328]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "orr x22, xzr, #0x8000000000000000", + "orr w23, wzr, #0x3fff", + "fmov d5, x22", + "mov v5.16b, v5.16b", + "mov v5.d[1], x23", + "mov w22, #0x0", + "strb w22, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]" ] }, "fpatan": { @@ -783,6 +6311,71 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1432]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fxtract": { @@ -790,6 +6383,110 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl x24, x21, #1", + "lsl x23, x23, x24", + "bic w22, w22, w23", + "strh w22, [x28, #1010]", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1360]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1368]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fprem1": { @@ -797,6 +6494,64 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1440]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdecstp": { @@ -804,6 +6559,12 @@ "Optimal": "Yes", "Comment": [ "0xd9 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fincstp": { @@ -811,6 +6572,12 @@ "Optimal": "Yes", "Comment": [ "0xd9 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fprem": { @@ -818,6 +6585,64 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1448]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fyl2xp1": { @@ -825,6 +6650,121 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "orr x20, xzr, #0x8000000000000000", + "orr w22, wzr, #0x3fff", + "fmov d6, x20", + "mov v6.16b, v6.16b", + "mov v6.d[1], x22", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v6.d[0]", + "umov w3, v6.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1424]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsqrt": { @@ -832,6 +6772,56 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1336]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsincos": { @@ -839,6 +6829,112 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl x24, x21, #1", + "lsl x23, x23, x24", + "bic w22, w22, w23", + "strh w22, [x28, #1010]", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1344]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v5.16b, v5.16b, v5.16b", + "mov v5.d[0], x0", + "mov v5.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1352]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w22, #0x0", + "strb w22, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "frndint": { @@ -846,6 +6942,56 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1312]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fscale": { @@ -853,6 +6999,62 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1456]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsin": { @@ -860,6 +7062,58 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1344]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcos": { @@ -867,6 +7121,58 @@ "Optimal": "No", "Comment": [ "0xd9 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1352]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fiadd dword [rax]": { @@ -874,6 +7180,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fimul dword [rax]": { @@ -881,6 +7282,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "ficom dword [rax]": { @@ -888,6 +7384,107 @@ "Optimal": "No", "Comment": [ "0xda !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "ficomp dword [rax]": { @@ -895,6 +7492,118 @@ "Optimal": "No", "Comment": [ "0xda !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fisub dword [rax]": { @@ -902,6 +7611,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fisubr dword [rax]": { @@ -909,6 +7713,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fidiv dword [rax]": { @@ -916,6 +7815,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fidivr dword [rax]": { @@ -923,6 +7917,101 @@ "Optimal": "No", "Comment": [ "0xda !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov w0, w21", + "ldr x1, [x28, #1304]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovb st0, st0": { @@ -930,6 +8019,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st1": { @@ -937,6 +8048,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st2": { @@ -944,6 +8077,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st3": { @@ -951,6 +8106,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st4": { @@ -958,6 +8135,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st5": { @@ -965,6 +8164,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st6": { @@ -972,6 +8193,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovb st0, st7": { @@ -979,6 +8222,28 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmove st0, st0": { @@ -986,6 +8251,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st1": { @@ -993,6 +8282,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st2": { @@ -1000,6 +8313,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st3": { @@ -1007,6 +8344,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st4": { @@ -1014,6 +8375,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st5": { @@ -1021,6 +8406,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st6": { @@ -1028,6 +8437,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmove st0, st7": { @@ -1035,6 +8468,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovbe st0, st0": { @@ -1042,6 +8499,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st1": { @@ -1049,6 +8530,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st2": { @@ -1056,6 +8561,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st3": { @@ -1063,6 +8592,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st4": { @@ -1070,6 +8623,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st5": { @@ -1077,6 +8654,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st6": { @@ -1084,6 +8685,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovbe st0, st7": { @@ -1091,6 +8716,30 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov w22, #0x0", + "mov x23, #0xffffffffffffffff", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovu st0, st0": { @@ -1098,6 +8747,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd8 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st1": { @@ -1105,6 +8781,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xd9 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st2": { @@ -1112,6 +8815,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xda /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st3": { @@ -1119,6 +8849,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xdb /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st4": { @@ -1126,6 +8883,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xdc /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st5": { @@ -1133,6 +8917,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xdd /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st6": { @@ -1140,6 +8951,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xde /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovu st0, st7": { @@ -1147,6 +8985,33 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xdf /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov w21, #0x0", + "mov x22, #0xffffffffffffffff", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fucompp": { @@ -1154,6 +9019,87 @@ "Optimal": "No", "Comment": [ "0xda 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x23, x22, x23", + "orr x21, x21, x23", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "uxth x21, w21", + "lsl x23, x20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fild dword [rax]": { @@ -1161,6 +9107,42 @@ "Optimal": "No", "Comment": [ "0xdf !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr w21, [x4]", + "mov w22, #0x0", + "sxtw x21, w21", + "orr w23, wzr, #0x8000", + "cmp x21, #0x0 (0)", + "csel x23, x23, x22, lt", + "cmp x21, #0x0 (0)", + "cneg x21, x21, mi", + "orr w24, wzr, #0x3f", + "mov x0, #0x3f", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w26, #0x403e", + "sub x24, x26, x24", + "cmp x21, #0x0 (0)", + "csel x21, x22, x24, eq", + "orr x21, x23, x21", + "fmov d4, x25", + "fmov d5, x21", + "mov v4.d[1], v5.d[0]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fisttp dword [rax]": { @@ -1168,6 +9150,64 @@ "Optimal": "No", "Comment": [ "0xdb !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1216]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w21, w0", + "str w21, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fist dword [rax]": { @@ -1175,6 +9215,53 @@ "Optimal": "No", "Comment": [ "0xdb !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1192]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w20, w0", + "str w20, [x4]" ] }, "fistp dword [rax]": { @@ -1182,6 +9269,64 @@ "Optimal": "No", "Comment": [ "0xdf !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1192]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w21, w0", + "str w21, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fld tword [rax]": { @@ -1189,6 +9334,21 @@ "Optimal": "No", "Comment": [ "0xdb !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr q4, [x4]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fstp tword [rax]": { @@ -1196,6 +9356,25 @@ "Optimal": "No", "Comment": [ "0xdb !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "str d4, [x4]", + "mov x21, v4.d[1]", + "strh w21, [x4, #8]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fcmovnb st0, st0": { @@ -1203,6 +9382,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st1": { @@ -1210,6 +9411,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st2": { @@ -1217,6 +9440,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st3": { @@ -1224,6 +9469,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st4": { @@ -1231,6 +9498,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st5": { @@ -1238,6 +9527,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st6": { @@ -1245,6 +9556,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnb st0, st7": { @@ -1252,6 +9585,28 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovne st0, st0": { @@ -1259,6 +9614,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st1": { @@ -1266,6 +9645,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st2": { @@ -1273,6 +9676,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st3": { @@ -1280,6 +9707,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st4": { @@ -1287,6 +9738,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st5": { @@ -1294,6 +9769,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st6": { @@ -1301,6 +9800,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovne st0, st7": { @@ -1308,6 +9831,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldr w21, [x28, #728]", + "ubfx x22, x21, #30, #1", + "orr x20, x20, x22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x22, x23, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x22, x20, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]", + "str w21, [x28, #728]" ] }, "fcmovnbe st0, st0": { @@ -1315,6 +9862,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st1": { @@ -1322,6 +9893,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x1 (1)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st2": { @@ -1329,6 +9924,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x2 (2)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st3": { @@ -1336,6 +9955,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st4": { @@ -1343,6 +9986,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x4 (4)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st5": { @@ -1350,6 +10017,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x5 (5)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st6": { @@ -1357,6 +10048,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x6 (6)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnbe st0, st7": { @@ -1364,6 +10079,30 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx x21, x20, #29, #1", + "ubfx x22, x20, #30, #1", + "orr w21, w21, w22, lsl #6", + "mov x22, #0xffffffffffffffff", + "mov w23, #0x0", + "cmp x21, #0x0 (0)", + "csel x21, x22, x23, eq", + "dup v4.2d, x21", + "ldrb w21, [x28, #747]", + "add x22, x21, #0x7 (7)", + "and x22, x22, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x22, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "str w20, [x28, #728]" ] }, "fcmovnu st0, st0": { @@ -1371,6 +10110,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st1": { @@ -1378,6 +10144,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st2": { @@ -1385,6 +10178,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st3": { @@ -1392,6 +10212,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st4": { @@ -1399,6 +10246,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st5": { @@ -1406,6 +10280,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st6": { @@ -1413,6 +10314,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcmovnu st0, st7": { @@ -1420,6 +10348,33 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "orr w21, wzr, #0x1", + "ldrb w22, [x28, #706]", + "fmov s4, w22", + "cnt v4.16b, v4.16b", + "umov w22, v4.b[0]", + "and x21, x21, x22", + "orr x20, x20, x21, lsl #2", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x0", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "dup v4.2d, x20", + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q6, [x0, #752]", + "mov v0.16b, v4.16b", + "bsl v0.16b, v6.16b, v5.16b", + "mov v4.16b, v0.16b", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fnclex": { @@ -1427,13 +10382,65 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xe2 /4" - ] + ], + "ExpectedArm64ASM": [] }, "fninit": { "ExpectedInstructionCount": 49, "Optimal": "No", "Comment": [ "0xdb 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, #0x37f", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w21", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w21, [x28, #1008]", + "strb w20, [x28, #747]", + "strb w20, [x28, #744]", + "strb w20, [x28, #745]", + "strb w20, [x28, #746]", + "strb w20, [x28, #750]", + "orr w20, wzr, #0xffff", + "strh w20, [x28, #1010]" ] }, "fucomi st0, st0": { @@ -1441,6 +10448,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st1": { @@ -1448,6 +10519,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st2": { @@ -1455,6 +10590,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st3": { @@ -1462,6 +10661,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st4": { @@ -1469,6 +10732,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st5": { @@ -1476,6 +10803,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st6": { @@ -1483,6 +10874,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fucomi st0, st7": { @@ -1490,6 +10945,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st0": { @@ -1497,6 +11016,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st1": { @@ -1504,6 +11087,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st2": { @@ -1511,6 +11158,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st3": { @@ -1518,6 +11229,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st4": { @@ -1525,6 +11300,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st5": { @@ -1532,6 +11371,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st6": { @@ -1539,6 +11442,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fcomi st0, st7": { @@ -1546,6 +11513,70 @@ "Optimal": "No", "Comment": [ "0xdb 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "lsr w21, w0, #0", + "bfi w21, w22, #30, #1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" ] }, "fadd qword [rax]": { @@ -1553,6 +11584,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fmul qword [rax]": { @@ -1560,6 +11686,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fcom qword [rax]": { @@ -1567,6 +11788,107 @@ "Optimal": "No", "Comment": [ "0xdc !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fcomp qword [rax]": { @@ -1574,6 +11896,118 @@ "Optimal": "No", "Comment": [ "0xdc !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fsub qword [rax]": { @@ -1581,6 +12015,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr qword [rax]": { @@ -1588,6 +12117,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv qword [rax]": { @@ -1595,6 +12219,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr qword [rax]": { @@ -1602,6 +12321,101 @@ "Optimal": "No", "Comment": [ "0xdc !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xc0": { @@ -1611,6 +12425,62 @@ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st1, st0": { @@ -1618,6 +12488,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st2, st0": { @@ -1625,6 +12551,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st3, st0": { @@ -1632,6 +12614,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st4, st0": { @@ -1639,6 +12677,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st5, st0": { @@ -1646,6 +12740,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st6, st0": { @@ -1653,6 +12803,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fadd st7, st0": { @@ -1660,6 +12866,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xc8": { @@ -1669,6 +12931,62 @@ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st1, st0": { @@ -1676,6 +12994,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st2, st0": { @@ -1683,6 +13057,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st3, st0": { @@ -1690,6 +13120,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st4, st0": { @@ -1697,6 +13183,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st5, st0": { @@ -1704,6 +13246,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st6, st0": { @@ -1711,6 +13309,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmul st7, st0": { @@ -1718,6 +13372,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xe0": { @@ -1727,6 +13437,62 @@ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st1, st0": { @@ -1734,6 +13500,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st2, st0": { @@ -1741,6 +13563,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st3, st0": { @@ -1748,6 +13626,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st4, st0": { @@ -1755,6 +13689,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st5, st0": { @@ -1762,6 +13752,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st6, st0": { @@ -1769,6 +13815,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubr st7, st0": { @@ -1776,6 +13878,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xe8": { @@ -1785,6 +13943,62 @@ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st1, st0": { @@ -1792,6 +14006,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st2, st0": { @@ -1799,6 +14069,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st3, st0": { @@ -1806,6 +14132,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st4, st0": { @@ -1813,6 +14195,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st5, st0": { @@ -1820,6 +14258,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st6, st0": { @@ -1827,6 +14321,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsub st7, st0": { @@ -1834,6 +14384,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xf0": { @@ -1843,6 +14449,62 @@ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st1, st0": { @@ -1850,6 +14512,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st2, st0": { @@ -1857,6 +14575,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st3, st0": { @@ -1864,6 +14638,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st4, st0": { @@ -1871,6 +14701,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st5, st0": { @@ -1878,6 +14764,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st6, st0": { @@ -1885,6 +14827,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivr st7, st0": { @@ -1892,6 +14890,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xdc, 0xf8": { @@ -1901,6 +14955,62 @@ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xdc 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st1, st0": { @@ -1908,6 +15018,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st2, st0": { @@ -1915,6 +15081,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st3, st0": { @@ -1922,6 +15144,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st4, st0": { @@ -1929,6 +15207,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st5, st0": { @@ -1936,6 +15270,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st6, st0": { @@ -1943,6 +15333,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdiv st7, st0": { @@ -1950,6 +15396,62 @@ "Optimal": "No", "Comment": [ "0xdc 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fld qword [rax]": { @@ -1957,6 +15459,63 @@ "Optimal": "No", "Comment": [ "0xdd !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v4.8b", + "ldr x0, [x28, #1160]", + "blr x0", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fisttp qword [rax]": { @@ -1964,6 +15523,64 @@ "Optimal": "No", "Comment": [ "0xdd !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1224]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "str x21, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fst qword [rax]": { @@ -1971,6 +15588,53 @@ "Optimal": "No", "Comment": [ "0xdd !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1176]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v4.8b, v0.8b", + "str d4, [x4]" ] }, "fstp qword [rax]": { @@ -1978,6 +15642,64 @@ "Optimal": "No", "Comment": [ "0xdd !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1176]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v4.8b, v0.8b", + "str d4, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "frstor [rax]": { @@ -1985,6 +15707,122 @@ "Optimal": "No", "Comment": [ "0xdd !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w20", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx x21, x20, #11, #3", + "strb w21, [x28, #747]", + "ubfx x22, x20, #8, #1", + "ubfx x23, x20, #9, #1", + "ubfx x24, x20, #10, #1", + "ubfx x20, x20, #14, #1", + "strb w22, [x28, #744]", + "strb w23, [x28, #745]", + "strb w24, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "strh w20, [x28, #1010]", + "add x20, x4, #0x1c (28)", + "mov x22, #0xffffffffffffffff", + "orr w23, wzr, #0xffff", + "fmov d4, x22", + "mov v4.16b, v4.16b", + "mov v4.d[1], x23", + "ldur q5, [x4, #28]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x22, x20, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x20, #10]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x20, x22, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x22, #10]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x22, x20, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x20, #10]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x20, x22, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x22, #10]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x22, x20, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x20, #10]", + "and v5.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q5, [x0, #752]", + "add x20, x22, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur q5, [x22, #10]", + "and v4.16b, v5.16b, v4.16b", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "add x22, x20, #0xa (10)", + "add x21, x21, #0x1 (1)", + "and x21, x21, #0x7", + "ldur d4, [x20, #10]", + "ldr h5, [x22, #8]", + "mov v4.h[4], v5.h[0]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fnsave [rax]": { @@ -1992,6 +15830,129 @@ "Optimal": "No", "Comment": [ "0xdd !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1008]", + "str w21, [x4]", + "mov w21, #0x0", + "lsl w22, w20, #11", + "orr x22, x21, x22", + "ldrb w23, [x28, #744]", + "ldrb w24, [x28, #745]", + "ldrb w25, [x28, #746]", + "ldrb w26, [x28, #750]", + "lsl w23, w23, #8", + "orr x22, x22, x23", + "lsl w23, w24, #9", + "orr x22, x22, x23", + "lsl w23, w25, #10", + "orr x22, x22, x23", + "lsl w23, w26, #14", + "orr x22, x22, x23", + "str w22, [x4, #4]", + "ldrh w22, [x28, #1010]", + "str w22, [x4, #8]", + "str w21, [x4, #12]", + "str w21, [x4, #16]", + "str w21, [x4, #20]", + "str w21, [x4, #24]", + "add x22, x4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x4, #28]", + "add x23, x22, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x22, #10]", + "add x22, x23, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x23, #10]", + "add x23, x22, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x22, #10]", + "add x22, x23, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x23, #10]", + "add x23, x22, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x22, #10]", + "add x22, x23, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur q4, [x23, #10]", + "add x23, x22, #0xa (10)", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stur d4, [x22, #10]", + "dup v4.8h, v4.h[4]", + "str h4, [x23, #8]", + "mov w20, #0x37f", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "uxth w0, w20", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "strh w20, [x28, #1008]", + "strb w21, [x28, #747]", + "strb w21, [x28, #744]", + "strb w21, [x28, #745]", + "strb w21, [x28, #746]", + "strb w21, [x28, #750]", + "orr w20, wzr, #0xffff", + "strh w20, [x28, #1010]" ] }, "fnstsw [rax]": { @@ -1999,6 +15960,25 @@ "Optimal": "No", "Comment": [ "0xdd !11b /7" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "lsl w21, w21, #11", + "orr x20, x20, x21", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "lsl w21, w21, #8", + "orr x20, x20, x21", + "lsl w21, w22, #9", + "orr x20, x20, x21", + "lsl w21, w23, #10", + "orr x20, x20, x21", + "lsl w21, w24, #14", + "orr x20, x20, x21", + "strh w20, [x4]" ] }, "ffree st0": { @@ -2006,6 +15986,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x0 (0)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st1": { @@ -2013,6 +16006,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st2": { @@ -2020,6 +16026,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x2 (2)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st3": { @@ -2027,6 +16046,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x20, x20, #0x3 (3)", + "and x20, x20, #0x7", + "ldrh w22, [x28, #1010]", + "lsl x20, x20, #1", + "lsl x23, x21, x20", + "bic w22, w22, w23", + "lsl x20, x21, x20", + "orr x20, x22, x20", + "strh w20, [x28, #1010]" ] }, "ffree st4": { @@ -2034,6 +16066,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x4 (4)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st5": { @@ -2041,6 +16086,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x5 (5)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st6": { @@ -2048,6 +16106,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x6 (6)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "ffree st7": { @@ -2055,6 +16126,19 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x7 (7)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x20, x20, #1", + "lsl x23, x22, x20", + "bic w21, w21, w23", + "lsl x20, x22, x20", + "orr x20, x21, x20", + "strh w20, [x28, #1010]" ] }, "fst st0": { @@ -2062,6 +16146,15 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st1": { @@ -2069,6 +16162,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st2": { @@ -2076,6 +16178,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st3": { @@ -2083,6 +16194,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st4": { @@ -2090,6 +16210,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st5": { @@ -2097,6 +16226,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st6": { @@ -2104,6 +16242,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fst st7": { @@ -2111,6 +16258,15 @@ "Optimal": "Yes", "Comment": [ "0xdd 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fstp st0": { @@ -2118,6 +16274,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st1": { @@ -2125,6 +16301,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st2": { @@ -2132,6 +16328,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st3": { @@ -2139,6 +16355,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]", + "ldrh w22, [x28, #1010]", + "lsl w23, w20, #1", + "lsl x24, x21, x23", + "bic w22, w22, w24", + "lsl x21, x21, x23", + "orr x21, x22, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st4": { @@ -2146,6 +16382,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st5": { @@ -2153,6 +16409,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st6": { @@ -2160,6 +16436,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fstp st7": { @@ -2167,6 +16463,26 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucom st0": { @@ -2174,6 +16490,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" ] }, "fucom st1": { @@ -2181,6 +16559,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st2": { @@ -2188,6 +16628,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st3": { @@ -2195,6 +16697,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x3 (3)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st4": { @@ -2202,6 +16766,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st5": { @@ -2209,6 +16835,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st6": { @@ -2216,6 +16904,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucom st7": { @@ -2223,6 +16973,68 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "fucomp st0": { @@ -2230,6 +17042,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add x22, x20, #0x0 (0)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st1": { @@ -2237,6 +17122,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st2": { @@ -2244,6 +17202,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st3": { @@ -2251,6 +17282,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrh w22, [x28, #1010]", + "lsl w23, w20, #1", + "lsl x24, x21, x23", + "bic w22, w22, w24", + "lsl x21, x21, x23", + "orr x21, x22, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st4": { @@ -2258,6 +17362,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st5": { @@ -2265,6 +17442,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st6": { @@ -2272,6 +17522,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fucomp st7": { @@ -2279,6 +17602,79 @@ "Optimal": "No", "Comment": [ "0xdd 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fiadd word [rax]": { @@ -2286,6 +17682,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fimul word [rax]": { @@ -2293,6 +17784,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "ficom word [rax]": { @@ -2300,6 +17886,107 @@ "Optimal": "No", "Comment": [ "0xde !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" ] }, "ficomp word [rax]": { @@ -2307,6 +17994,118 @@ "Optimal": "No", "Comment": [ "0xde !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fisub word [rax]": { @@ -2314,6 +18113,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fisubr word [rax]": { @@ -2321,6 +18215,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fidiv word [rax]": { @@ -2328,6 +18317,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fidivr word [rax]": { @@ -2335,6 +18419,101 @@ "Optimal": "No", "Comment": [ "0xde !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "sxth w0, w21", + "ldr x1, [x28, #1296]", + "blr x1", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st0": { @@ -2342,6 +18521,73 @@ "Optimal": "No", "Comment": [ "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st1": { @@ -2349,6 +18595,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st2": { @@ -2356,6 +18669,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st3": { @@ -2363,6 +18743,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st4": { @@ -2370,6 +18817,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st5": { @@ -2377,6 +18891,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st6": { @@ -2384,6 +18965,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "faddp st7": { @@ -2391,6 +19039,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1392]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st0": { @@ -2398,6 +19113,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st1": { @@ -2405,6 +19187,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st2": { @@ -2412,6 +19261,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st3": { @@ -2419,6 +19335,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st4": { @@ -2426,6 +19409,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st5": { @@ -2433,6 +19483,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st6": { @@ -2440,6 +19557,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fmulp st7": { @@ -2447,6 +19631,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1408]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fcompp": { @@ -2454,6 +19705,87 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x23, x22, x23", + "orr x21, x21, x23", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "uxth x21, w21", + "lsl x23, x20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "db 0xde, 0xe0": { @@ -2463,6 +19795,73 @@ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xde 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st1, st0": { @@ -2470,6 +19869,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st2, st0": { @@ -2477,6 +19943,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st3, st0": { @@ -2484,6 +20017,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st4, st0": { @@ -2491,6 +20091,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st5, st0": { @@ -2498,6 +20165,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st6, st0": { @@ -2505,6 +20239,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubrp st7, st0": { @@ -2512,6 +20313,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xde, 0xe8": { @@ -2521,6 +20389,73 @@ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xde 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st1, st0": { @@ -2528,6 +20463,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st2, st0": { @@ -2535,6 +20537,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st3, st0": { @@ -2542,6 +20611,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st4, st0": { @@ -2549,6 +20685,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st5, st0": { @@ -2556,6 +20759,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st6, st0": { @@ -2563,6 +20833,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fsubp st7, st0": { @@ -2570,6 +20907,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1400]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xde, 0xf0": { @@ -2579,6 +20983,73 @@ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xde 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st1, st0": { @@ -2586,6 +21057,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st2, st0": { @@ -2593,6 +21131,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st3, st0": { @@ -2600,6 +21205,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st4, st0": { @@ -2607,6 +21279,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st5, st0": { @@ -2614,6 +21353,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st6, st0": { @@ -2621,6 +21427,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivrp st7, st0": { @@ -2628,6 +21501,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "db 0xde, 0xf8": { @@ -2637,6 +21577,73 @@ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", "0xde 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st1, st0": { @@ -2644,6 +21651,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st2, st0": { @@ -2651,6 +21725,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st3, st0": { @@ -2658,6 +21799,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w23, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w23, w23, w25", + "lsl x21, x21, x24", + "orr x21, x23, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st4, st0": { @@ -2665,6 +21873,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st5, st0": { @@ -2672,6 +21947,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st6, st0": { @@ -2679,6 +22021,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fdivp st7, st0": { @@ -2686,6 +22095,73 @@ "Optimal": "No", "Comment": [ "0xde 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "mov x2, v5.d[0]", + "umov w3, v5.h[4]", + "ldr x4, [x28, #1416]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "ldrh w22, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w22, w22, w25", + "lsl x23, x23, x24", + "orr x22, x22, x23", + "strh w22, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q4, [x0, #752]" ] }, "fild word [rax]": { @@ -2693,6 +22169,42 @@ "Optimal": "No", "Comment": [ "0xdf !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldrh w21, [x4]", + "mov w22, #0x0", + "sxth x21, w21", + "orr w23, wzr, #0x8000", + "cmp x21, #0x0 (0)", + "csel x23, x23, x22, lt", + "cmp x21, #0x0 (0)", + "cneg x21, x21, mi", + "orr w24, wzr, #0x3f", + "mov x0, #0x3f", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w26, #0x403e", + "sub x24, x26, x24", + "cmp x21, #0x0 (0)", + "csel x21, x22, x24, eq", + "orr x21, x23, x21", + "fmov d4, x25", + "fmov d5, x21", + "mov v4.d[1], v5.d[0]", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fisttp word [rax]": { @@ -2700,6 +22212,64 @@ "Optimal": "No", "Comment": [ "0xdf !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1208]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x21, w0", + "strh w21, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fist word [rax]": { @@ -2707,6 +22277,53 @@ "Optimal": "No", "Comment": [ "0xdf !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1184]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x20, w0", + "strh w20, [x4]" ] }, "fistp word [rax]": { @@ -2714,6 +22331,64 @@ "Optimal": "No", "Comment": [ "0xdf !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1184]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x21, w0", + "strh w21, [x4]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fbld tword [rax]": { @@ -2721,6 +22396,64 @@ "Optimal": "No", "Comment": [ "0xdf !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl x23, x20, #1", + "lsl x22, x22, x23", + "bic w21, w21, w22", + "strh w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr q4, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1384]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q4, [x0, #752]" ] }, "fbstp tword [rax]": { @@ -2728,6 +22461,68 @@ "Optimal": "No", "Comment": [ "0xdf !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q4, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v4.d[0]", + "umov w1, v4.h[4]", + "ldr x2, [x28, #1376]", + "blr x2", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v4.16b, v4.16b, v4.16b", + "mov v4.d[0], x0", + "mov v4.h[4], w1", + "str d4, [x4]", + "mov x21, v4.d[1]", + "strh w21, [x4, #8]", + "ldrh w21, [x28, #1010]", + "orr w22, wzr, #0x3", + "lsl w23, w20, #1", + "lsl x24, x22, x23", + "bic w21, w21, w24", + "lsl x22, x22, x23", + "orr x21, x21, x22", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st0": { @@ -2735,6 +22530,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st1": { @@ -2742,6 +22543,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st2": { @@ -2749,6 +22556,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st3": { @@ -2756,6 +22569,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st4": { @@ -2763,6 +22582,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st5": { @@ -2770,6 +22595,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st6": { @@ -2777,6 +22608,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "ffreep st7": { @@ -2784,6 +22621,12 @@ "Optimal": "Yes", "Comment": [ "0xdf 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]" ] }, "fnstsw ax": { @@ -2791,6 +22634,25 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "lsl w21, w21, #11", + "orr x20, x20, x21", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "lsl w21, w21, #8", + "orr x20, x20, x21", + "lsl w21, w22, #9", + "orr x20, x20, x21", + "lsl w21, w23, #10", + "orr x20, x20, x21", + "lsl w21, w24, #14", + "orr x20, x20, x21", + "bfxil x4, x20, #0, #16" ] }, "fucomip st0": { @@ -2798,6 +22660,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st1": { @@ -2805,6 +22742,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st2": { @@ -2812,6 +22824,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st3": { @@ -2819,6 +22906,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "ldr w25, [x28, #728]", + "mov w0, w25", + "bfi w0, w23, #29, #1", + "lsr w23, w0, #0", + "bfi w23, w24, #30, #1", + "strb w22, [x28, #706]", + "ldrh w22, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w22, w22, w25", + "lsl x21, x21, x24", + "orr x21, x22, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" ] }, "fucomip st4": { @@ -2826,6 +22988,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st5": { @@ -2833,6 +23070,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st6": { @@ -2840,6 +23152,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fucomip st7": { @@ -2847,6 +23234,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st0": { @@ -2854,6 +23316,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x0 (0)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st1": { @@ -2861,6 +23398,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x1 (1)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st2": { @@ -2868,6 +23480,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x2 (2)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st3": { @@ -2875,6 +23562,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "orr w21, wzr, #0x3", + "add x22, x20, #0x3 (3)", + "and x22, x22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "ldr w25, [x28, #728]", + "mov w0, w25", + "bfi w0, w23, #29, #1", + "lsr w23, w0, #0", + "bfi w23, w24, #30, #1", + "strb w22, [x28, #706]", + "ldrh w22, [x28, #1010]", + "lsl w24, w20, #1", + "lsl x25, x21, x24", + "bic w22, w22, w25", + "lsl x21, x21, x24", + "orr x21, x22, x21", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" ] }, "fcomip st4": { @@ -2882,6 +23644,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x4 (4)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st5": { @@ -2889,6 +23726,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x5 (5)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st6": { @@ -2896,6 +23808,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x6 (6)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] }, "fcomip st7": { @@ -2903,6 +23890,81 @@ "Optimal": "No", "Comment": [ "0xdf 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x21, x20, #0x7 (7)", + "and x21, x21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q5, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xd0 (208)", + "mov x0, sp", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov x0, v5.d[0]", + "umov w1, v5.h[4]", + "mov x2, v4.d[0]", + "umov w3, v4.h[4]", + "ldr x4, [x28, #1288]", + "blr x4", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "ldr w24, [x28, #728]", + "mov w0, w24", + "bfi w0, w22, #29, #1", + "lsr w22, w0, #0", + "bfi w22, w23, #30, #1", + "strb w21, [x28, #706]", + "ldrh w21, [x28, #1010]", + "orr w23, wzr, #0x3", + "lsl w24, w20, #1", + "lsl x25, x23, x24", + "bic w21, w21, w25", + "lsl x23, x23, x24", + "orr x21, x21, x23", + "strh w21, [x28, #1010]", + "add x20, x20, #0x1 (1)", + "and x20, x20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" ] } }