diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 1fc1c85ba..6ae6b3425 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -4410,19 +4410,14 @@
       ]
     },
     "pmaddwd mm0, mm1": {
-      "ExpectedInstructionCount": 10,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 5,
+      "Optimal": "Yes",
       "Comment": "0x0f 0xf5",
       "ExpectedArm64ASM": [
         "ldr d4, [x28, #752]",
         "ldr d5, [x28, #768]",
-        "sxtl v6.4s, v4.4h",
-        "sxtl2 v4.4s, v4.8h",
-        "sxtl v7.4s, v5.4h",
-        "sxtl2 v5.4s, v5.8h",
-        "mul v6.4s, v6.4s, v7.4s",
-        "mul v4.4s, v4.4s, v5.4s",
-        "addp v4.4s, v6.4s, v4.4s",
+        "smull v4.4s, v4.4h, v5.4h",
+        "addp v4.4s, v4.4s, v4.4s",
         "str d4, [x28, #752]"
       ]
     },
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index 8f35fcc78..b865b269c 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -1087,16 +1087,12 @@
       ]
     },
     "pmaddwd xmm0, xmm1": {
-      "ExpectedInstructionCount": 7,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 3,
+      "Optimal": "Yes",
       "Comment": "0x66 0x0f 0xf5",
       "ExpectedArm64ASM": [
-        "sxtl v4.4s, v16.4h",
-        "sxtl2 v5.4s, v16.8h",
-        "sxtl v6.4s, v17.4h",
-        "sxtl2 v7.4s, v17.8h",
-        "mul v4.4s, v4.4s, v6.4s",
-        "mul v5.4s, v5.4s, v7.4s",
+        "smull v4.4s, v16.4h, v17.4h",
+        "smull2 v5.4s, v16.8h, v17.8h",
         "addp v16.4s, v4.4s, v5.4s"
       ]
     },
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 6efc8e810..ed00fb3be 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -6863,7 +6863,7 @@
       ]
     },
     "vpmaddwd xmm0, xmm1, xmm2": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 7,
       "Optimal": "No",
       "Comment": [
         "Map 1 0b01 0xf5 128-bit"
@@ -6871,12 +6871,8 @@
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
         "mov z5.d, p7/m, z18.d",
-        "sxtl v6.4s, v4.4h",
-        "sxtl2 v4.4s, v4.8h",
-        "sxtl v7.4s, v5.4h",
-        "sxtl2 v5.4s, v5.8h",
-        "mul v6.4s, v6.4s, v7.4s",
-        "mul v4.4s, v4.4s, v5.4s",
+        "smull v6.4s, v4.4h, v5.4h",
+        "smull2 v4.4s, v4.8h, v5.8h",
         "addp v4.4s, v6.4s, v4.4s",
         "mov v4.16b, v4.16b",
         "mov z16.d, p7/m, z4.d"
@@ -6891,12 +6887,12 @@
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
         "mov z5.d, p7/m, z18.d",
-        "sunpklo z6.s, z4.h",
-        "sunpkhi z4.s, z4.h",
-        "sunpklo z7.s, z5.h",
-        "sunpkhi z5.s, z5.h",
-        "mul z6.s, z6.s, z7.s",
-        "mul z4.s, z4.s, z5.s",
+        "smullb z0.s, z4.h, z5.h",
+        "smullt z1.s, z4.h, z5.h",
+        "zip1 z6.s, z0.s, z1.s",
+        "smullb z0.s, z4.h, z5.h",
+        "smullt z1.s, z4.h, z5.h",
+        "zip2 z4.s, z0.s, z1.s",
         "movprfx z0, z6",
         "addp z0.s, p7/m, z0.s, z4.s",
         "uzp1 z4.s, z0.s, z0.s",