diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 125b90822..803a5a607 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5880,6 +5880,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
 
     {OPD(1, 0b00, 0x5E), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFDIV, 4>},
     {OPD(1, 0b01, 0x5E), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFDIV, 8>},
+    {OPD(1, 0b10, 0x5E), 1, &OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFDIV, 4>},
 
     {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMAX, 4>},
     {OPD(1, 0b01, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFMAX, 8>},
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index 48b67b04f..3db80e84c 100644
--- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -572,6 +572,8 @@ void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFADD, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFADD, 8>(OpcodeArgs);
 template
+void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFDIV, 4>(OpcodeArgs);
+template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMAX, 4>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorScalarALUOp<IR::OP_VFMAX, 8>(OpcodeArgs);
diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
index 0ca7ac841..519e720cc 100644
--- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
+++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -162,7 +162,7 @@ void InitializeVEXTables() {
 
     {OPD(1, 0b00, 0x5E), 1, X86InstInfo{"VDIVPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0x5E), 1, X86InstInfo{"VDIVPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x5E), 1, X86InstInfo{"VDIVSS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b10, 0x5E), 1, X86InstInfo{"VDIVSS",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b11, 0x5E), 1, X86InstInfo{"VDIVSD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
     {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
diff --git a/unittests/ASM/VEX/vdivss.asm b/unittests/ASM/VEX/vdivss.asm
new file mode 100644
index 000000000..33f59d34b
--- /dev/null
+++ b/unittests/ASM/VEX/vdivss.asm
@@ -0,0 +1,70 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x414243443E800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM1": ["0x4142434440800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM2": ["0x414243443F100000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM3": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM4": ["0x4142434441C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5": ["0x4142434440C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM7": ["0x414243443F23D70A", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
+    "XMM8": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"],
+    "XMM9": ["0x4142434441C80000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+vmovapd ymm0, [rdx + 32 * 0]
+vmovapd ymm1, [rdx + 32 * 1]
+vmovapd ymm2, [rdx + 32 * 2]
+vmovapd ymm3, [rdx + 32 * 3]
+vmovapd ymm4, [rdx + 32 * 4]
+
+; Register only
+vdivss xmm0, xmm0, xmm1
+vdivss xmm2, xmm2, xmm3
+
+; Memory operand
+vdivss xmm5, xmm4, [rdx + 32 * 1]
+vdivss xmm4, xmm4, [rdx + 32 * 0]
+
+; Merging different src into destination
+vpxor xmm7, xmm7, xmm7
+vmovapd ymm8, [rdx + 32 * 3]
+vmovapd ymm9, [rdx + 32 * 4]
+vdivss xmm7, xmm8, xmm9
+
+hlt
+
+align 32
+.data:
+dq 0x414243443F800000 ; 1.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434440800000 ; 4.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441100000 ; 9.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441800000 ; 16.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758
+
+dq 0x4142434441C80000 ; 25.0
+dq 0x5152535455565758
+dq 0x5152535455565758
+dq 0x5152535455565758