lioncash
122aa8a69a
Arm64/VectorOps: Simplify FADDP result merging
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Keeps the implementation similarly in sync with VAddP.
2022-12-16 04:19:46 +00:00
Ryan Houdek
8ce6c08152
Merge pull request #2251 from lioncash/hadd
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OpcodeDispatcher: Handle VPHADDW/VPHADDD
2022-12-15 20:11:07 -08:00
lioncash
27c0d4a9f5
OpcodeDispatcher: Handle VPHADDD
2022-12-16 03:28:57 +00:00
lioncash
dd4ba7562f
OpcodeDispatcher: Handle VPHADDW
2022-12-16 03:28:57 +00:00
lioncash
bd9d8e8fe5
x86_64: Correct handling for 128-bit/256-bit VAddP
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Makes the behavior consistent with the ARM JIT.
2022-12-16 03:28:57 +00:00
lioncash
c7ac204322
Arm64/VectorOps: Simplify VAddP merging operation
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We can just merge the two results together instead of shifting to the
left and then ORing together.
2022-12-16 03:28:52 +00:00
lioncash
5e634fcbc9
Crypto: Explicitly clear upper lane with VPCLMULQDQ
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Ensures the 128-bit case will be handled when extending for 256-bit
2022-12-16 01:08:48 +00:00
lioncash
e985dcdb22
X86Tables: Restrict CVTTSD2SI src to 64 bit
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When accessing memory, this should only be doing a 64-bit access, rather
than a 128-bit one.
2022-12-15 23:59:15 +00:00
lioncash
ee9778480d
X86Tables: Restrict CVTDQ2PD src to 64 bit
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When accessing memory, this should only be doing a 64-bit access, rather
than a 128-bit one.
2022-12-15 23:46:48 +00:00
Mai
048daa4579
Merge pull request #2244 from Sonicadvance1/move_to_header
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ARM64: Moves RA functions to header
2022-12-15 23:13:32 +00:00
Ryan Houdek
6ae8a1e55f
ARM64: Moves RA functions to header
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These are just some basic address calculations and a load, we want these
to be inlined as much as possible.
2022-12-15 15:00:33 -08:00
Ryan Houdek
dc2eaf6511
Merge pull request #2246 from lioncash/extend
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OpcodeDispatcher: Handle VPMOVSXB{D, W, Q}/VPMOVSXW{D, Q}/VPMOVSXDQ/VPMOVZXB{D, W, Q}/VPMOVZXW{D, Q}/VPMOVZXDQ
2022-12-15 14:19:28 -08:00
lioncash
ba5fafcd7f
OpcodeDispatcher: Narrow memory access with scalar rounding operations
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These should only be accessing a 32-bit or 64-bit portion of memory
depending on single or double precision variants are used. Previously
we'd be doing a full 128-bit load.
2022-12-15 19:42:37 +00:00
lioncash
b12503fe32
OpcodeDispatcher: Handle VPMOVSXDQ
2022-12-15 18:10:38 +00:00
lioncash
aa63c7b94d
OpcodeDispatcher: Handle VPMOVSXWQ
2022-12-15 18:08:00 +00:00
lioncash
cccbb7f595
OpcodeDispatcher: Handle VPMOVSXWD
2022-12-15 18:01:43 +00:00
lioncash
ce12ed60ae
OpcodeDispatcher: Handle VPMOVSXBQ
2022-12-15 17:58:42 +00:00
lioncash
d7eab5f787
OpcodeDispatcher: Handle VPMOVSXBD
2022-12-15 17:54:51 +00:00
lioncash
21537a3636
OpcodeDispatcher: Handle VPMOVSXBW
2022-12-15 17:50:58 +00:00
lioncash
588a2611a7
OpcodeDispatcher: Handle VPMOVZXDQ
2022-12-15 17:45:14 +00:00
lioncash
2895a09101
OpcodeDispatcher: Handle VPMOVZXWQ
2022-12-15 17:41:15 +00:00
lioncash
5c8d40d9be
OpcodeDispatcher: Handle VPMOVZXWD
2022-12-15 17:37:51 +00:00
lioncash
b4079cfea3
OpcodeDispatcher: Handle VPMOVZXBQ
2022-12-15 17:32:18 +00:00
lioncash
2b5570a910
OpcodeDispatcher: Handle VPMOVZXBD
2022-12-15 17:28:35 +00:00
lioncash
6bb0c5b24c
OpcodeDispatcher: Handle VPMOVZXBW
2022-12-15 17:18:49 +00:00
lioncash
bc31f98f16
OpcodeDispatcher: Move ExtendVectorElements impl to regular function
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This can be reused for the AVX versions.
2022-12-15 17:11:02 +00:00
lioncash
58c3e20bd1
OpcodeDispatcher: Move template impl to regular function where applicable
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Reduces the amount of code size generated by the specializations.
Only targets ones that are heavily templated like the generic op helper
functions.
2022-12-15 01:54:12 +00:00
lioncash
27ea6096a2
OpcodeDispatcher: Handle VROUNDSD
2022-12-14 06:41:36 +00:00
lioncash
2244dd9847
OpcodeDispatcher: Handle VROUNDSS
2022-12-14 06:34:58 +00:00
lioncash
ca2f4bd468
OpcodeDispatcher: Handle VROUNDPD
2022-12-14 06:28:17 +00:00
lioncash
6b5c94be23
OpcodeDispatcher: Handle VROUNDPS
2022-12-14 06:27:59 +00:00
lioncash
779dc48d8d
OpcodeDispatcher: Factor out VectorRound into VectorRoundImpl
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This will be used in following commits for the AVX versions that use
this.
2022-12-14 05:52:16 +00:00
lioncash
90828aeb11
OpcodeDispatcher: Handle VINSERTI128
2022-12-14 04:26:42 +00:00
lioncash
fe7c6da1e2
OpcodeDispatcher: Handle VINSERTF128
2022-12-14 04:24:04 +00:00
lioncash
a9ad0d081c
OpcodeDispatcher: Handle VPERM2I128
2022-12-14 03:41:29 +00:00
lioncash
54885bec32
OpcodeDispatcher: Handle VPERM2F128
2022-12-14 03:41:22 +00:00
lioncash
8a961bfcc5
VEXTables: Specify VPERMQ/VPERMPD as 256-bit
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The AVX versions of these operands only operate on 256-bit ymm
registers, so we can specify this directly to be a little more
self-documenting.
2022-12-14 01:51:36 +00:00
lioncash
d6ab7a4f97
Frontend: Handle 256-bit destination sizes directly
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Previously the only time we'd promote to a 256-bit size is if the VEX.L
bit was set in the 128-bit path.
Allow specifying 256-bit sizes directly.
2022-12-14 01:50:05 +00:00
lioncash
7114fb3293
OpcodeDispatcher: Handle VPERMPD
2022-12-14 01:37:27 +00:00
lioncash
8a87aff730
OpcodeDispatcher: Handle VPERMQ
2022-12-14 01:30:55 +00:00
lioncash
c5b4719793
OpcodeDispatcher: Handle VHADDPD
2022-12-13 23:45:42 +00:00
lioncash
0f6201108f
OpcodeDispatcher: Handle VHADDPS
2022-12-13 23:45:38 +00:00
lioncash
b589dce7f5
x86_64/VectorOps: Make VFADDP behavior consistent with ARMv8
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We need to swap the second and third results to be consistent with ARM.
Also fixes the mistake where I used vhaddpd instead of vhaddps in the
single-precision 256-bit case.
2022-12-13 23:34:12 +00:00
lioncash
c98fffd33d
OpcodeDispatcher: Handle VPMAXSD
2022-12-13 21:49:40 +00:00
lioncash
de3777cc78
OpcodeDispatcher: Handle VPMAXSW
2022-12-13 21:47:17 +00:00
lioncash
dd640e7a3d
OpcodeDispatcher: Handle VPMAXSB
2022-12-13 21:44:46 +00:00
lioncash
d53ddb73bf
OpcodeDispatcher: Handle VPMAXUD
2022-12-13 21:40:29 +00:00
lioncash
25e9333abb
OpcodeDispatcher: Handle VPMAXUW
2022-12-13 21:38:52 +00:00
lioncash
85766dd074
OpcodeDispatcher: Handle VPMAXUB
2022-12-13 21:36:47 +00:00
lioncash
b0e0a2a165
OpcodeDispatcher: Handle VPMINSD
2022-12-13 20:51:14 +00:00
lioncash