Ryan Houdek
1cf60f43cb
[AArch64] Implements vector integer length and narrow ops
2020-03-15 00:54:33 -07:00
Ryan Houdek
99d95d5bca
[AArch64] Implements float conversion ops
2020-03-15 00:53:49 -07:00
Ryan Houdek
deac8d5a75
[AArch64] Implements vector float compare ops
2020-03-15 00:52:43 -07:00
Ryan Houdek
823c803142
[AArch64] Fixes GPR<->FPR conversion moves
2020-03-15 00:45:50 -07:00
Ryan Houdek
702473d3a5
[AArch64] Implements vector shift by immediate ops
2020-03-15 00:44:35 -07:00
Ryan Houdek
4212d177a3
[AArch64] Fixes VSLI/VSRI for byte shifts larger than the register. Needs to zero the reg
2020-03-15 00:44:15 -07:00
Ryan Houdek
35317d0e8a
[AArch64] Fixes and implements vector shift ops
2020-03-15 00:43:06 -07:00
Ryan Houdek
a670d05274
[AArch64] Fixes VEXTR op
2020-03-15 00:42:11 -07:00
Ryan Houdek
8f1d5e9a4c
[AArch64] Fixes FRSQRT Op
2020-03-15 00:40:38 -07:00
Ryan Houdek
803bbe817e
[AArch64] Fixes FSQRT Op
2020-03-15 00:39:40 -07:00
Ryan Houdek
214728e19e
[AArch64] Implements vector saturating add/sub ops
2020-03-15 00:38:43 -07:00
Ryan Houdek
5530e9eb0e
[AArch64] Implements VUMULL IR op
2020-03-15 00:38:17 -07:00
Ryan Houdek
746f399e00
[AArch64] Implements VNOT op
2020-03-15 00:37:30 -07:00
Ryan Houdek
c79ee8314e
[AArch64] Implements SplatVector Ops
2020-03-15 00:37:14 -07:00
Ryan Houdek
cc68d1f88e
[AArch64] Implements VInsGPR Op
2020-03-15 00:36:51 -07:00
Ryan Houdek
180944a194
[AArch64] Fixes integer division and remainder ops
2020-03-15 00:35:09 -07:00
Ryan Houdek
9ae0930515
[AArch64] Implements FindTrailingZeros IR Op
2020-03-15 00:33:46 -07:00
Ryan Houdek
5f295ffc5e
[AArch64] Fixes FindMSB for 16bit and 32bit register sizes
2020-03-15 00:33:23 -07:00
Ryan Houdek
d75fed7691
[AArch64] Fixes ROR for 8bit and 16bit register sizes
2020-03-15 00:32:51 -07:00
Ryan Houdek
8686c0f269
[AArch64] Fixes Break IR op. No immediate offset on atomics.
2020-03-15 00:32:20 -07:00
Ryan Houdek
8c374142e6
[AArch64] Implements Load/Store context indexed
2020-03-15 00:31:25 -07:00
Ryan Houdek
1f112bccbb
[AArch64] Fixes VExtractToGPR for 8bit and 16bit sizes
2020-03-15 00:30:53 -07:00
Ryan Houdek
79ffd11c1d
Cleans up and renames the CVT ops
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Fixes issue #14 .
A lot of these were named in very confusing ways.
Makes them very explicit about what the operation is doing
2020-03-13 17:42:39 -07:00
Ryan Houdek
121bed017c
Merge pull request #24 from Sonicadvance1/fixes_jit_x86
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Various fixes for the x86 JIT
2020-03-13 15:52:48 -07:00
Ryan Houdek
0e80dc27cc
Merge pull request #21 from Sonicadvance1/movshdup
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Implements Movshdup instruction
2020-03-13 15:52:24 -07:00
Ryan Houdek
30338dd7f4
Merge pull request #20 from Sonicadvance1/pextrw
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Implements PExtrw instruction
2020-03-13 15:52:09 -07:00
Ryan Houdek
78bcf3960d
Merge pull request #19 from Sonicadvance1/psrl_family
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Implements PSRL{W,D,Q} instruction family
2020-03-13 15:51:58 -07:00
Ryan Houdek
4459a048f7
Merge pull request #18 from Sonicadvance1/Interpreter/vushr
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Removes undefined behaviour in the VUSHR in interpreter
2020-03-13 13:04:56 -07:00
Ryan Houdek
d5481efa6b
Fixes AtomicFetch{Add,Sub} for 8bit and 16bit ops in the x86 JIT
2020-03-12 22:13:53 -07:00
Ryan Houdek
600f43779c
Fixes and implements a couple vector shift ops in the x86 JIT
2020-03-12 22:13:17 -07:00
Ryan Houdek
12288ab887
Fixes VFCMPLE in x86 JIT
2020-03-12 22:12:34 -07:00
Ryan Houdek
2c44338478
Implements VFCMPNEQ in x86 JIT
2020-03-12 22:11:52 -07:00
Ryan Houdek
2e34f25257
Implements VSQXTUN and VSQXTUN2 in x86 JIT
2020-03-12 22:11:36 -07:00
Ryan Houdek
d0a7685bfa
Implements VUMULL in x86 JIT
2020-03-12 22:11:18 -07:00
Ryan Houdek
5bb93e5b8e
Implements VSQADD and VSQSUB in x86 JIT
2020-03-12 22:09:49 -07:00
Ryan Houdek
e3e62f3dd1
Fixes VInsGPR in x86 JIT
2020-03-12 22:09:21 -07:00
Ryan Houdek
6730d5601c
Fixes VExtractToGPR on x86 JIT
2020-03-12 22:08:30 -07:00
Ryan Houdek
739b471731
Implements signed/unsigned div/rem on x86 JIT
2020-03-12 22:07:36 -07:00
Ryan Houdek
42830d3e48
Merge pull request #22 from phire/fix_condslt
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Fix Signed LT in x86 jit
2020-03-12 22:02:12 -07:00
Scott Mansell
f2967e8ef9
OP_NEG/OP_NOT: add support for other opsizes.
2020-03-13 17:54:09 +13:00
Scott Mansell
99d1dcad98
Fix Neg IR_OP, Add Not IR_OP
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In some places, Neg meant logical one's complement negation.
In others it meant arithmetic two's complement negation.
As both x87 and aarch64 have neg instructions that do
two's complement negations, we will standardise on that.
Additionally we will add a Not_IR op for one's complement
2020-03-13 17:53:57 +13:00
Scott Mansell
ba4e311dc2
Fix Signed LT in x86 jit
2020-03-13 17:52:49 +13:00
Ryan Houdek
6069fcb9d4
Implements Movshdup instruction
2020-03-12 18:31:33 -07:00
Ryan Houdek
64dd3187d5
Implements PExtrw instruction
2020-03-12 18:28:29 -07:00
Ryan Houdek
612b74d001
Implements PSRL{W,D,Q}
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Saw this family when running mesa softpipe
2020-03-12 18:23:01 -07:00
Ryan Houdek
5cb9f9e0fa
Removes undefined behaviour in the VUSHR in interpreter
2020-03-12 18:20:12 -07:00
Stefanos Kornilios Mitsis Poiitidis
99399ecbac
Merge pull request #10 from Sonicadvance1/unittests/cmps
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Adds unit tests for the CMPS instruction family
2020-03-12 10:57:59 +02:00
Ryan Houdek
1b4ea20b17
Implements REPNE for SCAS
2020-03-10 18:21:16 -07:00
Ryan Houdek
a8f4e8a860
Implements CMPS support for REPNE and no prefix
2020-03-10 18:18:06 -07:00
Stefanos Kornilios Mitsis Poiitidis
963de98276
Merge pull request #7 from Sonicadvance1/unittests/primary_1
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Primary table unit tests and a couple fixes
2020-03-10 15:26:05 +02:00
Ryan Houdek