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4,962 Commits 11 Branches 71 Tags
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Commit Graph
1660 Commits
Author SHA1 Message Date
Ryan Houdek 2332c41510 Merge pull request #2119 from lioncash/tbl 
IR: Handle 256-bit VTBL1
 2022-10-26 20:44:23 -07:00
lioncash ec3039c5a2 IR: Handle 256-bit VTBL1 
Extends VTBL1 to handle 256-bit vectors.
 2022-10-27 00:35:45 +00:00
lioncash cd518d4726 Arm64/VectorOps: Make use of MOVPRFX where applicable 
Allows hardware to pack the move and following destructive operation
together into one constructive operation if possible.

e.g.

movprfx VTMP1.D, VectorLower.D
addp VTMP1.B, Pred, VTMP1.B, VectorUpper.B

is allowed to be merged as if it executed constructively like:

addp VTMP1.B, Pred, VectorLower.B, VectorUpper.B

if the hardware supports it. If it doesn't, then the instructions will
behave like a regular move and destructive addp operation separately.
 2022-10-26 21:38:48 +00:00
Ryan Houdek b7d9c00dff Merge pull request #2117 from lioncash/ins 
IR: Handle 256-bit VInsGPR
 2022-10-26 13:22:35 -07:00
lioncash 4b17575f5a IR: Handle 256-bit VInsGPR 
Extends VInsGPR to handle 256-bit vectors.
 2022-10-26 19:45:27 +00:00
lioncash d87ff5afa9 IR: Handle 256-bit VExtractToGPR 
Extends VExtractToGPR to handle 256-bit vectors.
 2022-10-26 17:43:31 +00:00
Ryan Houdek 62a24bd38f Merge pull request #2075 from Sonicadvance1/gpuvis_profiler 
FEXCore: Adds support for a timeline profiler interface
 2022-10-26 08:44:54 -07:00
Ryan Houdek 7e810233d9 Merge pull request #2112 from lioncash/ftoi 
IR: Handle 256-bit Vector_FToI
 2022-10-26 00:07:04 -07:00
Ryan Houdek 74e18f4317 Merge pull request #2114 from lioncash/vec 
Arm64/BranchOps: Remove unused std::vector
 2022-10-25 22:02:09 -07:00
lioncash 1eea95cf18 Arm64/BranchOps: Remove unused std::vector 
Removes a heap allocation for inline syscalls.
 2022-10-26 04:34:57 +00:00
lioncash 6804916697 IR: Check for invalid conversion masks in Float_FromGPR_S 
Previously this would silently ignore unhandled masks.
 2022-10-26 03:59:25 +00:00
lioncash 819e61bf14 IR: Handle 256-bit Vector_FToI 
Expands Vector_FToI to handle 256-bit vectors.
 2022-10-26 03:42:23 +00:00
Ryan Houdek b8f7e4c8ec Merge pull request #2111 from lioncash/ftof 
IR: Handle 256-bit Vector_FtoF
 2022-10-25 20:17:26 -07:00
lioncash 17bcc0eed4 IR: Handle 256-bit Vector_FtoF 
Extends Vector_FtoF to handle 256-bit vectors.
 2022-10-26 02:58:06 +00:00
lioncash 9273538955 IR: Handle 256-bit Vector_FToS 
Extends Vector_FToS to handle 256-bit vectors.
 2022-10-26 00:59:11 +00:00
lioncash 9750189def IR: Handle 256-bit Vector_FToZS 
Extends Vector_FToZS to handle 256-bit vectors.
 2022-10-26 00:53:53 +00:00
Ryan Houdek cb17ee9871 Merge pull request #2109 from lioncash/stof 
IR: Handle 256-bit Vector_SToF
 2022-10-25 17:14:16 -07:00
lioncash 4c3b78ba9a IR: Handle 256-bit Vector_SToF 
Extends Vector_SToF to handle 256-bit vectors.
 2022-10-25 23:54:41 +00:00
Ryan Houdek 27b022d4d9 Merge pull request #2106 from lioncash/dup 
IR: Handle 256-bit VDupElement
 2022-10-25 13:49:29 -07:00
lioncash e188928742 IR: Handle 256-bit VDupElement 
Extends VDupElement to handle 256-bit vectors.
 2022-10-25 20:01:53 +00:00
lioncash 1b5146d3ac IR: Handle 256-bit VUnZip2 
Extends VUnZip2 to handle 256-bit vectors.
 2022-10-25 16:01:55 +00:00
lioncash 80cf3ca6b9 IR: Handle 256-bit VUnZip 
Extends VUnZip to handle 256-bit vectors.
 2022-10-25 15:49:02 +00:00
Ryan Houdek ab45db1665 Merge pull request #2094 from lioncash/zip 
IR: Handle 256-bit VZip/VZip2
 2022-10-20 19:02:29 -07:00
Ryan Houdek bb38bcb67d Merge pull request #2093 from lioncash/shrn 
IR: Handle 256-bit VUShrNI/VUShrNI2
 2022-10-20 19:00:51 -07:00
lioncash 340b2ca624 IR: Handle 256-bit VZip2 
Extends VZip2 to handle 256-bit vectors.
 2022-10-20 21:15:18 +00:00
lioncash 5baa15de03 IR: Handle 256-bit VZip 
Extends VZip to handle 256-bit vectors.
 2022-10-20 19:22:07 +00:00
lioncash 6ddca804d1 IR: Handle 256-bit VUShrNI2 
Extends VUShrNI2 to handle 256-bit vectors.
 2022-10-20 18:31:36 +00:00
lioncash f9831a85fb IR: Handle 256-bit VUShrNI 
Extends VUShrNI to handle 256-bit vectors.
 2022-10-20 17:51:47 +00:00
lioncash 7261033b7f IR: Handle 256-bit VSQXTUN2 
Extends VSQXTUN2 to handle 256-bit vectors.
 2022-10-20 17:08:00 +00:00
lioncash 3ad6866198 IR: Handle 256-bit VSQXTUN 
Extends VSQXTUN to handle 256-bit vectors.
 2022-10-20 16:51:53 +00:00
Ryan Houdek 1c7d4165ab Merge pull request #2091 from lioncash/vsqxtn 
IR: Handle 256-bit VSQXTN/VSQXTN2
 2022-10-19 20:46:53 -07:00
Ryan Houdek 3e48b1a8ac FEXCore: Adds support for a timeline profiler interface 
This creates a generic interface that FEXCore can use for timeline
profiling. This allows us to create a generic interface which the
backend details are hidden so we can support multiple timeline profile
APIs.

The only API supported right now is ftrace/gpuvis. Which is extremely
lightweight of an interface with minimal overhead.

We must be careful here since in most cases will will have dozens of
FEX instances running at any given time. So a timeline profiler like
Microprofiler can have major issues since that only ever expects a
single process at a time.

Not enabled by default but just needs the `ENABLE_FEXCORE_PROFILER`
cmake option set to enable.
 2022-10-19 19:56:35 -07:00
lioncash 07be100daf IR: Handle 256-bit VSQXTN2 
Extends VSQXTN2 to handle 256-bit vectors.
 2022-10-20 02:41:45 +00:00
lioncash de9351eefb IR: Handle 256-bit VSQXTN 
Expands VSQXTN to handle 256-bit vectors.
 2022-10-20 02:04:05 +00:00
lioncash ad39add55f Arm64/VectorOps: Simplify VUXTL2 SVE implementation 
Turns out there's an instruction that does what we need, but isn't named
similarly to UXTL2 at all.
 2022-10-19 22:24:07 +00:00
lioncash f3c301e359 Arm64/VectorOps: Simplify VUXTL SVE implementation 
Turns out there's an instruction that does what we need, but has a name
not similar to UXTL
 2022-10-19 22:22:23 +00:00
lioncash 1c37a1b4d6 Arm64/VectorOps: Simplify VSXTL2 SVE implementation 
Turns out there's a built-in instruction that does exactly what we want,
but just has a different name from SXTL2
 2022-10-19 22:16:33 +00:00
lioncash 7222529904 Arm64/VectorOps: Simplify VSXTL SVE implementation 
Was reading the ARM ARM and realized there's an instruction that does
exactly what we need right out of the box.
 2022-10-19 22:12:22 +00:00
wannacu d4416d200e OpcodeDispatcher: Implements DAA, DAS, AAA, AAS, AAM and AAD instruction 2022-10-19 13:56:06 +08:00
Ryan Houdek 3ac5e0423a Merge pull request #2088 from lioncash/vsmull 
IR: Handle 256-bit VSMull/VSMull2
 2022-10-18 16:11:03 -07:00
Mai b1e475d81d Merge pull request #2081 from Sonicadvance1/fix_rotate_flags 
OpcodeDispatcher: Fixes flag calculation on ROR and ROL by immediate
 2022-10-18 22:33:47 +00:00
Mai 4a09a4324f Merge pull request #2082 from Sonicadvance1/fix_c2_fprem1 
OpcodeDispatcher: Fixes FPREM1 C2 flag calculation
 2022-10-18 22:33:29 +00:00
lioncash 47f94327c5 IR: Amend x86_64 32->64 case for VUMull2 
Realized I forgot to amend the registers used in the final multiply.
 2022-10-18 16:23:16 +00:00
lioncash a009ed0b6b IR: Handle 256-bit VSMull2 
Extends VSMull2 to handle 256-bit vectors.
 2022-10-18 16:23:14 +00:00
lioncash 2476a686e7 IR: Handle 256-bit VSMull 
Extends VSMull to handle 256-bit vectors.
 2022-10-18 16:22:44 +00:00
Ryan Houdek 78a077397e Merge pull request #2085 from lioncash/vmull 
IR: Handle 256-bit VUMull/VUMull2
 2022-10-17 18:10:48 -07:00
lioncash 0c4b456aaa IR: Handle 256-bit VUMull2 
Extends VUMull2 to handle 256-bit vectors.
 2022-10-17 19:03:26 +00:00
lioncash 09185167bc OpcodeDispatcher/Vector: Amend and simplify PMULLOp 
Allows PMULLOp to function correctly with the amended VPSHUFD entries.

Since this is only used to perform expanded multiplication from 32-bit
entries to 64-bit entries, we can simplify things a little bit.

All we need to do is yank the third 32-bit word down into the second
32-bit word's spot in the vector and let the VUMull/VSMull IR ops handle
it.
 2022-10-17 19:03:26 +00:00
lioncash 5d78c3203c IR: Handle 256-bit VUMull 
Extends VUMull to handle 256-bit vectors.

While we're at it, we can fix a typo in the VPSHUFD called for the
32->64-bit case.

To mirror UMULL, we need to replicate element 0 and 1, not 0 and 2

While we're at it, we can fix this with VSMull as well.
 2022-10-17 19:03:23 +00:00
Ryan Houdek 102d5c57cb OpcodeDispatcher: Fixes FPREM1 C2 flag calculation 
Accidentally didn't implement this for FPREM1 but it /was/ implemented
for FPREM. Fixes an infinite loop in cossin implementations.

Test code from the application returns an incorrect result, but it isn't
due to FPREM1.

```
$ `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos -1
$ FEXInterpreter `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos 0.54030230586814
```

Fixes #2021
 2022-10-16 15:24:46 -07:00